JP2853374B2 - Frame synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for synchronization pull-in means used for PCM transmission. In particular, it relates to means for avoiding false synchronization.

[0002]

2. Description of the Related Art In a conventional circuit, a bit pattern that matches a synchronization pattern a specified number of times has been regarded as a synchronization signal. That is, after guarding by the backward protection circuit, one of the remaining synchronization candidates is regarded as a synchronization signal, and when it is determined to be a false synchronization signal, the circuit is reset and the synchronization bit is searched again from the beginning, or Backward protection was continued until there was only one synchronization candidate.

[0003]

In such a conventional circuit, when the same pattern as the synchronization pattern is included in the PCM input data for a long period of time, there is a drawback that the synchronization cannot be obtained forever. there were. Since synchronization candidates exist in addition to the true synchronization pattern, in one method, do not proceed to the next state until there is one synchronization candidate,
Alternatively, in another method, a false synchronization pattern in PCM data is first captured, and the next state is reached, for example, a CRC (cyclic redundancy check) operation is performed. Resetting the synchronization circuit after knowing that the synchronization is detected from the beginning, the same false synchronization pattern may be captured again. There is a drawback that the false synchronization pattern is always captured depending on the timing relationship between the reset of the circuit and the false synchronization pattern.

An object of the present invention is to provide a frame synchronizing apparatus which reliably detects a true synchronizing pattern from a plurality of synchronizing candidates and guarantees data transparency. And

[0005]

According to the present invention, a PCM data is inputted by determining whether the synchronization signal is true or false and connecting the PCM data to a synchronization signal determination circuit for generating a control signal when the determination result is false. In a frame synchronization circuit having a first terminal and a second terminal for applying a frame pulse to the synchronization signal determination circuit, a shift register for holding PCM data passing through the first terminal and a shift register for holding the PCM data. A coincidence detection circuit for comparing a bit located at a synchronization bit interval included in PCM data with a synchronization pattern, and a cyclic register having a number of bits equal to the synchronization bit interval and in which all of the bits are initially set. Means for resetting the corresponding bit of the cyclic register when the result of comparison by the match detection circuit does not match. A self-running counter for applying a pulse having a constant cycle to the second terminal, a means for driving the self-running counter in response to a set bit output first from the cyclic register after measuring the time required for backward protection, and When the control signal is input from the signal determination means, the control signal is latched, and the corresponding bit of the cyclic register is reset at the timing of the output pulse of the self-running counter while the control signal is latched. Means for resetting the self-running counter and the latched control signal.

Here, it is desirable to have an initial state setting means for counting the number of set bits in the cyclic register and setting the own frame synchronization circuit to an initial state when the counted value indicates zero.

[0007]

In the PCM data stored in the shift register, bits at each synchronization bit arrangement interval are checked by a coincidence detection circuit, and the check results are sequentially stored in a cyclic register.
The first synchronization candidate detected after the end of the backward protection is regarded as a synchronization pattern. If it is determined that the synchronization is false, the operation of regarding the second synchronization candidate detected in the cyclic register up to that time as a synchronization pattern is true. Is repeated until the synchronization pattern is detected. This makes it possible to detect a true synchronization pattern even if a false synchronization pattern having the same bit pattern as the synchronization pattern exists continuously in the information data for a long time.

[0008]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block circuit diagram of this embodiment. In this embodiment, as shown in FIG. 1, a PCM for inputting PCM data is connected to a synchronization signal determination circuit that determines whether the synchronization signal is true or false and generates a control signal when the determination result is false. An input terminal 50 and a frame pulse output terminal 53 for applying a frame pulse to the synchronization signal determination circuit.
And further, as a feature of the present invention, P
A shift register 1 for holding PCM data via the CM input terminal 50, a coincidence detection circuit 2 for comparing a bit located at a synchronization bit interval included in the PCM data held in the shift register 1 with a synchronization pattern, A cyclic register 3 having a number of bits equal to the synchronization bit interval, all of which are initially set,
The AND circuit 11, which is a means for resetting the corresponding bit of the cyclic register 3 when the comparison result in the coincidence detection circuit 2 does not match, and a pulse generator for supplying a pulse having a cycle equal to the synchronization bit interval to the frame pulse output terminal 53. A running counter 6, a timer 5 and a AND circuit 1 which are means for driving the self-running counter 6 in accordance with a set bit which is first output from the cyclic register 3 after measuring a time required for backward protection.
When the control signal is input from the synchronization signal determination means, the control signal is latched, and the corresponding bit of the cyclic register 3 is output at the timing of the output pulse of the free-running counter 6 while the control signal is latched. The number of set bits in the register 7, the NAND circuit 8, the AND circuit 12, and the latch 7, which is a means for resetting the self-running counter 6 and the latched control signal, and resetting the count value to zero. A candidate number counter 4, an inverter 9, and an AND circuit 13, which are initial state setting means for setting the own frame synchronization circuit to an initial state when shown.

Next, the operation of this embodiment will be described. PC
The PCM data input from the M input terminal 50 is stored in the shift register 1 and sequentially shifted bit by bit.
Lead lines S1, S2,..., Sm are output from the shift register 1 at synchronization bit intervals, and are connected to m input terminals of the coincidence detection circuit 2. As an example, assume that the synchronization pattern is a 6-bit repetition of "0, 0, 1, 0, 1, 1", and that they are inserted one bit at a time in a 772-bit interval. Assuming that there are four lead lines S1, S2, S3 and S4, the total bit length of the shift register 1 is 772 bits × 3 blocks = 2316 bits, and one bit is taken out every 772 bits and a match detection circuit is obtained. Sent to 2.

FIG. 2 shows an example of the coincidence detecting circuit 2. Six 4-input AND circuits are provided so that the synchronization pattern can be detected from any bit position, and their inputs are equipped with inverters corresponding to the 4 bits of the synchronization pattern shifted one bit at a time. When any of the AND circuits detects a match with the synchronization pattern, the output of the AND circuit becomes "1" and the output line M of the 6-input OR circuit becomes "1". When all the six AND circuits detect a mismatch, the output line M becomes "0". If one of the six AND circuits detects a match when there is no bit error, then the AND circuits that detect the match for every 772 bits are shifted one by one, so that the output line M A "1" appears every 772 bits. Assuming that there are two synchronization candidates, there are two patterns of “1” appearing in the 772-bit cycle on the output line M. Therefore, if the time is limited to the 772-bit period, “1” appears on the output line M at this time. Are two. That is, the number of “1” in the 772 bit time indicates the number of synchronization candidates.

Returning to FIG. 1, the bit length of the cyclic register 3 is 772 bits, and all bits are initially "1". Since the output of the NAND circuit 8 is initially "1", the AND circuit 12 is open. When the matching circuit output line M is "1" after the start of the test, the output of the AND circuit 11 also becomes "1".
The bit corresponding to the bit position currently being checked in the cyclic register 3 remains "1". Conversely, when the output line M is "0", the corresponding bit of the cyclic register 3 is rewritten to "0" and stored. Once rewritten to "0", the bit position is not regarded as a synchronization pattern, and even if the output line M of the coincidence detection circuit 2 becomes "1", the output of the AND circuit 11 becomes "0" of the cyclic register 3. To "0", and the corresponding bit of the cyclic register 3 remains "0". The candidate counter 4 counts the number of synchronization candidates, and the initial count value is “772”. The count value indicates the number of "1" in the cyclic register 3. When the output line M of the coincidence detection circuit 2 is "0" and the output of the cyclic register 3 is "1", the corresponding bit of the cyclic register 3 is set. Is rewritten from "1" to "0", and at the same time, the output of the AND circuit 13 provided with the inverter 9 becomes "1", and the count value is counted down by "1". In this way, every time "1" of the cyclic register 3 is rewritten to "0", the count value decreases by "1". When all the bits of the cyclic register 3 become "0", the count value also becomes "0". This indicates that no synchronization candidate remains. This is a case where the true synchronization bit has an error and cannot be captured due to a bit error. In this case, the synchronization circuit is reset and all of the synchronization circuits are returned to the initial state, and the inspection is started again.

When the timer 5 counts the time required for backward protection from the start of the test, the output of the timer 5 becomes "1" and the AND circuit 14 is opened. Thereafter, "1" first appearing from the cyclic register 3 is regarded as a synchronization candidate, and the AND circuit 1
4 outputs “1” to drive the self-propelled counter 6.
The free running counter 6 has a frame synchronization bit interval of 772.
A one-bit pulse is generated for each bit. This is output from the frame pulse output terminal 53 as a frame synchronization pulse. Once the self-propelled counter 6 is driven, it is configured not to receive a subsequent drive input signal until reset. This is to prevent the self-running cycle from being disturbed even if there are a plurality of “1” in the cyclic register 3.

FIG. 3 shows an example of the configuration of the self-running counter 6.
When the output of the AND circuit 14 is "1", the AND circuit 61
Is initially open, so the 772-bit counter 62
Becomes "1", counts 772 bits with a clock CLK equal to the bit rate of the PCM input data, and circulates every 772 bits. When the enable terminal E becomes "1", the output Q of the counter 62 also becomes "1" immediately, and this is given to the latch terminal L of the latch 63,
Becomes "0", closes the AND circuit 61, and ignores the subsequent output of the AND circuit 14 even if it becomes "1". When the reset signal RST becomes "0", the counter 62 and the latch are both reset, and the self-running counter 6 returns to the initial state.

Returning to FIG. 1, when a frame pulse is generated, it is determined that frame synchronization has been established, and the process proceeds to the next state.
In the case of false synchronization, "1" is given to the control signal input terminal 52, and the output of the NAND circuit 8 indicates that the frame pulse is "1".
Becomes “0” at the timing when the AND circuit 12 is closed, and at that time “1” outputted from the cyclic register 3
Is rewritten to “0”, the candidate number count value of the candidate number counter 4 is reduced by “1”, and the self-running counter 6 and the control signal are reset. If the synchronization candidate still remains, the next “1” appearing from the cyclic register 3 is regarded as a synchronization candidate, and the self-running counter 6 is driven again to newly generate a frame pulse at the timing of the synchronization candidate. Thereafter, the true synchronization pattern is captured by repeating in the same manner.

Next, the operation of this embodiment will be described with reference to a time chart shown in FIG. FIG. 4 shows a case where there are two synchronization candidates between 772 bits of the synchronization frame interval.
After a lapse of a predetermined time from the start of the inspection, the output of the timer 5 becomes "1" and the rear protection end state is set. The inspection time is generally set to an integral multiple of the synchronization frame time, during which time only the bits of the cyclic register 3 that continuously match the synchronization pattern remain "1". In FIG. 4, two bits are "1". One of the two bits corresponds to a true synchronization pattern, and the other corresponds to a false synchronization pattern.
After the output of the timer 5 becomes "1", the cyclic register 3
Is a false synchronization pattern in this example,
At this point, no true or false judgment is made, and the present circuit regards the pattern as a synchronous pattern and generates a frame pulse from the self-running counter 6 (A). Thereafter, if it is determined by the CRC or the like that false synchronization is to be performed, the control input is set to "1", and a reset signal is generated from the output of the NAND circuit 8 by the output "1" of the self-running counter 6 which occurs first, and When the bit corresponding to the false synchronization bit of the register 3 is rewritten to “0”, the reset signal is released and the self-running counter 6 returns to the initial waiting state, and the count value of the candidate number counter 4 decreases by “1”. I do. Next, when "1" corresponding to the true synchronization pattern appears from the cyclic register 3, the self-running counter 6 is driven again by this "1" (c). In this way, a true synchronization pattern is finally detected, and a frame pulse corresponding to the pattern is generated.

The case of 772 bits has been described above as an example, but the same applies to other cases.

[0017]

As described above, according to the present invention, when a plurality of synchronization candidates still remain after the end of backward protection,
The synchronization candidate captured first is regarded as a synchronization pattern, but other synchronization candidates are held in the cyclic register without discarding, and when the current synchronization pattern is determined to be false synchronization, the synchronization candidate captured next is assumed. Is regarded as a synchronization pattern, so that there is an effect that it is not necessary to take a time for re-inspection and backward protection.

Further, since it can be repeatedly executed until a true synchronization pattern is found, the true synchronization pattern can be reliably detected even if the same data as the synchronization pattern is continuously received from the opposite transmitter for a long period of time. This has the effect of ensuring complete data transparency.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a connection diagram showing a configuration of a match detection circuit shown in FIG. 1;

FIG. 3 is a connection diagram showing a configuration of a self-running counter shown in FIG.

FIG. 4 is a tamming diagram showing the operation of the embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Shift register 2 Match detection circuit 3 Cyclic register 4 Candidate number counter 5 Timer 6 Self-running counter 7 Latch 8 NAND circuit 9 Inverter 11, 12, 13, 14 AND circuit 50 PCM input terminal 51 Restart control output terminal 52 Control signal input terminal 53 Frame pulse output terminal 61 AND circuit 62 Counter 63 Latch

Claims (2)

(57) [Claims] A first terminal for inputting PCM data, the first terminal being connected to a synchronization signal determining circuit for generating a control signal when the determination result is false, and determining the synchronization signal; In a frame synchronization circuit having a second terminal for applying a frame pulse to a hand circuit, a shift register for holding PCM data passing through the first terminal, and a synchronization bit interval included in the PCM data held in the shift register And a cyclic register having a number of bits equal to the synchronization bit interval and all of the bits being set in an initial state. Means for resetting the corresponding bit of the cyclic register when the result does not match; A self-running counter provided to a terminal, a means for driving the self-running counter in accordance with a set bit output first from the cyclic register after measuring a time required for backward protection, and a control signal from the synchronization signal determining means. At the time of input, the control signal is latched, and during the period in which the control signal is latched, the corresponding bit of the cyclic register is reset at the timing of the output pulse of the self-running counter. Means for resetting a signal. 2. The frame synchronization apparatus according to claim 1, further comprising an initial state setting means for counting the number of set bits in said cyclic register and setting an own frame synchronization circuit to an initial state when the counted value indicates zero. circuit.