JP2914321B2 - Error detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of an abnormality detection circuit for a frame pulse signal in a digital signal processing device.

[0002]

2. Description of the Related Art Conventionally, as such an abnormality detection circuit, there is an abnormality monitoring circuit as disclosed in Japanese Patent Application Laid-Open No. 6-28054. FIG. 7 shows a main configuration of the abnormality monitoring circuit. The abnormality monitoring circuit 30 connects the signal line through which the frame pulse signal FP flows to the load input terminal LD, and connects the signal line through which the clock signal CLK flows to the clock input terminal CK.
, And a comparison circuit 32 that connects the signal line through which the frame pulse signal FP flows to one input terminal Ia and connects the output terminal C of the counter 31 to the other input terminal Ib.

The counter 31 uses the input timing (for example, pulse rising timing) of the frame pulse signal FP input from the load input terminal LD as a starting point of the counting operation, and sets the pulse of the clock signal CLK input from the clock input terminal CK. The number is counted by an amount corresponding to the cycle of the frame pulse signal FP, and when the count value reaches the maximum count value of the counter 31, a high level (hereinafter, referred to as an output terminal C) from the output terminal C
(High level is expressed as “H” and low level is expressed as “L”)
_Is output. The comparison circuit 32 compares the frame pulse signal FP input from one input terminal Ia with the count-up signal C _{UP of the} counter 31 input from the other input terminal Ib, and
A comparison signal CM for judging whether or not the frame pulse signal FP is transmitted correctly at a constant period interval from
P is output.

Hereinafter, an operation example of the abnormality monitoring circuit 30 will be described with reference to FIG. For example, the counter 31 sets an initial count value based on the pulse rising timing of the frame pulse signal FP (see FIG. 2B) and counts the number of pulses of the clock signal CLK (see FIG. 2A). Start operation. The initial count value is the clock signal C in the cycle of the input frame pulse signal FP.
This value is set based on the number of pulses of LK. Each time the rising edge of the pulse of the clock signal CLK is detected, the count initial value is incremented by +1. When the count value reaches the maximum count value, the count-up signal C _UP (See FIG. 3C).

That is, if the frame pulse signal FP is normal, the pulse rising timing of the frame pulse signal FP and the counter 31 count up signal C _UP
Is output at the same time. Therefore, the frame pulse signal FP and the count-up signal C _UP
Is compared by the comparison circuit 32. If they match, the comparison signal CMP (see FIG. 3D) indicating the comparison result is set to “H”, and if they do not match, the comparison signal CMP is set to “L”. By referring to the comparison signal CMP at the timing when the frame pulse signal FP is detected, it is possible to detect whether the frame pulse signal FP is normal or abnormal.

For example, when a frame pulse signal FP is generated at a timing that does not originally occur, as shown by a white arrow X in FIG.
Does not coincide with the timing at which the counter 31 outputs the count-up signal C _UP , the comparison signal CMP becomes “L”, and it can be detected that the frame pulse signal FP at this time is abnormal.

[0007]

However, in such a conventional abnormality monitoring circuit 30, when the frame pulse signal FP is input, the counter 31 starts counting operation unconditionally based on the input timing. For example, when an abnormal pulse signal is received in which the pulse rising point of the frame pulse signal FP is shifted from the normal pattern, the counting start point of the counter 31 is also shifted, and the counter 31 outputs the frame pulse signal. FP
The output of the count-up signal C _UP cannot be performed correctly at the timing coincident with the output timing of.

When the output timing of the count-up signal C _UP from the counter 31 is shifted as described above, a normal pulse signal of the frame pulse signal FP input at the correct timing is received, and the shifted counting is performed. Until the start point is corrected to the correct count start point, even if a normal pulse signal is received, it cannot be detected that the pulse signal is a normal pulse signal, and the pulse signal is erroneously detected as an abnormal pulse signal. There was a problem that it would.

As a special example, when an abnormal pulse signal having a pulse rising point of the frame pulse signal FP coincident with a normal pulse signal but having a delayed pulse falling point and a different pulse width is received, Abnormality monitoring circuit 3
In the case of 0, the pulse rise points coincide with each other even though an abnormal pulse signal is received, so that the pulse signal is erroneously detected as a normal pulse signal. Further, when the frame pulse signal FP is continuously interrupted, the counter 31 cannot perform the counting operation based on the count initial value, and thus performs the counting operation at a period irrelevant to the period of the frame pulse signal FP. As a result, there is a problem that the abnormality of the frame pulse signal FP cannot be detected.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problem, and an object of the present invention is to provide an abnormality detecting circuit for quickly and accurately detecting normality or abnormality of a frame pulse signal FP.

[0011]

An abnormality detection circuit according to the present invention compares the pulse shape of an input frame pulse signal with a preset reference pulse shape to determine whether the pulse shapes are the same. When it is determined that the pulse shapes are the same as a result of the comparison determination by the shape comparison determining means and the shape comparison determining means, the operation is performed based on the pulse rising (or falling) timing of the frame pulse signal. A timer means for starting and outputting a time-up signal after a preset time, and when the output timing of the time-up signal from the clock means does not match the pulse rising (or falling) timing of the frame pulse signal, or When the shape of the frame pulse signal is different from the reference pulse shape as a result of the comparison and determination by the shape comparison and determination means It is configured with an abnormality detecting means for detecting the fact that there is an abnormality in the frame pulse signal FP.

In this case, the shape comparing / determining means includes a data extracting unit for extracting a pulse value at a continuous clock timing of the frame pulse signal based on a clock signal serving as a reference operation signal, and a frame extracted by the data extracting unit. The value of the pulse signal is compared with the value of a predetermined number of bit strings representing a predetermined reference pulse shape serving as a comparison reference, and when all values are the same, a comparison result indicating that the pulse shapes are the same It is effective to provide a comparison / determination unit that outputs a signal and outputs a comparison / determination result signal indicating that the pulse shape is different when any one of the values is different.

The time counting means counts the number of pulses of a clock signal serving as a reference operation signal from a preset initial count value to a predetermined count value. A counter that outputs an up signal,
It is preferable to have an initial value setting unit that sets the initial count value of the counter so that the count time from the initial count value by the counter to the predetermined count value is equal to the cycle of the frame pulse signal. When the pulse shapes are the same based on the comparison / determination result signal output from the shape comparison / determination means, it is effective to provide an initial count value updating means for updating the count value of the counter to the initial count value.

The abnormality detecting means includes a first AND circuit for obtaining a logical product of the frame pulse signal and the time-up signal from the timing means, a comparison result signal from the shape comparing / determining means and a time from the timing means. It is effective to have a second AND circuit for obtaining a logical product with the up signal.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on one illustrated embodiment. FIG. 1 is a diagram illustrating a schematic configuration of an abnormality detection circuit according to the present embodiment. The abnormality detection circuit 1 in the present embodiment is roughly divided into a frame pulse pattern comparison circuit 2 serving as a shape comparison / determination means, a frame pulse cycle counter 3 serving as a time measuring means, and a frame pulse cycle comparison circuit 4 serving as an abnormality detection means. It is constituted so that it may be provided.

FIG. 2 is a diagram showing a main configuration of the abnormality detection circuit shown in FIG. As shown in FIG. 2, the frame pulse pattern comparison circuit 2 includes a shift register 5 serving as a data extraction unit and a comparator 6 serving as a comparison determination unit.
The frame pulse cycle counter 3 includes a counter 7, an initial value setting unit 8, and an OR gate 9 serving as an initial count value updating unit.
The frame pulse period comparison circuit 4 includes an AND gate 11 serving as a first logic circuit and an AND gate 12 serving as a second logic circuit.

In the present embodiment, the pattern shape of the frame pulse signal FP is represented by a 3-bit bit string "010", and the frame pulse pattern comparison circuit 2 has a delay time of one clock. The shift register 5, the counter 7, and the like use the pulse rising timing as an operation reference point, and the operation between clocks is in-phase logic.

The frame pulse pattern comparison circuit 2 compares the pulse shape of the input frame pulse signal FP with a preset reference pulse shape to determine whether or not each pulse shape is the same. It is. Specifically, the shift register 5 inputs the frame pulse signal FP to the serial input terminal SI, inputs the clock signal CLK to the clock input terminal CP, and outputs the frame pulse signal FP 'delayed by one clock to the output terminal Q. outputs from _0, and outputs the frame pulse signal FP "delayed by two clocks from the output terminal Q _1.

The comparator 6 outputs the frame pulse signal F
By inputting P to the data input terminal A ₀ and inputting the outputs from the output terminals Q ₀ and Q _{1 of the} shift register 5 to the data input terminals A ₁ and A ₂ respectively, the frame pulse signal FP to be compared Enter the pulse shape of
Further, by giving a reference pulse shape as a comparison reference to the data input terminals B _{0 to} B ₂ by a 3-bit bit string “010”, each data value and data input to the data input terminals A _{0 to} A ₂ are changed. The data values input to the input terminals B _{0 to} B ₂ are compared with each other, and if all the values are the same, a comparison result signal CMP of “H” indicating that the pulse shapes are the same from the output terminal EQ is output. Is output. On the other hand, if any one of the values is different, “L” indicating that the pulse shape is different
Is output.

When the comparison / determination result signal CMP output from the frame pulse pattern comparison circuit 2 becomes "H" and it is determined that the pulse shapes are the same, the frame pulse period counter 3 outputs the frame pulse signal FP. The operation is started based on the pulse rising timing, and a carry-out signal (time-up signal) C _UP is output after a predetermined time. Specifically, the counter 7 inputs the output signal from the OR gate 9 to the load input terminal L, inputs the clock signal CLK to the clock input terminal CK, and uses the signal input to the load input terminal L as a trigger, From the initial value setting unit 8 to the data input terminal D ₀
To D _n results began to incremented by +1 the initial count provided to the carry-out signal C _UP of "H" from the output terminal CO when the count value has reached the maximum count of counter 7
Is output.

The initial value setting section 8 sets the initial count value of the counter 7 so that the counting time from the initial count value to the maximum count value of the counter 7 becomes equal to the cycle of the frame pulse signal FP. The output signal of the comparator 6 is input to one input terminal of the OR gate 9, and the output signal of the AND gate 10 is input to the other input terminal. Also, at one input terminal of the AND gate 10,
An inverted signal of the output signal of the comparator 6 is input, and an output signal from the output terminal CO of the counter 7 is input to the other input terminal.

As a result, the comparison determination result signal C of "H" indicating that the pulse shapes are the same is output from the comparator 6.
When MP is output, a trigger signal is input from the OR gate 9 to the load input terminal L of the counter 7, and the counter 7 updates the current count value to the initial count value and starts the counting operation. On the other hand, when the comparator 6 outputs the comparison determination result signal CMP of “L” indicating that the pulse shapes are different, the counter 7 executes the counting operation as it is without changing the current count value. When the carry-out signal C _UP is output, the current count value is updated to the initial count value. That is, when the pattern shape of the frame pulse signal FP is different from the reference pulse shape, counting is performed based on the counting start point in the previous cycle. That is, the current count value of the counter 7 is updated to the initial count value when the comparison determination result signal CMP from the comparator 6 becomes “H” and when the carry-out signal C _UP from the counter 7 becomes “H”. "
Only when

The frame pulse period comparator circuit 4, when the pulse rise timing of the output timing and the frame pulse signal FP carry-out signal C _UP of output from the counter 7 "H" is a mismatch, or, from the comparator 6 When the comparison determination result signal CMP is "L", it is detected that the frame pulse signal FP is abnormal. More specifically, the AND gate 11 has one input terminal that outputs an output signal from the output terminal Q ₀ of the shift register 5,
That is, the frame pulse signal FP delayed by one clock to input the timing is input, and the inverted signal of the carry-out signal C _UP from the counter 7 is input to the other input terminal. The AND gate 12 has one input terminal receiving the comparison / determination result signal CMP from the comparator 6 and the other input terminal receiving the carry-out signal C _UP from the counter 7 as it is.

As a result, the AND gate 11
Carry-out signal C from the counter 7 _UPIs “L”
Generated during periods other than the cycle timing of the frame pulse signal FP
Detecting errors in the generated frame pulse signal FP
Output “L” during normal operation and “H” during abnormal operation.
U. Similarly, the AND gate 12 outputs the key from the counter 7.
Carry-out signal C_UPPulse signal when the signal becomes “H”
Frame pulse signal generated at the cycle timing of signal FP
FP error can be detected, "H" at normal time,
In the case of an abnormality, “L” is output. That is, andge
The output from the port 11 becomes "H", or
When the output from the gate 12 becomes “L”, the frame
Abnormality of pulse signal FP can be detected
You.

Next, an example of the operation of the abnormality detection circuit 1 in the above-described embodiment will be described with reference to FIGS. 3 to 6 based on various frame pulse signals FP. FIG. 3 is a timing chart showing output signals from each block when a normal frame pulse signal is received. If the frame pulse signal FP is normal, the frame pulse signal FP
And (FIG. (B) refer) output signal FP from the output terminal Q ₀ of the shift register 5 with a delay of one clock from the input of '(see FIG. (C)), the comparison determination result signal C of the comparator 6
MP (see FIG. 4D) is both "H". At this time, the counter 7 sets the carry-out signal C in synchronization with the pulse rising timing of the frame pulse signal FP.
_{Since UP} (see FIG. 7E) is set to “H”, the output signal DE ₀ from the AND gate 11 (see FIG. 7F) is “L”, and the output signal DE ₁ from the AND gate 12 (see FIG. FIG. 7 (g) shows “H” and the frame pulse signal FP
Is detected as normal.

(Frame pulse signal with pulse missing abnormality)
FIG. 4 shows a frame pallet with a pulse missing abnormality.
Output signal from each block when the
FIG. In the figure, as shown by arrow A,
The pulse is skipped in the frame pulse signal FP (see FIG.
Input of frame pulse signal FP
Output terminal Q of shift register 5 delayed by one clock from ₀Or
The output signal FP '(see FIG. 3C) becomes "L".
You. Therefore, the bit string to be compared by the comparator 6 is
Becomes “000” and the comparison result signal
The signal CMP (see FIG. 3D) becomes “L”. Then
The counter 7 has a period counter of the frame pulse signal FP of the previous period.
Carry-out signal C based on the _UP(The same figure
(See (e)) Since it is set to “H”, the AND gate 11
Output signal DE₀(Refer to (f) in the figure) becomes “L”.
Indicates normal, but the output signal DE from the AND gate 12₁
(See (g) in the figure) is “L”, so the frame
Then, a detection result that the signal FP is abnormal is obtained.

(Frame pulse signal with abnormal pulse generation)
Fig. 5 shows a frame pallet with abnormal pulse generation.
Output signal from each block when the
FIG. As shown by arrow B in FIG.
A pulse is generated in the frame pulse signal FP (see FIG.
When a raw abnormality occurs, input of frame pulse signal FP
Output terminal Q of shift register 5 delayed by one clock from ₀Or
The output signal FP '(see FIG. 3C) becomes "H".
You. Therefore, the bit string to be compared by the comparator 6 is
It becomes “010” and the comparison judgment result signal of the comparator 6 is output.
The signal CMP (see FIG. 3D) becomes “H”. But,
This pulse generation timing is based on the frame pulse signal FP.
Counter 7
Carry-out signal C from_UP(See (e) in the figure)
It remains at "L". Therefore, AND gate 12
Output signal DE₀(See (f) in the figure) becomes “H”.
Indicates normal, but the output signal DE from the AND gate 11 is
₁(See (g) in the figure) becomes “H”, so that the frame
A detection result indicating that the luth signal FP is abnormal is obtained.

In this case, the initial count value of the counter 7 is updated when the comparison determination result signal CMP from the comparator 6 becomes "H", so that at the pulse rising timing of the next frame pulse signal FP, The carry-out signal C _UP from the counter 7 becomes “L”, the output signal from the AND gate 11 becomes “H”, and a detection result indicating that the frame pulse signal FP is abnormal is obtained again.
Then, based on the "H" comparison / determination result signal output from the comparator 6 at this time, the counter 7 sets the initial count value at a correct timing thereafter, and detects whether the frame pulse signal FP is normal or abnormal. .

(Frame pulse signal with abnormal pulse shape)
FIG. 6 shows a frame pallet having an abnormal pulse shape.
Output signal from each block when the
FIG. As shown by arrow C in FIG.
A pulse form is used for the frame pulse signal FP (see FIG.
Input of frame pulse signal FP
Output terminal Q of shift register 5 delayed by one clock from ₀You
And Q₁The output signal FP 'from FIG.
And FP ”are both set to“ H ”.
6 is “011” and the comparison bit string is “011”.
The comparison / determination result signal CMP (see FIG.
It becomes “L”. As a result, the AND gate 12
Output signal DE₀(Refer to (f) in the figure) becomes “L”, and
Obtained a detection result indicating that the frame pulse signal FP was abnormal.
You. In this case, the abnormal shape pulse generation timing
Is the normal occurrence timing in the frame pulse signal FP
Carry out from counter 7
Signal C_UP(See (e) in the figure) becomes “H”.
It becomes "L" at the lock timing. This allows
Output signal DE from the gate 11₁(See (g)
) Becomes “H”, so even at the next clock timing
Obtain a detection result indicating that the frame pulse signal FP is abnormal
Can be

As described above, in the present embodiment, the pulse shape of the frame pulse signal FP input by the frame pulse pattern comparison circuit 2 is checked, and an input signal having a pulse shape different from the reference pulse shape is determined to be abnormal. Therefore, if an abnormal pulse signal having a different pulse width is received even if the pulse rising point of the frame pulse signal FP coincides with the pulse rising point of the normal pattern, it is determined that the frame pulse signal FP is normal. There is no false detection. In this case, even if the pulse shape of the frame pulse signal FP input to the frame pulse pattern comparison circuit 2 is normal, the pulse rising of the frame pulse signal FP is performed based on the carry-out signal C _UP from the counter 7. Since a pulse signal generated at a timing other than the timing is determined to be abnormal, it is possible to prevent erroneous detection when detecting a normal or abnormal frame pulse signal.

Further, since the counter 7 continues the counting operation at the previous cycle timing even if the frame pulse signal FP is continuously interrupted, the counter 7 immediately receives an invalid frame pulse signal even if it receives an invalid frame pulse signal. Normal or abnormal detection of the frame pulse signal can be performed, and abnormality of the frame pulse signal FP can be reliably detected.
The counter 7 updates the initial count value correctly in the cycle of the next frame pulse signal FP even if the initial count value is erroneously updated due to the occurrence of the abnormal pulse signal. Detection can be performed quickly.

In the above-described embodiment, the case where the pulse shape of the frame pulse signal FP is represented by three bits of "010" has been described as an example. However, the number of bits and the bit pattern in this case are arbitrary. If you increase the number of bits,
This can be handled by increasing the number of stages of the shift register 5 and the number of bits to be compared by the comparator 6. Similarly, the delay time (1 clock), the operation timing point (pulse rise), the in-phase logic of the operation between the clocks, and the like of the signals compared in the frame pulse period comparison circuit 4 are variously changed according to the desired circuit configuration. It goes without saying that it is possible.

In the above-described embodiment, the AND gate 1
The case where it is determined that the frame pulse signal FP has an abnormality when the output signal DE ₀ from 1 is “H” or when the output signal DE ₁ from the AND gate 12 is “L” is illustrated. However, the present invention is not limited to this, and the determination logic may be changed by changing the input polarity. Further, the output signal DE ₀ of the AND gate 11 and the inverted signal of the output signal DE ₁ of the AND gate 12 are input to one OR gate, so that the output signal of “H” output from the OR gate is obtained. , The frame pulse signal F
You may comprise so that abnormality of P may be detected.

Further, in the above-described embodiment, the function of the frame pulse period counter 3 serving as the time measuring means is realized by using the addition type counter 7, but the function of the frame pulse signal FP is realized by using the subtraction type counter. The trigger signal may be input to the load input terminal L using a counter whose count period up to the maximum count value completely coincides with the frame pulse signal FP, although the versatility may be lost. Is input to a reset terminal (not shown), so that the initial value setting unit 8 can be omitted.

[0035]

As is apparent from the above description, according to the present invention, it is possible to prevent erroneous detection when performing normal or abnormal detection of a frame pulse signal. In addition, a period during which normal or abnormal detection of the frame pulse signal cannot be performed due to erroneous detection is eliminated, and it is possible to quickly detect whether the frame pulse signal is normal or abnormal.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a schematic configuration of an abnormality detection circuit according to an embodiment.

FIG. 2 is a diagram showing a main configuration of the abnormality detection circuit shown in FIG. 1;

FIG. 3 is a timing chart showing output signals from each block when a normal frame pulse signal is received.

FIG. 4 is a timing chart showing an output signal from each block when a frame pulse signal having a pulse missing abnormality is received.

FIG. 5 is a timing chart showing output signals from respective blocks when a frame pulse signal having a pulse generation abnormality is received.

FIG. 6 is a timing chart showing output signals from each block when a frame pulse signal having a pulse shape abnormality is received.

FIG. 7 is a diagram showing a main configuration of a conventional abnormality monitoring circuit.

FIG. 8 is a timing chart for explaining an operation example of a conventional abnormality monitoring circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Abnormality detection circuit 2 Frame pulse pattern comparison circuit (shape comparison judgment means) 3 Frame pulse cycle counter (time measurement means) 4 Frame pulse cycle comparison circuit (error detection means) 5 Shift register (data extraction part) 6 Comparator (comparison judgment part) 7) Counter 8 Initial value setting section 9 OR gate 10 AND gate 11 AND gate (first logic circuit) 12 AND gate (second logic circuit)

Claims (5)

(57) [Claims] 1. A pulse shape of a frame pulse signal serving as an input signal is compared with a preset reference pulse shape.
A shape comparison / judgment unit for judging whether or not each pulse shape is the same; and a comparison judgment by the shape comparison / judgment unit. A time-measuring means for starting an operation from a predetermined time and outputting a time-up signal after a predetermined time, and when the output timing of the time-up signal from the time-measuring means does not coincide with the input timing of the frame pulse signal, or An abnormality detection circuit, comprising: abnormality detection means for detecting that there is an abnormality in the frame pulse signal when the shape of the frame pulse signal is different from the reference pulse shape as a result of the comparison judgment by the comparison judgment means. 2. A data extraction unit for extracting a pulse value at a continuous clock timing of a frame pulse signal based on a clock signal serving as a reference operation signal, wherein the shape comparison determination unit extracts the pulse value from the data extraction unit. The value of the frame pulse signal is compared with the value of a predetermined number of bit strings representing a predetermined reference pulse shape serving as a comparison reference. When all values are the same, a comparison that the pulse shape is the same is made. 2. The abnormality detection circuit according to claim 1, further comprising a comparison / determination unit that outputs a result signal and outputs a comparison / determination result signal indicating that the pulse shape is different when any one of the values is different. 3. The time counting means counts the number of pulses of a clock signal serving as a reference operation signal from a preset initial count value to a predetermined count value, and when the count value reaches the predetermined count value, A counter that outputs a time-up signal; and an initial value setting unit that sets an initial count value of the counter so that a counting time from an initial count value by the counter to a predetermined count value is equal to a cycle of a frame pulse signal. The abnormality detection circuit according to claim 1, further comprising: 4. An initial count value updating unit that updates a count value of the counter to an initial count value when the pulse shapes are the same based on a comparison determination result signal output from the shape comparison determination unit. 4. The abnormality detection circuit according to claim 3, further comprising means. 5. An abnormality detecting means, comprising: a first AND circuit for calculating a logical product of a frame pulse signal and a time-up signal from the timing means; and a comparison / determination result signal from the shape comparison / determination means; A second AND circuit for obtaining an AND with a time-up signal from the means.
Abnormality detection circuit as described.