JPH05244146A - Frame synchronization detecting circuit - Google Patents

Abstract

PURPOSE:To settle the so-called the front protection and the rear protection with a simple circuit by deciding a continuous detection state which shows the coincidence of synchronization and a continuous non-detection states showing the discordance of synchronization. CONSTITUTION:A frame synchronization detecting circuit detects a frame synchronizing code out of a digital data string and decides the settlement of the front protection and the rear protection. An N-bit shift register 1 is added to the frame synchronization detecting circuit to output N shift signals in parallel with each other when the frame synchronizing codes are successively shifted one by one bit and the coincident frequency of the rear protection is set at N (N: an integer of >=3). Furthermore this circuit is provided with an AND circuit 2 for outputting a rear protection settlement signal when the N shift signals are all set at levels '1', the NOT circuits 5A and 5B which output the first L shift signals (2<=L<N) in parallel with each other and inverts these signals out of the N shift signals, and an AND circuit 3 which outputs a front protection settlement signal when the inputted output signals of both circuits 5A and 5B are all set at levels '1'.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization detection circuit, and more particularly to a frame synchronization detection circuit which realizes the determination of forward / backward protection of a frame synchronization code on the receiving side of a digital data transmission device with a simple circuit. ..

[0002]

2. Description of the Related Art Generally, as is well known, in the case of the backward protection characteristic, the determination of frame synchronization establishment is such that the synchronization code continues to match a predetermined number of times (for example, L times) in comparison with the reference synchronization pattern. If it is determined that the synchronization is established, a set signal is sent. On the other hand, in the case of the forward protection characteristic, if the synchronization codes do not match for a predetermined number of times (for example, M times) compared with the reference synchronization pattern, it is determined that the synchronization is lost, and the reset signal is sent again to start the synchronization determination operation. Send out.

Conventionally, this type of frame synchronization detection circuit is
As shown in FIG. 3, the synchronization code detection pulse signal output each time a match occurs and the non-detection pulse signal output each time a mismatch occurs are input, and the continuous detection counter 101
And the continuous non-detection counter 102. When the continuous detection counter 101 counts the pulse signals indicating L times of coincidence, the set signal 113 is output. Further, when the continuous non-detection counter 102 counts the pulse signals indicating the mismatches M times, the reset signal 114 is output. This set signal 1
13 or the reset signal 114 is input and the flip-flop 103 is driven to output the synchronization state signal 115.

[0004]

Since this conventional frame synchronization detection circuit uses a counter, it is necessary to accurately determine the timing of counting and the like, which has the drawback of complicating the circuit configuration. ..

[0005]

A frame synchronization detection circuit of the present invention is a frame synchronization detection circuit for detecting a frame synchronization code in a frame digital data sequence to determine whether front protection or backward protection is established. When the code is sequentially shifted bit by bit and the number of backward protection matches is N (N is an integer of 3 or more), the N bit shift register for outputting N shift signals in parallel and the N shift signals are all " An AND circuit that outputs a backward protection establishment signal in the case of 1 "level, and a NOT circuit that inputs and inverts the first L (2≤L <N) shift signals of the N shift signals in parallel , And an AND circuit which inputs the output signal of the NOT circuit and outputs a front protection establishment signal when all are "1" level.

[0006]

The present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a timing chart of signals for explaining the present embodiment. The embodiment shown in FIG. 1 inverts shift signals 12A and 12B to a 6-bit shift register (generally N bits, but N = 6 is illustrated) 1 and an AND circuit 3 which determines backward protection. It is composed of NOT circuits 5A and 5B.

Next, the operation of this embodiment will be described. First, as a condition for synchronization protection, two stages of forward protection (M =
2) For example, a case of 5 stages of backward protection (L = 2) in which matching is continued 5 times is taken as an example. Further, the sync code detection code pulse when the outputs of the shift register 1 match is set to the "1" level, and the sync code non-detection code pulse when they do not match is set to "0". Figure 2
, The frame synchronization continues for 4 cycles, and the cycle synchronization codes of the input signal 11 having the code detection information for frame synchronization are 1, 2, 3, 4 on a first-come-first-served basis. (Not used) shift signals 12A to 12
E is output to each line. This shift signal 12A-1
2E is shifted bit by bit as shown in FIG. 2, and the five information signals 3, 2, 1, ... Of the second column of the shift signals 12A, B, C to E are input to the AND circuit 2 in phase. It Further, the shift signals 12A and 12B are the NOT circuits 5A and 5B.
It is inverted by and input to AND3. Now shift signal 1
If all 5 of 2A and 12E are at the "1" level indicating coincidence, it is determined that the backward protection 5 stages are established, the synchronous code detection signal 14 is output to the output of the AND circuit 2, and a flip-flop (not shown) is operated to set. Output a signal. On the other hand, if the first two signals of the shift signals 12A and 12B are all "0" level indicating non-coincidence, it is determined that the two front protection stages are established, and the inversion signal (from "0" to "1") to the AND circuit 3 causes the synchronization code. The non-detection signal 15 is output, and the reset signal is output from the flip-flop.

It is possible to determine the synchronization by using two logic circuits without using the conventional counter circuit, but the number of stages L and M of the backward protection and the forward protection can be set to arbitrary values depending on the reliability of the synchronization determination.

[0009]

As described above, the frame synchronization detection circuit of the present invention is provided with the shift register and the AND circuit, so that it is possible to determine the continuous detection state indicating the synchronization match and the continuous non-detection state indicating the mismatch. There is. Further, there is an effect that these judgments can be realized by a simpler logic circuit than the conventional example.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a timing chart of each signal in the present embodiment.

FIG. 3 is a block diagram of a conventional frame synchronization detection circuit.

[Explanation of symbols]

 1 6-bit (N = 6 bits) shift register 2, 3 AND circuit 5A, 5B NOT circuit 101 continuous detection counter 102 continuous non-detection counter 103 flip-flop

Claims (2)

[Claims] 1. A frame synchronization detection circuit for detecting a frame synchronization code in a frame digital data sequence to determine whether forward and backward protection is established, wherein the frame synchronization code is sequentially shifted by one bit and backward protection is matched. An N-bit shift register that outputs N shift signals in parallel when the number of times is N (N is an integer of 3 or more), and a backward protection establishment signal is output when all of the N shift signals are at "1" level. AND circuit, a NOT circuit for inputting and inverting the first L (2 ≦ L <N) shift signals of the N shift signals in parallel, and an output signal of the NOT circuit for input A frame synchronization detection circuit, comprising: an AND circuit that outputs a front protection establishment signal when the level is "1". 2. The value of N in the N-bit shift register is set to a large value in order to maintain the relationship of N> L, and the value of N is sequentially monitored while observing the reliability of determination of backward protection establishment. The frame synchronization detection circuit according to claim 1, wherein the frame synchronization detection circuit can be changed.