JP2814978B2 - Frame synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a frame synchronization circuit used in a receiving section in digital data transmission.

[0002]

2. Description of the Related Art Conventionally, in digital data transmission,
A frame synchronization is established by inserting a frame pulse into a data signal in a transmission unit and detecting the frame pulse in a reception unit (for example, Japanese Patent Application Laid-Open No. 61-4 / 1986).
No. 1244). A conventional example will be described with reference to the drawings. FIG. 2 is an explanatory diagram showing an example of a configuration of a received digital data signal. In the figure, (a) shows a clock signal, and (b) shows a digital data signal. One word of the digital data signal includes bits D1 to D8 which are data portions.
And a 1-bit frame pulse added to one end thereof, for a total of 9 bits. The frame pulse is added so that "0" and "1" appear alternately between words.

FIG. 3 is a block diagram showing a conventional frame synchronization circuit. Reference numeral 1 denotes a reference pulse generation circuit that includes a counter 2 and an AND element 3 and outputs a reference pulse c generated by dividing the supplied clock signal by N. Here, N = 9. Reference numeral 4 denotes a shift register to which a digital data signal and a clock signal are supplied, and which performs a bit shift of the digital data signal in one cycle of N bits in synchronization with the clock signal.

[0004] Reference numeral 5 denotes a first (Q1)-(1) among digital data signals bit-shifted by the shift register 4.
This is a latch element that latches the Nth (Q9) and outputs it in parallel. Reference numeral 6 denotes the 0th (Q0) output and the Nth (Q9) of the digital data signals output from the shift register 4.
Are different from each other, the coincidence pulse i
Are output, and if they have the same logic, a mismatch pulse j
Is an exclusive OR element (hereinafter, referred to as an EX-OR element).

Reference numeral 7 denotes an AND element for calculating the logical product of the coincidence pulse i and the reference pulse c. Reference numeral 8 denotes the number of coincidences between the logic of the coincidence pulse i and the logic of the reference pulse c when the output of the AND element 7 is supplied. , Is a coincidence counter for comparing this count value with a predetermined set value N1 (first set value). Reference numeral 9 denotes an AND element that calculates the logical product of the mismatch pulse j and the reference pulse c. Reference numeral 10 denotes the number of matches between the logic of the mismatch pulse j and the logic of the reference pulse c when the output of the AND element 9 is supplied. This is a mismatch counter for comparing a numerical value with a predetermined set value N2 (second set value). Note that N1, N2
Are arbitrary natural numbers, where N1 = 8, N
2 = 4.

Reference numeral 11 indicates that when a pulse is supplied to the set terminal (S terminal), the output of the Q terminal is held at logic "1 (first logic)", and when a pulse is supplied to the reset terminal (R terminal). This is a flip-flop that holds the output of the Q terminal at logic “0 (second logic)”. 12 is a NOR element, 13 is O
The R element 14 is a NOT element. Reference numeral 17 denotes a hunting pulse generation circuit which includes a shift register 15 and an OR element 16, receives the output of the flip-flop 11 and a clock signal, and generates and outputs a hunting pulse.

The operation of the conventional example having the above configuration will be described in detail. The reference pulse generation circuit 1 outputs a reference pulse c by dividing the supplied clock signal by N using a counter 2.

The shift register 4 is supplied with a digital data signal and a clock signal, and bit-shifts the digital data signal in synchronization with the clock signal with one cycle being N bits. The 0th (Q0) output and the Nth (Q9) output of the bit-shifted digital data signal are E
When the two logics are different from each other, that is, when (0, 1) or (1, 0), EX-OR
The OR element 6 outputs a coincidence pulse i. Also, when both logics match, that is, (0, 0) or (1,
In the case of 1), a mismatch pulse j is output.

The AND element 7 is supplied with the reference pulse c and the coincidence pulse i, and takes a logical product of them. At this time, if the logic of the reference pulse c is “1” and the logic of the coincidence pulse i is “1”, the synchronous coincidence pulse a is output and the count value of the coincidence counter 8 is counted up. By counting up, the count value becomes a predetermined set value N1 (= 8).
, A pulse is output from the Q3 terminal. This pulse is supplied to the flip-flop 11 via the NOR element 12, and resets the flip-flop 11. Further, this pulse is simultaneously supplied to the coincidence counter 8 and the non-coincidence counter 10 via the OR element 13, and resets each count value of both to "0".

Similarly, the AND element 9 is supplied with the reference pulse c and the mismatch pulse j, and takes the logical product of the two. At this time, if the logic of the reference pulse c is “1” and the logic of the mismatch pulse j is “1”, the synchronization mismatch pulse b is output and the count value of the mismatch counter 10 is counted up. When the count value reaches a predetermined set value N2 (= 4) by counting up, a pulse is output from the Q2 terminal. This pulse is supplied to the flip-flop 11 via the NOT element 14, and sets the flip-flop 11. Further, this pulse is simultaneously supplied to the coincidence counter 8 and the non-coincidence counter 10 via the OR element 13, and resets each count value of both to "0".

The flip-flop 11 is set to Q
When the output of the terminal changes from logic “0” to “1”, the outputs of the Q0 and QN1 terminals of the shift register 15 become c
The data is shifted in synchronization with the clock signal supplied from the terminal and supplied to the AND element 16. AND element 16
The hunting pulse h is generated and output by taking the logical product of the output of the Q0 terminal and the output of the QN1 terminal. The hunting pulse h is supplied to the OR element 3 to shift the reference pulse c by one bit, and at the same time, to the NOR element 12.
To the flip-flop 11 to reset the flip-flop 11.

The above operation is repeatedly performed, and as a result,
The coincidence counter 8 changes the synchronous coincidence pulse a to N1 (=
8) If it is detected twice, it is determined that frame synchronization has been established. If the digital data signal received after the frame synchronization is established is interrupted or a bit slip or the like occurs in the digital data signal and the frame pulse cannot be detected, EX is output.
The OR element 6 outputs a mismatch pulse j to count up the mismatch counter 10. When the count value of the non-coincidence counter 10 reaches the set value N2 (= 4), a pulse is output from the Q2 terminal to be in an asynchronous state. Thereafter, hunting is repeated to establish synchronization again.

Now, as apparent from the above, the set value N2
Is reduced, the count value decreases, and the asynchronous detection time can be shortened. However, when the set value N2 is small, B
When the bit error occurs in the frame bit when the ER (bit error rate) increases, the mismatch counter 10
The hunting is started even if the frame synchronization is normal, and the number of unnecessary transitions to the resynchronization establishment process increases. Further, if the set value N2 is increased, unnecessary hunting can be reduced, but the asynchronous detection time becomes longer.

[0014]

As described above, the time required to detect an asynchronous state and the number of transitions to an unnecessary resynchronization establishment process are in a trade-off relationship with each other. At the same time, there is a problem in that it is difficult to enhance frame synchronization maintenance at the time of BER deterioration. SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to provide a frame synchronization circuit capable of shortening an asynchronous detection time, and at the same time, enhancing frame synchronization maintenance when BER is deteriorated.

[0015]

In order to achieve the above object, a frame synchronization circuit according to the present invention comprises a reference pulse generation circuit for outputting a reference pulse generated by dividing a supplied clock signal by N. A shift register to which a digital data signal and a clock signal are supplied to shift the digital data signal by N bits in synchronization with the clock signal, and that the 0th output and the Nth output of the shift register adopt different logics. A coincidence counter that outputs a pulse when the counted value reaches a predetermined first set value, and the number of times that the 0th output and the Nth output of the shift register have the same logic. Is counted, and the counted value is equal to a predetermined second set value or a third set value.
A switch that outputs a pulse when the set value is reached, a switch that selects and outputs one of the second set value and the output based on the third set value in the mismatch counter, A flip-flop that outputs a signal held in one of the first logic and the second logic in accordance with the output, and a hunting pulse that shifts a reference pulse by one bit in accordance with the output of the flip-flop The circuit includes a hunting pulse generation circuit and a latch element that latches the first to Nth outputs of the shift register and outputs the outputs in parallel. With this configuration, the present invention can select the set value of the mismatch counter according to the BER of the received digital data signal.

[0016]

Next, details of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. 3, the same reference numerals as those in FIG. 3 denote the same parts, and 10a counts the number of times the output of the AND element 9 is supplied to match the logic of the mismatch pulse j and the logic of the reference pulse c. Value N2 (second
, And N3 (third set value), output a pulse from the Q2 terminal and the Q3 terminal, respectively. The relationship between N2 and N3 can be arbitrarily determined as N2 <N3. Here, N2 = 4, N3 =
8 is assumed. Reference numeral 18 denotes a switch for selecting one of the Q2 and Q3 terminals of the mismatch counter 10a in accordance with the supplied BER / ALM signal.

The structure of the digital data signal used in the present invention is the same as that of the conventional example and is shown in FIG. One of the bits D1 to D8 is used as a parity detection bit, and is used for parity check on the receiving side.

The operation of the present invention having the above configuration will be described in detail. The reference pulse generation circuit 1 outputs a reference pulse c by dividing the supplied clock signal by N using a counter 2. Thereafter, the operation up to the operation of the coincidence counter 8 is the same as that of the conventional example. The AND element 9 is supplied with the reference pulse c and the non-coincidence pulse j, and takes a logical product of the two. At this time, the logic of the reference pulse c is “1”,
If the logic of the mismatch pulse j is “1”, the synchronization mismatch pulse b is output and the count value of the mismatch counter 10a is counted up. When the count value reaches a predetermined set value N2 by counting up, a pulse is output from the Q2 terminal. Similarly, when the count value reaches a predetermined set value N3, a pulse is output from the Q3 terminal.

The switch 18 connects either the Q2 terminal or the Q3 terminal of the mismatch counter 10a to the NOT element 14 according to the BER / ALM signal. The BER of the received digital data signal is greater than or equal to a predetermined threshold (BE
When R is degraded), the BER / ALM signal is supplied to connect the Q2 terminal to the NOT element 14. Also, this B
When the ER falls below a predetermined threshold (BER is good), BE
The supply of the R-ALM signal is stopped, and the Q3 terminal and the NOT element 14 are connected.

The pulse output from the Q2 terminal or the Q3 terminal is supplied to the flip-flop 11 via the switch 18 and the NOT element 14, and the flip-flop 1
Set 1 Also, this pulse is simultaneously output to the OR element 1
3, a match counter 8 and a mismatch counter 10a.
And resets the respective count values to "0".

The flip-flop 11 is set to Q
When the output of the terminal changes from logic “0” to “1”, the output of the Q0 terminal and the output of the QN1 terminal of the shift register 15 are shifted in synchronization with the clock signal supplied from the c terminal, and Supplied. AND element 1
6 generates and outputs a hunting pulse h by taking the logical product of the output of the Q0 terminal and the output of the QN1 terminal. The hunting pulse h is supplied to the OR element 3 to shift the reference pulse c by one bit, and at the same time, is supplied to the flip-flop 11 via the NOR element 12 so that the flip-flop 11 is reset.

The above operation is repeatedly performed. As a result,
The coincidence counter 8 changes the synchronous coincidence pulse a to N1 (=
8) If it is detected twice, it is determined that frame synchronization has been established. When the digital data signal received after the frame synchronization is established or the digital data signal is bit-slip or the like and the frame pulse cannot be detected due to a bit slip or the like, the asynchronous state is established. 10a is counted up.

BER is greater than or equal to a predetermined threshold (BER deteriorates)
In the case of, the pulse output from the Q3 terminal is supplied to the flip-flop 11, and hunting is repeated to establish synchronization. That is, by selecting the larger value N3 (= 8) as the set value, the frame synchronization holding is enhanced. BER is less than a predetermined threshold (BER is good)
In the case of, the pulse output from the Q2 terminal is supplied to the flip-flop 11, and hunting is repeated to establish synchronization. That is, by selecting the smaller value N2 (= 4) as the set value, the asynchronous detection time is shortened and resynchronization is quickly established.

More precise control can be performed by using the mismatch counter 10a having three or more types of set values and the switch 18 having the same number of switching stages as the number of output terminals of the mismatch counter 10a. is there.

[0025]

As described above, according to the present invention, two types of setting values of the mismatch counter are prepared, and one of these setting values is selected according to the quality of the BER of the received digital data signal. It has. Therefore, BE
When R is good, by selecting a smaller value as the set value, the asynchronous detection time of the frame can be reduced, and resynchronization can be quickly established. Also, B
When the ER is degraded, frame synchronization can be enhanced by selecting a larger value as the set value.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an example of a configuration of a received digital data signal.

FIG. 3 is an explanatory diagram showing a conventional example.

[Explanation of symbols]

1: Reference pulse generation circuit, 2: Counter, 3, 13: O
R element, 4, 15 ... shift register, 5 ... latch element,
6 ... Exclusive OR element (EX-OR element), 7, 9, 1
6 AND device, 8 match counter, 10a mismatch counter, 11 flip-flop, 12 NOR
Element, 14 NOT element, 17 hunting pulse generation circuit, 18 switch.

Claims (2)

(57) [Claims] In a frame synchronization circuit for transmitting a digital data signal having a frame pulse in which a first logic and a second logic alternately appear every N bits, the supplied clock signal is divided by N. A reference pulse generation circuit that outputs the generated reference pulse; a shift register that is supplied with the digital data signal and the clock signal and shifts the digital data signal by N bits in synchronization with the clock signal; A coincidence counter that counts the number of times that the Nth output has a different logic from each other and outputs a pulse when the counted value reaches a predetermined first set value; a 0th output of the shift register and an Nth output And the number of times the outputs of the counters have the same logic as each other, and the counted value reaches a predetermined second set value or a third set value. And a switch for selecting and outputting either the second set value or the output based on the third set value in the non-match counter, and outputting a pulse according to the output of the match counter and the output of the switch. And a hunting pulse generating a hunting pulse for shifting a reference pulse by one bit in accordance with the output of the flip-flop. A frame synchronization circuit comprising: a circuit; and a latch element that latches first to Nth outputs of a shift register and outputs the latched data in parallel. 2. The switch according to claim 1, wherein the switch selects one of pulses output according to a second set value or a third set value according to a bit error rate of the received digital data signal. A frame synchronization circuit characterized in that a frame is output.