CN117155354A - Continuous pulse synchronization device, continuous pulse synchronization method and chip - Google Patents
Continuous pulse synchronization device, continuous pulse synchronization method and chip Download PDFInfo
- Publication number
- CN117155354A CN117155354A CN202311151105.2A CN202311151105A CN117155354A CN 117155354 A CN117155354 A CN 117155354A CN 202311151105 A CN202311151105 A CN 202311151105A CN 117155354 A CN117155354 A CN 117155354A
- Authority
- CN
- China
- Prior art keywords
- counter
- count value
- converter
- pulse
- synchronization device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 21
- 229910002056 binary alloy Inorganic materials 0.000 abstract description 2
- 230000005540 biological transmission Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
- H03K5/1506—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/08—Output circuits
Abstract
The embodiment of the application discloses a continuous pulse synchronization device, a continuous pulse synchronization method and a chip. The continuous pulse synchronization device in the application counts the source clock pulse signals input into the source clock domain through the first counter working in the source clock domain and outputs the count value, and converts the count value of the input source clock pulse signals into corresponding binary system through the second converter working in the destination clock domain, and counts the pulses output by the pulse generation unit through the second counter working in the destination clock domain, so that the final pulse generation unit can generate and output pulse signals according to the count value output by the second converter working in the destination clock domain and the count value output by the second counter, and the pulse synchronization device does not need to use a low level Clr signal to indicate input pulses as in the current common pulse synchronization device, continuous input of the pulses is realized, and pulse loss can be avoided.
Description
Technical Field
The present application relates to the field of chips, and in particular, to a continuous pulse synchronization device, a continuous pulse synchronization method, and a chip.
Background
The pulse synchronizer commonly used in the current equipment has a certain limit on application, namely, only pulses with certain intervals can be received, for example, a first beat is a pulse, a second beat and a third beat are not pulses, the pulse synchronizer is low-level, then the pulse synchronizer is a pulse until a tenth beat, and otherwise the pulse synchronizer can lose the pulse. This is mainly because, in the case of the present pulse synchronizer (such as the pulse synchronizer shown in fig. 1), if continuous or closely spaced pulses are input, the pulse input method is as follows: the pulse latches the input 1 (i.e. input pulse), at this time, the synchronizer 1 will output a high level, the synchronizer 2 will also output a high level, the Clr signal (pulse clear signal) in the pulse latch will become a high level, and after the Clr signal becomes a high level, the pulse latch will output a low level, the synchronizer 1 outputs a low level, the synchronizer 2 will also output a low level, and then the Clr signal will become a low level, and the pulse latch will be able to input the next pulse. It can be seen that after the pulse in the pulse synchronizer commonly used at present latches the input pulse, the Clr signal returned after the signal rotates 2 turns is low level, and the source input pulse can be input only when the Clr signal is low level, so that the pulse synchronizer commonly used in the present device can only receive pulses with a certain interval.
If each pulse is used to trigger the occurrence of every action of the destination clock domain, for example, each pulse triggers a state machine jump of the destination clock domain, if the pulse is lost, the state machine jump is rarely triggered, resulting in a device function error.
Disclosure of Invention
The application discloses a continuous pulse synchronization device, a continuous pulse synchronization method and a chip, which are used for realizing synchronization by continuously receiving pulses and avoiding pulse loss.
According to a first aspect of an embodiment of the present application, there is provided a continuous pulse synchronization device, the synchronization device including: a first counter, a first converter, a first synchronizer, a second converter, a second counter and a pulse generating unit,
the first counter is used for counting the source clock pulse signals input into the first counter and outputting count values;
the first converter is used for converting the count value of the first counter into a corresponding Gray code;
the first synchronizer is used for converting the Gray code from a source clock domain to a destination clock domain;
the second converter is used for converting the Gray code of the destination clock domain into a corresponding binary value;
the second counter is used for counting the pulses output by the pulse generating unit;
the pulse generating unit is used for generating and outputting a pulse signal according to the count value output by the second converter and the count value output by the second counter.
Optionally, the synchronization device further includes: a third converter, a second synchronizer, a fourth converter and an input pulse back pressure control unit,
the third converter is used for converting the count value of the second counter into Gray codes;
the second synchronizer is used for synchronizing the Gray code output by the third converter into the Gray code count value of the source clock domain;
the fourth converter is used for converting the Gray code count value output by the second synchronizer into a binary count value;
the input pulse back pressure control unit is used for generating a back pressure signal according to the binary count value output by the fourth converter and the count value output by the first counter, and back pressure the source clock pulse signal input source.
Optionally, the counting bit width of the first counter and the second counter is n; the input pulse back pressure control unit is specifically used for:
and outputting a back-pressure signal to back-pressure the source clock pulse signal input source when the count value of the first counter is the same as the low (n-1) bit of the binary count value output by the fourth converter and the highest bit is different.
Optionally, the number of pulses generated by the pulse generating unit is equal to a difference between the count value output by the second converter and the count value output by the second counter.
Optionally, the maximum value of the number of source clock pulse signals continuously received by the synchronization device is 2 n-1 Wherein n is the count bit width of the first counter.
According to a second aspect of embodiments of the present application, there is provided a continuous pulse synchronization method, the method being applied to a continuous pulse synchronization apparatus, the synchronization apparatus comprising: a first counter, a first converter, a first synchronizer, a second converter, a second counter and a pulse generating unit,
the first counter is used for counting the source clock pulse signals input into the first counter and outputting count values;
the first converter is used for converting the count value of the first counter into a corresponding Gray code;
the first synchronizer is used for converting the Gray code from a source clock domain to a destination clock domain;
the second converter is used for converting the Gray code of the destination clock domain into a corresponding binary value;
the second counter is used for counting the pulses output by the pulse generating unit;
the pulse generating unit is used for generating and outputting a pulse signal according to the count value output by the second converter and the count value output by the second counter.
Optionally, the synchronization device further includes: a third converter, a second synchronizer, a fourth converter and an input pulse back pressure control unit,
the third converter is used for converting the count value of the second counter into Gray codes;
the second synchronizer is used for synchronizing the Gray code output by the third converter into the Gray code count value of the source clock domain;
the fourth converter is used for converting the Gray code count value output by the second synchronizer into a binary count value;
the input pulse back pressure control unit is used for generating a back pressure signal according to the binary count value output by the fourth converter and the count value output by the first counter, and back pressure the source clock pulse signal input source.
Optionally, the counting bit width of the first counter and the second counter is n; the input pulse back pressure control unit is specifically used for:
and outputting a back-pressure signal to back-pressure the source clock pulse signal input source when the count value of the first counter is the same as the low (n-1) bit of the binary count value output by the fourth converter and the highest bit is different.
Optionally, the maximum value of the number of source clock pulse signals continuously received by the synchronization device is 2 n-1 Wherein n is the count bit width of the first counter.
According to a third aspect of embodiments of the present application, there is provided a chip comprising a continuous pulse synchronization device according to any of the embodiments above.
The technical scheme provided by the embodiment of the application can comprise the following beneficial effects:
as can be seen from the above technical solution, the continuous pulse synchronization device in the solution provided by the present application counts the source clock pulse signals input therein by the first counter operating in the source clock domain and outputs the count value, and converts the count value of the input source clock pulse signals into the corresponding binary system by the second converter operating in the destination clock domain, and counts the pulses output by the pulse generating unit by the second counter operating in the destination clock domain, so that the final pulse generating unit can generate and output the pulse signals according to the count value output by the second converter operating in the destination clock domain and the count value output by the second counter, without indicating the input pulses by using the low-level Clr signal as in the current common pulse synchronizer, thereby realizing continuous input of the pulses and avoiding loss of the pulses.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the specification and together with the description, serve to explain the principles of the specification.
Fig. 1 is a block diagram of a continuous pulse synchronizer in the related art;
fig. 2 is a schematic structural diagram of a continuous pulse synchronization device according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of another continuous pulse synchronization device according to an embodiment of the present application.
Description of the embodiments
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the application. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "responsive to a determination", depending on the context.
In order to better understand the technical solutions provided by the embodiments of the present application and make the above objects, features and advantages of the embodiments of the present application more comprehensible, the following description of the method embodiments provided by the embodiments of the present application is given with reference to the accompanying drawings.
In circuit design, since a sequential circuit is often composed of various logic gates, and when the logic gates transfer signals, some time is needed to react to input changes, in order to eliminate propagation delay caused by time spent by transferring signals through the logic gates, a synchronizer (such as a pulse synchronizer) is arranged, and the propagation delay is accommodated through clock cycles. But this also results in the usual pulse synchronizer being able to receive only pulses at intervals, which would otherwise be lost. Therefore, in order to eliminate the application limitation of the pulse synchronizer commonly used at present and further improve the synchronization efficiency, the application provides a continuous pulse synchronization device, a continuous pulse synchronization method and a chip, so as to realize synchronization by continuously receiving pulses and avoid pulse loss.
Referring to fig. 2, fig. 2 provides a schematic structural diagram of a continuous pulse synchronization device. As an embodiment, as shown in fig. 2, the synchronization device includes: a first counter 2001, a first converter 2002 operating in a source clock domain, a first synchronizer 2003, a second converter 2004, a second counter 2005 and a pulse generating unit 2006 operating in a destination clock domain,
the first counter 2001 is configured to count a source clock signal input thereto and output a count value;
the first converter 2002 is configured to convert a count value of the first counter 2001 into a corresponding gray code;
the first synchronizer 2003 is configured to convert the gray code from a source clock domain to a destination clock domain;
the second converter 2004 is configured to convert the gray code of the destination clock domain into a corresponding binary value;
the second counter 2005 is used for counting the pulses output by the pulse generating unit;
the pulse generating unit 2006 is configured to generate and output a pulse signal according to the count value output by the second converter 2004 and the count value output by the second counter 2005.
As an embodiment, the source clock domain and the destination clock domain respectively belong to two different clock domains, and there may be a slight difference between corresponding current time, and the purpose of the continuous pulse synchronization method in this embodiment is to synchronize a pulse signal input from the source clock domain to the destination clock domain to trigger a function in the destination clock domain to execute.
In the above embodiment, in a specific implementation, the first counter 2001 may set a counter with a bit width of n bits (the initial value may be set to 0), and the count value output by the first counter 2001 is incremented by 1 each time a new pulse is input in the source clock domain.
In the embodiment of the application, because multiple bits of change can be generated between adjacent binary data, when the binary data is transmitted across clock domains, multiple bits of data errors can occur after the binary data is transmitted from a source clock domain to a destination clock domain. Therefore, in order to avoid this, the present embodiment implements the cross-clock domain transmission of the count value output by the first counter 2001, and converts the cross-clock domain transmission of multi-bit data into the cross-clock domain transmission of single-bit data by utilizing the characteristic that only 1bit is different between two adjacent codes of gray codes.
Based on the gray code, the process of implementing the transmission of the count value output by the first counter 2001 across clock domains by using the gray code in the above embodiment is specifically as follows: the count value output by the first counter 2001 is converted from binary to a corresponding gray code by the first converter 2002, then the gray code output by the first converter 2002 is converted from the source clock domain to the destination clock domain by the first synchronizer 2003, and then the gray code of the current destination clock domain (i.e., the gray code output by the first synchronizer 2003) is converted to a corresponding binary value by the second converter 2004, and finally the binary value output by the second converter 2004 is the count value output by the first counter 2001.
The first synchronizer 2003 converts the gray code output by the first converter 2002 from the source clock domain to the destination clock domain, and can play 2 beats or 3 beats through a multi-bit synchronizer (refer to the existing DFF flip-flop), so as to eliminate the metastable state of the gray code of the source clock domain and the gray code of the destination clock domain, and avoid data transmission errors.
In the above embodiment, the second counter 2005 may be a counter with a bit width of n bits (the initial value may be set to 0), and each time the pulse generating unit 2006 in the destination clock domain outputs a new pulse, the count value output by the second counter 2005 is incremented by 1.
In the embodiment of the present application, if the number of received input pulses is not equal to the number of output pulses (i.e., the count values output by the first counter 2001 and the second counter 2005 are not equal), it is indicated that the currently received input pulses are not all output yet, and thus, the output pulses can be continued. However, if the number of received input pulses is equal to the number of output pulses, it means that the current received input pulses have been all output, and no pulse that can be continuously output is required to wait for a new pulse to be input. Therefore, the pulse generating unit 2006 in this embodiment may generate and output a pulse signal based on the count value output by the second converter and the count value output by the second counter.
The description of the apparatus shown in fig. 2 is completed above.
As can be seen from the embodiment shown in fig. 2, the continuous pulse synchronizing apparatus of the present application counts the source clock pulse signals inputted thereto by the first counter operating in the source clock domain and outputs the count value, and converts the count value of the inputted source clock pulse signals into the corresponding binary by the second converter operating in the destination clock domain and counts the pulses outputted from the pulse generating unit by the second counter operating in the destination clock domain, so that the final pulse generating unit can generate and output the pulse signals according to the count value outputted from the second converter operating in the destination clock domain and the count value outputted from the second counter without indicating the inputted pulses using the low-level Clr signal as in the current common pulse synchronizer, continuous input of the pulses is achieved, and loss of the pulses can be avoided.
Referring to fig. 3, as shown in fig. 3, another structure diagram of the continuous pulse synchronization apparatus is provided in this embodiment. As an embodiment, the continuous pulse synchronization device shown in fig. 3 further includes, compared to the embodiment shown in fig. 2: a third converter 2007, a second synchronizer 2008, a fourth converter 2009 and an input pulse back pressure control unit 2010,
the third converter 2007 is configured to convert the count value of the second counter 2005 into gray code;
the second synchronizer 2008 is configured to synchronize the gray code output by the third converter 2007 to a gray code count value of a source clock domain;
the fourth converter 2009 is configured to convert the gray code count value output by the second synchronizer 2008 into a binary count value;
the input pulse back pressure control unit 2010 is configured to generate a back pressure signal according to the binary count value output by the fourth converter 2009 and the count value output by the first counter 2001, and back pressure the source clock pulse signal input source.
Alternatively, if the bit widths of the first counter 2001 and the second counter 2005 are n bits in the present embodiment, the input pulse back pressure control unit 2010 is specifically configured to: when the count value of the first counter 2001 is the same as the low (n-1) bit of the binary count value output by the fourth converter 2009 and the highest bit is different, a back-pressure signal is output to back-pressure the source clock signal input source. Wherein the backpressure signal is used to indicate that no new pulses are received. Alternatively, the backpressure signal may be implemented by a rdy signal in the circuit.
Alternatively, in some embodiments, the number of pulses generated by the pulse generating unit 2006 is equal to the difference between the count value output by the second converter 2004 and the count value output by the second counter 2005. The count value output by the second converter 2004 represents the source clock pulse signal input by the current synchronizer, and the count value output by the second counter 2005 represents the pulse output by the current pulse generating unit, so the number of pulses that the pulse generating unit 2006 can also generate in this embodiment is equal to the difference between the count value output by the second converter 2004 and the count value output by the second counter 2005.
Optionally, in this embodiment, the maximum value of the number of source clock pulse signals continuously received by the synchronization device is 2 n-1 Wherein n is the count bit width of the first counter. 2 herein n-1 The method is to set according to the maximum bearing capacity of the first synchronizer and the second synchronizer so as to avoid data errors caused by that the input and non-output pulse signals exceed the maximum bearing capacity of the first synchronizer and the second synchronizer.
The description of the apparatus shown in fig. 3 is completed above.
With the embodiment shown in fig. 3, the input pulse back pressure control unit 2010 may be further configured to generate a back pressure signal according to the binary count value output by the fourth converter 2009 and the count value output by the first counter 2001, and back pressure the source clock pulse signal input source, so as to avoid an error of the continuous pulse synchronizer.
The continuous pulse synchronization device provided by the embodiment of the application is described above. The following describes a continuous pulse synchronization method provided by an embodiment of the present application:
the continuous pulse synchronization method is applied to a continuous pulse synchronization device, and the synchronization device comprises: a first counter, a first converter, a first synchronizer, a second converter, a second counter and a pulse generating unit,
the first counter is used for counting the source clock pulse signals input into the first counter and outputting count values;
the first converter is used for converting the count value of the first counter into a corresponding Gray code;
the first synchronizer is used for converting the Gray code from a source clock domain to a destination clock domain;
the second converter is used for converting the Gray code of the destination clock domain into a corresponding binary value;
the second counter is used for counting the pulses output by the pulse generating unit;
the pulse generating unit is used for generating and outputting a pulse signal according to the count value output by the second converter and the count value output by the second counter.
Optionally, the synchronization device further includes: a third converter, a second synchronizer, a fourth converter and an input pulse back pressure control unit,
the third converter is used for converting the count value of the second counter into Gray codes;
the second synchronizer is used for synchronizing the Gray code output by the third converter into the Gray code count value of the source clock domain;
the fourth converter is used for converting the Gray code count value output by the second synchronizer into a binary count value;
the input pulse back pressure control unit is used for generating a back pressure signal according to the binary count value output by the fourth converter and the count value output by the first counter, and back pressure the source clock pulse signal input source.
Optionally, the counting bit width of the first counter and the second counter is n; the input pulse back pressure control unit is specifically used for:
and outputting a back-pressure signal to back-pressure the source clock pulse signal input source when the count value of the first counter is the same as the low (n-1) bit of the binary count value output by the fourth converter and the highest bit is different.
Optionally, the maximum value of the number of source clock pulse signals continuously received by the synchronization device is 2n-1, where n is the count bit width of the first counter.
It should be noted that, for details related to the above embodiments of the continuous pulse synchronization method, reference may be made to descriptions of the embodiments of the apparatus shown in fig. 2 and 3, which are not repeated herein.
Correspondingly, the embodiment of the application also provides a chip, which comprises the continuous pulse synchronization device.
The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather to enable any modification, equivalent replacement, improvement or the like to be made within the spirit and principles of the application.
Claims (10)
1. A continuous pulse synchronization device, the synchronization device comprising: operating at the source
A first counter, a first converter, a first synchronizer, a second converter, a second counter and a pulse generating unit in the destination clock domain,
the first counter is used for counting the source clock pulse signals input into the first counter and outputting count values;
the first converter is used for converting the count value of the first counter into a corresponding Gray code;
the first synchronizer is used for converting the Gray code from a source clock domain to a destination clock domain;
the second converter is used for converting the Gray code of the destination clock domain into a corresponding binary count value;
the second counter is used for counting the pulses output by the pulse generating unit;
the pulse generating unit is used for generating and outputting a pulse signal according to the count value output by the second converter and the count value output by the second counter.
2. The synchronization device of claim 1, further comprising: a third converter, a second synchronizer, a fourth converter and an input pulse back pressure control unit,
the third converter is used for converting the count value of the second counter into Gray codes;
the second synchronizer is used for synchronizing the Gray code output by the third converter into the Gray code count value of the source clock domain;
the fourth converter is used for converting the Gray code count value output by the second synchronizer into a binary count value;
the input pulse back pressure control unit is used for generating a back pressure signal according to the binary count value output by the fourth converter and the count value output by the first counter, and back pressure the source clock pulse signal input source.
3. The synchronization device of claim 2, wherein the first counter and the second counter have a count bit width of n; the input pulse back pressure control unit is specifically used for:
and outputting a back-pressure signal to back-pressure the source clock pulse signal input source when the count value of the first counter is the same as the low (n-1) bit of the binary count value output by the fourth converter and the highest bit is different.
4. The synchronization device according to claim 1, wherein the number of pulses generated by the pulse generating unit is equal to a difference between a count value output by the second converter and a count value output by the second counter.
5. The synchronization device according to claim 1, wherein a maximum value of the number of source clock pulse signals continuously received by the synchronization device is 2 n-1 Wherein n is the count bit width of the first counter.
6. A continuous pulse synchronization method, characterized in that the method is applied to a continuous pulse synchronization device, the synchronization device comprising: a first counter, a first converter, a first synchronizer, a second converter, a second counter and a pulse generating unit,
the first counter is used for counting the source clock pulse signals input into the first counter and outputting count values;
the first converter is used for converting the count value of the first counter into a corresponding Gray code;
the first synchronizer is used for converting the Gray code from a source clock domain to a destination clock domain;
the second converter is used for converting the Gray code of the destination clock domain into a corresponding binary value count value;
the second counter is used for counting the pulses output by the pulse generating unit;
the pulse generating unit is used for generating and outputting a pulse signal according to the count value output by the second converter and the count value output by the second counter.
7. The synchronization method according to claim 6, wherein the synchronization device further comprises: a third converter, a second synchronizer, a fourth converter and an input pulse back pressure control unit,
the third converter is used for converting the count value of the second counter into Gray codes;
the second synchronizer is used for synchronizing the Gray code output by the third converter into the Gray code count value of the source clock domain;
the fourth converter is used for converting the Gray code count value output by the second synchronizer into a binary count value;
the input pulse back pressure control unit is used for generating a back pressure signal according to the binary count value output by the fourth converter and the count value output by the first counter, and back pressure the source clock pulse signal input source.
8. The synchronization method of claim 7, wherein the first counter and the second counter have a count bit width of n; the input pulse back pressure control unit is specifically used for:
and outputting a back-pressure signal to back-pressure the source clock pulse signal input source when the count value of the first counter is the same as the low (n-1) bit of the binary count value output by the fourth converter and the highest bit is different.
9. The synchronization device according to claim 6, wherein the synchronization device continuously receives the maximum number of source clock signalsA value of 2 n-1 Wherein n is the count bit width of the first counter.
10. A chip comprising a continuous pulse synchronization device according to any one of claims 1-5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311151105.2A CN117155354A (en) | 2023-09-06 | 2023-09-06 | Continuous pulse synchronization device, continuous pulse synchronization method and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311151105.2A CN117155354A (en) | 2023-09-06 | 2023-09-06 | Continuous pulse synchronization device, continuous pulse synchronization method and chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117155354A true CN117155354A (en) | 2023-12-01 |
Family
ID=88898555
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311151105.2A Pending CN117155354A (en) | 2023-09-06 | 2023-09-06 | Continuous pulse synchronization device, continuous pulse synchronization method and chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117155354A (en) |
-
2023
- 2023-09-06 CN CN202311151105.2A patent/CN117155354A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4691319A (en) | Method and system for detecting a predetermined number of unidirectional errors | |
| FI78802B (en) | KOPPLINGSARRANGEMANG FOER KODNING OCH AVKODNING AV INFORMATIONSSIGNALER. | |
| EP0059224B1 (en) | System for coding and decoding binary data | |
| US7102553B2 (en) | Signal transmission method and signal transmission device | |
| US4740998A (en) | Clock recovery circuit and method | |
| CN114242138A (en) | Time delay controller, memory controller and time sequence control method | |
| JPH0654475B2 (en) | Device for detecting transition error | |
| CN101228698B (en) | 4-level logic decoder and method for decoding 4-level input data signal | |
| CN117155354A (en) | Continuous pulse synchronization device, continuous pulse synchronization method and chip | |
| EP0064590B1 (en) | High speed binary counter | |
| US4425562A (en) | Device for coding signals which are distributed between a number of channels | |
| US5901189A (en) | Symmetrical correlator | |
| JPH0462503B2 (en) | ||
| KR100272945B1 (en) | High speed asynchronous serial to parallel data converter | |
| CN100426679C (en) | Oversampling technique to reduce jitter | |
| US6633966B1 (en) | FIFO memory having reduced scale | |
| CN101373974B (en) | Coding method and apparatus | |
| EP0282924A2 (en) | Bipolar with eight-zeros substitution and bipolar with six-zeros substitution coding circuit | |
| CN109525241B (en) | Gray code counter | |
| JP2814978B2 (en) | Frame synchronization circuit | |
| KR100434364B1 (en) | Serial adder | |
| RU2207614C1 (en) | Data input device | |
| RU2025049C1 (en) | Device for decoding of group codes | |
| SU1101804A1 (en) | Stochastic walsh function generator | |
| SU1363224A1 (en) | Device for interphasing computing with communication channels |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |