JP2752654B2 - Data transmission method of scrambled code - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital data transmission system of a self-timing system, and more particularly to a data transmission system of performing continuous homo-code suppression using a scrambler.

[Conventional technology]

Conventionally, in data transmission in which transmission data is scrambled to thereby suppress the same code continuation of data on the transmission path, the suppression of the same code continuation is completely performed by the statistical pattern of the data itself input to the scrambler. Depends on.

[Problems to be solved by the invention]

As described above, in the data transmission method in which the same code is continuously suppressed by self-synchronous scrambling, the data in the register in the scrambler and the transmission data input to the scrambler at the start of transmission or during transmission. If all are the same code, the same code continuation occurs after the scramble operation. Therefore, despite the use of the scrambler, in the transmission code string output on the transmission path, There is a problem that the same code continuation cannot be suppressed, and as a result, the transmission code string is not randomized by the scrambler.

An object of the present invention is to provide a data transmission system capable of always performing the same code continuous suppression.

[Means for solving the problem]

In the data transmission method using the self-synchronous scrambler according to the present invention, the data transmitting side monitors a data scrambler, a monitoring unit for monitoring a continuous two-bit code of the scrambled transmission code, and the monitoring unit monitors the same code. When the continuous detection continues n (n is an integer of 2 or more), the transmission clock
An n counter that counts 1/2 shift clocks up to n and outputs a count, and a data inverting unit that forcibly converts the code after scrambling by a data inversion control signal output in response to the count output. And characterized in that:

〔Example〕

 Next, the present invention will be described with reference to the drawings.

Referring to FIG. 1, a data transmission unit 1 includes a scrambler 2 for scrambling transmission data input, and a continuous 2-bit data code monitoring unit for inputting a scrambled code and detecting a continuous 2-bit code sequence. 3 and inverter 10
The shift clock 1/2 of the transmission clock 8 by n
An n counter 4 for counting up to (an integer of 2 or more) and a data inverting unit 5 for forcibly inverting the transmission data output by the output of the n counter 4 to a continuous same sign and opposite sign.

Upon the start of data transmission, the transmission data input 7 is input to the scrambler 2 and converted into scrambled data. This scrambled data is input to a continuous 2-bit data code monitoring unit 3, which resets the n-counter 4 when the continuous 2-bit data shifted by one bit from the original data has a different code, and resets the counting operation. Stop.

The n counter 4 outputs the n count map when the n-th bit and the (n + 1) -th bit are the same. Second
The figure shows transmission data and counter operation codes in each unit to supplement the explanation of the operation of this example. The signal (a) in FIG. 2 is the original data to be transmitted,
Are input to the shift register 23. The signal (b) in FIG. 2 is a signal obtained by shifting the signal (a) by 1 bit, and corresponds to the signal 13 in FIG. Homogeneous code continuous monitoring unit 3
Generates the counter reset signal for the counter 4 by the EX-OR of the signal (a) and the signal (b). That is, when two adjacent bits have different codes, the counter 4
Are generated, and if they have the same sign,
A non-reset signal is generated. In order to realize the reset signal, a method using EX-OR or the like can be considered. FIG. 3 shows a simple example of the same-code continuation monitoring unit corresponding to 3 in FIG. The signal (d) in FIG. 2 shows the state of the reset signal 12. The signal (c) in FIG. 2 is a clock used for counting the same code continuation number, and has a half phase different from a clock for driving scramble. Here, the phase difference is assumed for counting the number of data. If the configuration is such that data counting can be performed reliably without setting the phase, a configuration in which the inverter 10 is unnecessary may be considered. In this example, the output of the inverter 10 corresponds to the clock signal (c).

The counter 4 performs a count operation using the clock signal (c) when the reset signal output from the homo-code continuity monitoring unit 3 is in a non-reset state. This is shown by signal (e). In the present embodiment, the counter 4 sets n-1 = 4 as a count-up value for the purpose of inverting the n + 1 = 6th bit when the same sign of n = 5 occurs consecutively. In other words, the same-code continuation is recognized by the appearance of the second consecutive bit that one block having the same code has two consecutive occurrences, and consequently, four consecutive blocks of the same code have occurred when five consecutive bits have occurred. It is the same value as having done. Therefore, the counter 4 of this example counts the number n-1 of consecutive blocks of the same code as the number n of the same code continuations. This is apparent from the fact that, in the same time slot of the signals (a) and (b) in FIG. 2, the number of time slots in which data has the same sign coincides with the count (e). The configuration of the counter 4 can be realized by either configuration, whether counting is continued after counting up or counting is stopped while holding the count up value.

When the next clock (c) is input to the counter 4 in the state of the count value 4, the counter 4 immediately outputs the inverted control signal.
Outputs 11. The signal (f) indicates the data inversion control signal 11. Since the data signal (a) is inverted from 0 to 1, the same-code continuation monitoring unit 3 outputs a reset signal (d) to the counter 4. In the signal (e), the count value 4
And the blank portion shown between the count value 0 and the count value 0, the generation of the reset signal (d) is also delayed due to the delay from the generation of the inversion control signal (f) to the change of the data signal (a).
As a result, a delay that occurs until the counter value returns to 0 is shown. The counter 4 immediately resets the count value to zero by the reset input. However, after the data inversion control signal (f) rises, it is necessary to hold the data inversion control signal after the next fall of the clock signal (c). In this embodiment, the holding of the signal (f) is started immediately at the rising of the signal (f), and the rear end of the held signal (f) is retimed at the rising of the next clock signal (c). Thus, a configuration for maintaining the required control time is assumed. By using the clock signal (c) and retiming the signal (a) whose data value is inverted from 0 to 1 by the flip-flop 6, an output indicating the signal (g) is finally obtained.

An operation example according to FIG. 1 is shown with a control value n = 5 of the same code continuation. In this embodiment, the signal (a) is denoted by the symbol “1”.
It is assumed that a transmission data string in which at least 6-bit code “0” continues after the transmission data string. The allowable number of consecutive same codes is 5, and in the signal (a) corresponding to the output of the scrambler, 5 consecutive codes of "0" are counted by the counter 4, and the counter 4 counts up. By the retiming of the count-up, the data inversion control signal 11
Sent to. Further, the input signal to the shift register 23 is immediately inverted in the data inversion section 5 by the data inversion control signal 11 (signal (f)). Therefore, in this example, it is converted to the code “1”. Since the same code continuous monitoring unit 3 performs code monitoring using the output of the direct data inversion unit,
With this inversion control, a reset signal is immediately generated, and the counter 4 is reset via the reset signal line 12. Therefore, the count value of the counter 4 returns to 0,
Since the data inversion control signal is retimed, the data inversion control signal is held 1 bit long without being inverted. The flip-flop 6 performs retiming on the inverted signal (a) by using a positive-phase clock to obtain an output indicated by the signal (g).

When the sixth bit is 1, the counter 4 counts up once, but the same-code monitoring unit 3 transmits a reset signal to the counter 4 based on the data of the sixth-bit sixth code “1”. Because the reset signal resets the count value before retiming the count-up state, the data inversion control signal is not transmitted to the data inversion unit, and data inversion does not occur. Therefore,
The sixth bit always has an inverse value for five consecutive transmission data.

〔The invention's effect〕

As described above, in the present invention, the continuous 2-bit code monitoring unit counts up to a 1 / 2-bit shift clock of the transmission clock when n consecutive detections of the same code continue for n times,
When the count is increased, the scrambled code is forcibly converted, so that the continuation of the same code can be suppressed. As a result, the transmission code string can be always randomized by the scrambler.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention, and FIG. 2 is a signal diagram for explaining the operation of the present invention. FIG. 3 is a diagram showing a configuration example of the code monitoring unit. 1 ... data transmission unit, 2 ... scrambler, 3 ... continuous 2-bit data code monitoring, 4 ... counter, 5 ... data inversion unit, 6 ... flip-flop, 7 ... transmission data input, 8 ... …
Transmission clock, 9 ... Transmission data output, 10 ... Inverter. 13 ... Scrambler input data shifted by 1 bit. 11: Data inversion control signal, 12: Reset signal,
21, 22, ... exclusive-OR circuit (EX-OR), 23 ... m-stage shift register.

Claims (1)

(57) [Claims] 1. A self-timing type data transmission system comprising a scrambler and using the scrambler to suppress homo-code continuity, wherein a continuous 2-bit homo-code continuation of scrambled transmission data is monitored. A continuous 2-bit code monitoring unit that outputs a non-reset signal when the same code continues and a reset signal when a different code continues, counts while the continuous 2-bit code monitoring unit sends a non-reset signal, An inversion control signal that counts up to 1 (n is an integer of 2 or more), can hold a count-up value n-1 or can continue counting, and inverts a continuous code to an inverse value by detecting the n + 1th bit of the same code. And a data inverting unit that receives the inversion control signal and forcibly inverts the data of the (n + 1) th bit to the opposite sign. Scrambled data transmission method of a code characterized by.