JPH07245630A - High speed data transmission system - Google Patents

Abstract

PURPOSE:To attain high speed data transmission employing an NR waveform while warranting a minimum transition by preventing production of consecutive same codes in n-bits or over with a scrambler at a sender side and providing a decoder not using a descrambler but having an error correction function to a receiver side. CONSTITUTION:An output of transmission data 20 is coded into a code such as a convolution code whose error is detected and corrected by a coder 21. The coded output is set to (n-1) stages of shift registers 23 via an OR circuit 26 synchronously with a transmission clock signal. When AND circuits 24, 25 detect n-sets of consecutive same codes, an OR circuit 26 generates a signal of level '1' and gives the signal to an XOR circuit 22 and the signal is given from the coder 21 to the XOR circuit 22, and its inverted output is set to a 1st stage of the shift register 23, and an output therefrom becomes transmission data. A Viterbi decoder 27 or the like immune to random error correction of the convolution code is used for the receiver side. Thus, high speed data transmission employing an NR waveform is attained while warranting a minimum transition.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high speed data transmission system. When data is transmitted at high speed, the transmission data is encoded and transmitted. However, in the case of an NRZ waveform, if one of the codes is continuous, the DC component increases and it becomes impossible for the receiving side to accurately reproduce the code. . Therefore, although a scrambler is provided on the transmission side to scramble the transmission signal and a descrambler is provided on the reception side to descramble the signal, it is desired to simplify the device configuration on the transmission side and the reception side.

[0002]

2. Description of the Related Art In conventional data communication, a lower limit of the frequency of a transmission data waveform is set in order to prevent the direct current component from increasing and preventing normal reception when the transmission waveform has few AC components. For example, in Ethernet or the like, 1,0 data is Manchester coded and transmitted by using an RZ (return to zero) waveform. However, with this method, the amount of information that can be transmitted is half that of the transmission capacity of the transmission path.

In data communication by radio via satellite, NRZ (non-return to zero) is used to increase the speed. In this case as well, the same code "1" or "0" is continuously transmitted. In order to prevent this, it is necessary to guarantee the minimum transition density so that it does not fall below the lower limit of the transmission frequency. The configuration in this case is shown as an explanatory view of the conventional example in FIG.

FIG. 3 is an explanatory view of a conventional example. A. On the transmitting side, the data to be transmitted is encoded in the encoder 60 for the purpose of error correction in order to improve the quality, and the encoded signal is input to the scrambler 61 to guarantee the minimum transition density as shown in FIG. Scrambled for. The scrambler 61 is the B. It is a circuit that has a configuration as shown as an example in FIG. 3 and that combines a plurality of stages of delay circuits D (flip-flop circuits, etc.) and a plurality of EORs (exclusive OR circuits). When the bits of the input data are continuously the same due to the following logical operation, the sign is forcibly changed and the output is transmitted.

On the receiving side, the A. The signal from the communication path is input to the descrambler 62 and descrambled as shown in FIG. The descrambler 62 is a C.I.
As shown in (1), the configuration corresponding to the scrambler 61 is provided, and the delay circuit D and EOR are provided in a plurality of stages.

The output of the descrambler 62 is the decoder 63.
To be decoded into data before being encoded.

[0007]

According to the conventional row as shown in FIG. 3, a scrambler is provided on the transmitting side to ensure the minimum transition density when high-speed data transmission is desired, and the receiving side is correspondingly provided with the scrambler. There is a problem that it is necessary to provide a descrambler at the same time, the cost of the device increases, and control is required to operate the descrambler on the receiving side in synchronization with the scrambler on the transmitting side.

It is an object of the present invention to provide a high-speed data transmission system capable of ensuring a minimum transition while using the NRZ waveform to speed up the operation and simplifying the structures of both the transmitting and receiving devices.

[0009]

FIG. 1 is a block diagram showing the principle of the present invention. In FIG. 1, 1 is an error correction function (a function to detect and correct an error when the error is less than a certain number of bits)
Is a scrambler that detects and inverts n consecutive codes, 3 is a transmission line, and 4 is a decoder that performs error correction. The encoder 1 can be provided with functions such as array conversion by interleaving,
Correspondingly, the decoder can be provided with functions such as deinterleaving. The transmission path 3 may be wired or wireless.

According to the present invention, the transmission side encodes the transmission data into a code having an error correction function, further scrambles by a scrambler so as to guarantee a minimum transition, and transmits the data. The reception side applies this signal to a decoder for error detection / Data is obtained at the time of transmission by making a correction.

[0011]

The transmission data is encoded in the encoder 1 into a code having an error correction function (one of various known codes is used). The encoded data is scrambled by the scrambler 2. However, the scrambler 2 is provided with n consecutive code detection and inversion means 2a which inverts and outputs the last n-th code when n identical codes ("1" or "0") occur consecutively. . The number n in this case is determined by the minimum transition required corresponding to the speed of this data transmission.

The output generated from the scrambler 2 is sent to the transmission line 3 by the signal of the NRZ waveform. When the receiving side receives the signal from the transmission path 3, the decoder 4 decodes the signal. This decoding has an error detection / correction function corresponding to the encoder 1 on the transmission side, and in the scrambler 2 on the transmission side, the original code is applied to the encoded data by the n continuous code detection / inversion means 2a. If the inverted bit is included, it is detected as an error, corrected, and returned to the original code. Therefore, it is not necessary to provide a descrambler on the receiving side.

[0013]

FIG. 2 is a block diagram of an embodiment. 2A. Is the configuration of the transmitting side, B. Indicates the configuration of the receiving side.

Referring to FIG. In FIG. 1, 20 is a data device on the transmission side, 21 is an encoder, 22 to 26 are n continuous code detection and inversion means 2a of FIG. 1, 22 is an XOR (exclusive OR) circuit, and 23 is (n-1). ) Stage shift register, 2
4 is an AND circuit to which the output of the (n-1) th stage of the shift register 23 and the output (1 bit) from the encoder 21 are input,
Although 25 inputs the same n outputs as the AND circuit 24, it is an AND circuit for inverting and inputting all the signals, and 26 is an OR circuit.

Referring to FIG. The data generated from the transmission side data device 20 is encoded by a code that can be error-detected and corrected by the encoder 21, for example, a convolutional code (a code associated with a plurality of bits generated before the current bit). To do. One of the code outputs is supplied to the AND circuits 24 and 25, and the other is output to the XOR circuit 22.
To the output of the OR circuit 26 and the exclusive OR is taken. In this case, when the output from the OR circuit 26 is "1", the output is "1" if the output of the encoder 21 is "0", and the output is "0" if the output of the encoder 21 is "1". Then, the input signal is inverted and output.

The output of the XOR 22 is set in the first stage (input stage) of the shift register 23 in synchronization with the transmission clock,
This first-stage bit output is output for transmission. When the signal from the XOR 22 is input to the first stage, each bit set in each stage of the n-stage shift register 23 before that is shifted to the next stage, and the last-stage bit is lost.

The bit signal output from the encoder 21 and each output signal of the (n-1) th stage of the shift register 23 are supplied to AND circuits 24 and 25, and the AND circuit 24 inputs all n inputs to "1". (N pieces of "1" codes are continuous) is detected, and the AND circuit 25 outputs all "0".
(N consecutive "0" codes) are detected.

In the AND circuit 24 or 25, the same reference numeral is n
When it is detected that the number of lines is continuous, the OR circuit 26 outputs "1".
Occurs, the signal input from the encoder 21 at this time is XOR
It is inverted by the circuit 22 and set in the first stage of the shift register 23, and the output of the first stage becomes transmission data, which is frequency-converted and transmitted in the NRZ waveform.

Next, referring to FIG. Decoder 2 on the receiving side shown in
7 and the data device 28 on the receiving side are shown, but the internal structure thereof is omitted because it uses a conventional decoder having an error correction function. Specifically, it is possible to use a known Viterbi decoder capable of receiving data encoded by the convolutional code and performing strong random error correction in decoding. The Viterbi decoder has been used conventionally because of its excellent error correction function, especially in wireless communication.

With this decoder, even if the signal of the nth bit is inverted when the same code of n bits continues in the transmitting side, this can be detected as an error and corrected to a correct code.

[0021]

According to the present invention, it is possible to prevent the same code from being continuously generated by n bits or more by the scrambler on the transmitting side, and to provide a decoder having an error correcting function without using the descrambler on the receiving side. With the simple structure of providing, a high-speed data transmission is possible by the NRZ waveform while guaranteeing the minimum transition.

As a decoder on the receiving side, a Viterbi decoder having an error correction function has been conventionally used in wireless communication or the like, and the present invention can be realized without increasing the amount of hardware.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment.

FIG. 3 is an explanatory diagram of a conventional example.

[Explanation of symbols]

 1 encoder 2 scrambler 3 transmission line 4 decoder

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H04L 25/08 B 9199-5K

Claims (4)

[Claims] 1. A transmission side comprises an encoder for encoding transmission data into a code capable of error correction, and a scrambler for scrambling output data of the encoder, and the output of the scrambler is transmitted by an NRZ waveform. And the receiving side
A decoder having an error correction function is provided, and when a signal sent from the transmission side is received, decoding including error correction is performed, and a signal changed by the scrambler is detected and corrected as an error. High-speed data transmission method. 2. The scrambler on the transmitting side according to claim 1, wherein the scrambler on the transmission side is composed of n consecutive code detection / inversion means for inverting the data of the predetermined number when the same code continues for a predetermined number of times. Characteristic high-speed data transmission method. 3. The n-successive code detection and inversion means according to claim 2, an exclusive OR circuit, an n-stage shift register to which an output of the exclusive OR circuit is input, and n of the shift register. A logic circuit for detecting that the outputs of the stages have the same sign, the output of the logic circuit is input to the exclusive OR circuit together with the output of the encoder, and the output of the first stage of the shift register is transmitted. A high-speed data transmission method characterized in that 4. The high-speed data transmission system according to claim 1, wherein the transmitting side includes an encoder that performs convolutional encoding, and the receiving side includes a decoder that performs Viterbi decoding.