JPH0644756B2 - Synchronous clock generation circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a synchronous clock for synchronizing a receiving side clock signal with a transmitting side fundamental frequency signal in a communication system in which a transmitting side and a receiving side are asynchronous, such as a data transmission device. It relates to a generation circuit.

[Prior Art] FIG. 1 is a block connection diagram showing an example of a conventional synchronous clock generation circuit. In the figure, (1) is a received data input signal and (2) is a basic frequency of the received data input signal. An oscillator that generates a high-speed clock signal (3) having a frequency several to several tens of times, (4) is a clock signal that counts this high-speed clock signal and has the same cycle as the fundamental frequency of the received data input signal (1). A counter that outputs (5), (6) is a change point detection circuit that detects the rising or falling point of the received data input signal (1), (7) is the output of this change point detection circuit, and the counter (4) Is a reset signal for resetting, and (8) is a discriminator for discriminating the received data input signal (1) by the clock signal (5) and reproducing the received data. FIG. 2 is a block connection diagram showing an example of the change inspection circuit (6).
(3) and (7) indicate the same or corresponding portions as the same reference numerals in FIG. In the figure, (10) is a D-type flip-flop circuit (hereinafter abbreviated as D-FF), and (11) is an exclusive OR circuit.

FIG. 3 is a timing chart showing waveforms of respective parts of the synchronous clock generating circuit shown in FIGS. 1 and 2. FIG. 3 (a) is a waveform of the transmission data signal, and FIG. 3 (b) is a waveform of impulse noise N mixed in the transmission data signal during transmission.
Figure (c) shows the waveform of the received data input signal (1), Figure 3 (d) shows the waveform of the reset signal (7), and Figure 3 (e) shows the high-speed clock signal.
The waveform of (3), and FIG. 3 (f) is the waveform of the clock signal (5).

In the synchronous clock generation circuit configured as described above, the change point detection circuit (6) uses the high-speed clock signal (3) DF
After the F (10) is operated and delayed by one clock, the exclusive OR circuit (11) generates a reset signal (7) of a single pulse, and the reset signal (7) resets the counter (4). Therefore, when impulsive noise N is mixed in the received data input signal (1) as shown in FIG. 3 (c), the reset signal (7) output from the change point detection circuit (6) is changed to that shown in FIG. Therefore, there is a drawback that an erroneous clock signal is generated as shown in FIG.

[Outline of Invention]

The present invention has been made in order to eliminate the drawbacks of the conventional device as described above, and suppresses impulsive noise mixed in during data transmission by simple digital processing, and has excellent noise resistance, and An object of the present invention is to obtain a synchronous clock generation circuit that does not lose the simplicity of the circuit configuration.

Example of Invention

FIG. 4 is a block connection diagram showing an embodiment of the present invention, and (1) to (8) show the same or corresponding portions as the same reference numerals in FIG. Reference numeral (20) is a shift register composed of a plurality of D-FFs for transferring the received data input signal (1) bit by bit.

FIG. 5 is a block connection diagram showing an embodiment of the shift register (20) and the change point detection circuit (6) of the synchronous clock generation circuit of FIG. 4, (1), (3), (6), (7) and (20) indicate the same or corresponding portions as the same reference numerals in FIG. (twenty one)~
(23) is a D-FF each constituting a shift register, (24)-
(26) is an output signal of each D-FF, (27) is an AND gate,
(28) is a NOR gate, (29) is an OR gate, (30) is an OR gate (2
The output signal of 9) and (31) are D-FFs.

Further, FIG. 6 is a timing chart showing waveforms of respective parts of the synchronous clock generating circuit of FIG. 4 and FIG. Figure 6 (a) shows the waveform of the received data input signal (1), and Figure 6 (b) shows the D-FF (21).
Waveform of the output signal (24) of FIG. 6, FIG. 6 (c) is the waveform of the output signal (25) of the D-FF (22), and FIG. 6 (d) is the output signal of the D-FF (23) (26). Waveform, Fig. 6 (e) shows the output signal (3
0) waveform, Figure 6 (f) is the reset signal (7) waveform, Figure 6
(g) shows the waveform of the high-speed clock signal (3), and FIG. 6 (h) shows the waveform of the clock signal (5).

In the example of FIG. 5, a high-speed clock signal that is 8 times the fundamental frequency
An example is shown in which (3) is divided by 8 to generate the clock signal (5) synchronized with the received data input signal (1).
The shift register (20) is composed of three D-FFs (21) to (23), and the normal phase outputs of the two D-FFs (21) and (22) in the preceding stage and the received data input signal (7). ) And the reverse phase output of the D-FF (23) at the 1st subsequent stage, the AND gate (27) detects the change of the rising signal, and the NOR gate (28) detects the change of the falling signal. .

As shown in FIG. 6 (a), even when a positive phase noise pulse N ₁ or a negative phase noise pulse ₁ is mixed in the received data input signal (1), the above-mentioned change point detection circuit (6) Therefore, only the reset signal (7) as shown in FIG. 6 (f) corresponding to the correct change of the received data input signal (1) is generated.

In the example of FIG. 6, the clock signal (5) is generated by dividing by 8 as shown in FIG. 6 (h), so that the reset signal (7) is reset by the D- F
It is delayed by 1 bit by F (31). Therefore, the clock signal (5) is output as an inverted version of the MSB of the counter (4).

Shift register (20) and change point detection circuit having the configuration of FIG.
In (6), the effect can be removed even up to a noise pulse having a width twice the high-speed clock period. This is two D
This is because the delay is given by -FF (21) and (22). If the number of D-FF stages of the positive phase output of the shift register (20) is increased, a wider noise pulse is obtained. Also, it is possible to prevent the generation of an erroneous reset signal.

However, when the anti-phase output D-FF (23) of the shift register (20) is composed of only one stage as shown in FIG. 5, if noise ₂ as shown in FIG. Since the pulse width after ₂ is sufficiently wide, the reset signal is generated by the change of both signals of this pulse, and an erroneous clock signal is generated as shown in FIG. 7 (g).

Here, FIG. 7 is a timing chart showing waveforms of respective parts when noise ₂ is mixed in the received data input signal (1). 7th
Figure (a) is the waveform of the received data input signal (1), Figure 7 (b) is D
Waveform of output signal (24) of -FF (21), Fig. 7 (c) is DF
The waveform of the output signal (25) of F (22), FIG. 7 (d) is D-FF (2
Waveform of the output signal (26) of 3), Figure 7 (e) is the OR gate (29)
7 (f) is the waveform of the reset signal (7), and FIG. 7 (g) is the waveform of the clock signal (5).

FIG. 8 is a block connection diagram of a shift register and a change point detection circuit showing another embodiment of the present invention, in which (1), (3),
(7), (21) to (26), (29) to (31) indicate the same or corresponding parts with the same reference numerals in FIG.

In the figure, (40) is a shift register, (41) is a change point detection circuit, (42) is a D-FF with a negative phase output (43), and (44) is a 5-input A.
The ND circuit (45) is a 5-input NOR gate.

FIG. 9 is a timing chart showing the waveform of each part of FIG. 8, and FIG. 9 (a) is the waveform of the received data input signal (1) in which noises ₂ , ₁ , and N ₁ are mixed, FIG. 9 (b) ) Is the waveform of the output signal (24) of the D-FF (21), and FIG. 9 (c) is the output signal (25) of the D-FF (22).
, The waveform of the output signal (26) of the D-FF (23) is shown in FIG. 9 (d), and the waveform of the output signal (43) of the D-FF (42) is shown in FIG. 9 (e).
FIG. 9 (f) shows the waveform of the output signal (30) of the OR gate (29),
9 (g) shows the waveform of the reset signal (7), FIG. 9 (h) shows the waveform of the high-speed clock signal (3), and FIG. 9 (i) shows the clock signal (5).
Is the waveform of.

In the embodiment of FIG. 8, after the D-FF (23), further D-FF (42)
Is added to provide a plurality of negative-phase output stages, and a shift register (40) including four D-FFs is configured. Signal change is detected by AND gate (44) and NOR gate (45) using the positive phase output of FIGS. 9 (b) and (c) and the negative phase output of FIGS. 9 (d) and (e). is doing. Therefore, the reset signal is not generated even for noise pulses of ₂ , ₁ , and N ₁ , which prevents the generation of false clocks. Although the reset signal is not generated in the portion where the data of the same polarity continues and the signal does not change, the clock signal (5) with a sufficiently small phase error is generated because the counter is reset by free running. Data encoding is CMI (Coded
(Mark Inversion) code, which is particularly effective when the code has a small number of consecutive same polarities.

In the above embodiment, the case where the high-speed clock signal (3) is 8 times the fundamental frequency has been described, but the same operation is performed in the case of any other integral multiple such as 16 times, 32 times and 64 times.

The D-FF is inserted so that the reset signal (7) is in the center of the received data input signal (1).
It may be omitted if there is a margin of (8), and conversely multiple DFs
It is also possible to add a fixed amount of delay by inserting F or using other means such as a counter.

Furthermore, it goes without saying that the number of stages of the shift register (20) and the number N of positive-phase output stages and the number M of negative-phase output stages thereof can be set to values other than those of the embodiment shown here according to the noise pulse width to be removed. Absent.

〔The invention's effect〕

The present invention includes an AND gate and a NOR gate, each gate forming a data input signal and a positive phase output of N D type flip-flops forming N stages of the shift register, and M forming M stages after the shift register. The change point of the signal is detected based on the reverse phase output of the D type flip-flops, and the detection result is output to the OR gate to adjust the phase of the output pulse to be the reset signal. No signal is generated.

Therefore, it is possible to obtain a highly accurate clock generation circuit by preventing generation of an incorrect clock.

Further, a reset signal is not generated in a portion where data of the same polarity continues and where there is no change point, but since the counter is reset by self-running, a clock signal with a sufficiently small phase error can be generated.

Furthermore, the coding of data is performed by CMI (Coded Mark Inve
A clock signal with a sufficiently small phase error can be generated even when a code having less continuity of the same polarity, such as a rsion code, is used.

[Brief description of drawings]

1 is a block connection diagram showing an example of a conventional synchronous clock generation circuit, FIG. 2 is a block connection diagram showing an example of a change point detection circuit of the circuit of FIG. 1, and FIG. 3 is FIGS. FIG. 4 is a timing chart showing waveforms of respective parts of the circuit shown in FIG. 4, FIG. 4 is a block connection diagram showing an embodiment of the present invention, and FIG. 5 shows an embodiment of a shift register and a change point detection circuit of the circuit shown in FIG. Block connection diagram, FIG. 6 is a timing diagram showing waveforms of each part of the circuits of FIGS. 4 and 6, FIG. 7 is a timing diagram when noise ₂ is included in the received data input signal, and FIG. 8 is the present invention. FIG. 9 is a block connection diagram of a shift register and a change point detection circuit showing another embodiment of the present invention, and FIG. 9 is a timing chart showing waveforms of respective parts of the circuit of FIG. In the figure, (1) is the received data input signal, (2) is the oscillator,
(3) high-speed clock signal, (4) counter, (5) clock signal, (6) change check circuit, (20) shift register,
(21) to (23) are D type flip-flops, (27) is AND
Gate, (28) NOR gate, (29) OR gate, (40)
Is a shift register, (41) is a change point detection circuit, (42) is a D type flip-flop, (44) is an AND gate, and (45) is N.
It is an OR gate. The same reference numerals in the drawings indicate the same or equivalent parts.

Claims (1)

[Claims] 1. An oscillator for generating a high-speed clock signal having a frequency that is an integral multiple of the fundamental frequency of a data input signal, counting the high-speed clock signal of this oscillator and outputting a clock signal of the same frequency as the fundamental frequency of the data input signal. Counter, N + M number of D-type flip-flops cascaded, means for inputting the data input signal to the shift register and shifting by the high-speed clock signal, the data input signal, before the shift register An ADN gate, which receives the positive-phase outputs of N D-type flip-flops forming N stages and the negative-phase outputs of M D-type flip-flops forming M stages after the shift register, and an AND gate NOR gate having the same input, two inputs of this NOR gate and the AND gate OR gate means for the reset signal to adjust the phase of the output pulses of the OR gate, means for resetting the counter by the reset signal, synchronizing signal generating circuit which includes a to.