JPS57211849A - Bit synchronizing circuit - Google Patents
Bit synchronizing circuitInfo
- Publication number
- JPS57211849A JPS57211849A JP56097943A JP9794381A JPS57211849A JP S57211849 A JPS57211849 A JP S57211849A JP 56097943 A JP56097943 A JP 56097943A JP 9794381 A JP9794381 A JP 9794381A JP S57211849 A JPS57211849 A JP S57211849A
- Authority
- JP
- Japan
- Prior art keywords
- clock
- bit
- flop
- flip
- gates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To detect the highly accurate rise of a bit by detecting the rise of an input data bit through a flip-flop which is actuated by a clock n times of the data transmitting speed. CONSTITUTION:Input data (a) is inputted to a terminal J of a J-K flip-flop 1 and the flip-flop 1 is set up by the fall of a clock (b). A gate signal (f) from a terminal Q and the clock (b) are applied to an AND gate G2 and an outputted clock (g) is counted up by a counter G8. Outputs (h), (i), (j) from the counter G8 are decoded by a decoder consisting of gates G3, G4 and the decoded output is applied to a shift register G9 as a shift pulse, i.e., a bit syncyronous signal K. Switches S1, S2, S3, pull-up resistances R1, R2, R3 and gates G1, G2, G3 are prepared for setting up the timing position of the generation of the synchronous pulse K, which can be set up on an optional position by changing over the switches S1, S2, S3.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56097943A JPS57211849A (en) | 1981-06-23 | 1981-06-23 | Bit synchronizing circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56097943A JPS57211849A (en) | 1981-06-23 | 1981-06-23 | Bit synchronizing circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57211849A true JPS57211849A (en) | 1982-12-25 |
Family
ID=14205745
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56097943A Pending JPS57211849A (en) | 1981-06-23 | 1981-06-23 | Bit synchronizing circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57211849A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60224346A (en) * | 1984-04-23 | 1985-11-08 | Mitsubishi Electric Corp | Synchronizing clock generating circuit |
-
1981
- 1981-06-23 JP JP56097943A patent/JPS57211849A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60224346A (en) * | 1984-04-23 | 1985-11-08 | Mitsubishi Electric Corp | Synchronizing clock generating circuit |
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