JPS5789364A - Pulse signal regenerative repeating installation - Google Patents
Pulse signal regenerative repeating installationInfo
- Publication number
- JPS5789364A JPS5789364A JP16450780A JP16450780A JPS5789364A JP S5789364 A JPS5789364 A JP S5789364A JP 16450780 A JP16450780 A JP 16450780A JP 16450780 A JP16450780 A JP 16450780A JP S5789364 A JPS5789364 A JP S5789364A
- Authority
- JP
- Japan
- Prior art keywords
- output
- signal
- pulse
- frequency divider
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/20—Repeater circuits; Relay circuits
- H04L25/24—Relay circuits using discharge tubes or semiconductor devices
- H04L25/242—Relay circuits using discharge tubes or semiconductor devices with retiming
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
Abstract
PURPOSE:To simplify the constitution and correct automatically the phase difference between input and output pulses, by providing a frequency divider which is operated by the output of a circuit which is set by the AND between the input pulse and a clock pulse and stores the operation stage. CONSTITUTION:An output (b) of a clock pulse generator CLG which generates the clock pulse (b) of a period sufficiently shorter than the pulse width indicating one bit of an input signal (a) given to a terminal IN is inputted to an AND gate G1 together with the signal (a), and an FF1 is set by the AND between the signal (a) and the output (b). By this set, the FF1 stores the operation state hereafter. A frequency divider DV and an FF2 are operated by the output of the FF1, and the frequency divider DV divides the pulse (b). The FF2 is set or reset by the signal (a) and this divided pulse, and the disaccord of the signal (a) with the output of the FF2 is detected to reset the FF1, and the output of the FF2 is transmitted as a reproduced output (h) to an output terminal OUT.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16450780A JPS5789364A (en) | 1980-11-25 | 1980-11-25 | Pulse signal regenerative repeating installation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16450780A JPS5789364A (en) | 1980-11-25 | 1980-11-25 | Pulse signal regenerative repeating installation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5789364A true JPS5789364A (en) | 1982-06-03 |
Family
ID=15794466
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16450780A Pending JPS5789364A (en) | 1980-11-25 | 1980-11-25 | Pulse signal regenerative repeating installation |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5789364A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61128653A (en) * | 1984-11-27 | 1986-06-16 | Nec Corp | Digital information receiving and reproducing device |
-
1980
- 1980-11-25 JP JP16450780A patent/JPS5789364A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61128653A (en) * | 1984-11-27 | 1986-06-16 | Nec Corp | Digital information receiving and reproducing device |
| JPH0518300B2 (en) * | 1984-11-27 | 1993-03-11 | Nippon Electric Co |
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