JP2001202231A - Parallel data counting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the constitution by using a counter as least as possible. SOLUTION: This parallel data counting device for counting the total number of data of 1 included in a prescribed clock period in parallel data c constituted of plural bits inputted synchronously with a clock is provided with a bit adder 13 for successively adding and outputting the number of data of 1 included in the parallel data synchronously with the clock and an accumulating part 14 for accumulating the number of data of 1 successively outputted synchronously with the clock from the bit adder 13 for prescribed clocks, and for outputting this result as the total number of data of 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel data counting device for counting the number of 1 data in parallel data of a plurality of bits sequentially input in synchronization with a clock.

[0002]

2. Description of the Related Art As one of test methods for testing that various digital communication systems operate normally, a test signal is applied to a test target system, and a bit included in the test signal passed through the test target system. Techniques for measuring the error occurrence rate have been put to practical use.

FIG. 8 is a schematic diagram showing a test system employing the above-described method. The parallel test data a of n bits is applied from the test signal generator 1 to the test target system 2 such as a transmission line. The parallel test data a ₁ passed through the test target system 2 is directly input to the comparator 3 and also to the signal reproducing unit 4. The signal reproducing unit 4 outputs the parallel test data a
_{Using 1} , parallel test data a ₂ equal to the original parallel test data a is created and sent to the comparator 3.

The comparator 3 is composed of, for example, n EXORs (exclusive OR circuits), and compares data (bit data) at the same bit position in the input test data a ₁ and a ₂ having an n-bit configuration. Then, the error detection data is output as "0" in the case of a match and "1" in the case of a mismatch. Therefore, the comparator 3 as a whole outputs parallel detection data b having an n-bit configuration. The n-bit parallel detection data b output from the comparator 3 is input to the next parallel data counter 5.

[0005] The parallel data counter 5 counts and outputs the total number of 1s included in the input n-bit parallel detection data b within a predetermined clock period. As described above, the error occurrence rate of the test target system 2 can be measured with the total number of 1 data.

The parallel data counter 5 incorporated in such a test system is configured, for example, as shown in FIGS. 9 and 10 (JP-A-8-102657). 9 and 10, it is assumed that the parallel data (parallel detection data b) input to the parallel data counter 5 has a 4-bit configuration for the sake of simplicity.

Each bit data of the parallel data is input to each counter circuit 6a, 6b, 6c, 6d via input terminals 7a, 7b, 7c, 7d, respectively. A clock signal CK input from the clock input terminal 8 is applied to each counter circuit 6a, 6b, 6c, 6d, and a holding signal (latch signal) LT input from the holding input terminal 9a is applied. The reset signal RE input from the reset input terminal 9b is applied.

Each of the counter circuits 6a, 6b, 6c,
6d, as shown in FIG. 10, comprises a counter 10a and a holding circuit 10b connected in series. Each counter 10a of each of the counter circuits 6a to 6d has a function of counting up the number of 1 data included in the data at the corresponding bit position every time the clock of the clock signal CK is input. Holding circuit 10 for each of counter circuits 6a to 6d
b, when the hold signal LT is input from the hold input terminal 9a, the number of 1 data output from the counter 10a is fetched and held, and the output terminals 11a, 11b, 11c, and 1b are held.
The data is output as data numbers Sa, Sb, Sc, and Sd from 1d to 1.

In the parallel data counter 5 having such a configuration, first, a reset signal RE is output from the reset input terminal 9b to reset the count value of each counter 10a of each of the counter circuits 6a to 6d to zero. Then
Each counter 10a counts up the number of 1 data included in the data at the corresponding bit position every time the clock of the clock signal CK is input. When a predetermined clock period (period) ends, when a holding signal LT is input from the holding input terminal 9a, a predetermined clock period (period) is output from the output terminals 11a to 11d of the counter circuits 6a to 6d. The number Sa, Sb, Sc, and Sd of 1 data included in the data at each bit position in is output. Then, the holding signal LT is input every predetermined clock period. The data numbers Sa, Sb, Sc, and Sd are held during the next predetermined clock period (cycle).

The data numbers Sa, Sb, Sc, S
The number of data obtained by adding d (Sa + Sb + Sc + Sd) is
This is the total number of 1 data included in a predetermined clock period (cycle) of the input parallel data.

The specific calculation of the total number of 1 data is performed as follows. First, when the data held in a certain clock period in the counter circuit 6a is Sa and the data held in the next predetermined clock period is (Sa + 1), the number of 1s in the predetermined clock period counted by the counter circuit 6a is: (Sa + 1−Sa). If this value is negative, the maximum value Smax of the counter is considered and [(Smax
+ Sa + 1) -Sa] is the value of 1 in the predetermined clock period. This process is performed by all the counter circuits 6a to 6d.
The sum of these is one data sum in a predetermined clock period.

[0012]

However, FIG.
The parallel data counter 5 configured as shown in FIG. 10 also has the following problem to be solved.

That is, as shown in FIG. 9, the number of counter circuits 6a corresponding to the number of bits of the input parallel data is
~ 6d is required. For example, in the example shown in FIG. 9, the number of bits of parallel data is set to 4 for simplicity of description, but in an actual digital communication system,
Since the number of bits of the parallel data may be as large as 100 to 200, the circuit configuration is complicated.

The parallel data counter 5 shown in FIG. 9 requires an adder for adding the number of data Sa, Sb, Sc, and Sd output from each of the counter circuits 6a to 6d. Become complicated.

The present invention has been made in view of such circumstances, and by using an adder, the number of counters used can be reduced as much as possible, and the total number of 1 in parallel data can be counted with a simple circuit configuration. It is an object of the present invention to provide a parallel data counting device capable of performing such operations.

[0016]

The present invention is applied to a parallel data counting device for counting the total number of data included in a predetermined clock period in parallel data of a plurality of bits input in synchronization with a clock. .

In order to solve the above problem, a parallel data counting device according to the present invention includes a bit adder that sequentially adds and outputs one data number included in parallel data in synchronization with a clock; An accumulator for accumulating the number of 1 data sequentially output from the bit adder in synchronization with the clock for a predetermined clock and outputting the result as the total number of 1 data.

In the parallel data counting device configured as described above, when one clock in the clock signal is input, the bit adder adds one of the bit data of the parallel data to add one. Output as the number of data. Then, the number of data of each 1 sequentially output from the bit adder in synchronization with the clock is accumulated by the accumulator for a predetermined clock.

As described above, since the function of counting the total number of 1 data can be constituted by the bit adder and the accumulator, the circuit configuration of the entire parallel data counting device can be simplified.

In another aspect of the present invention, the bit adders in the parallel data counting device according to the above-described invention are connected in a hierarchical tree, and include a plurality of adders having a plurality of input terminals and one output terminal. It consists of.

Each of the adders located at the forefront stage adds one data at a different bit position of the parallel data input to each input terminal to obtain a new one data number, which is added to the subsequent stage from the output terminal. To the input terminal of the adder. Further, each adder located at the intermediate stage adds the number of data of each one inputted from the output terminal of the adder located at the preceding stage and adds it to the adder located at a subsequent stage from the output terminal as a new data number of one. To the input terminal. Finally, the adder located at the last stage adds the number of data of each one inputted from the output terminal of each adder located at the preceding stage to form a new number of data from the output terminal to the accumulator. Send out.

In the parallel data counting device configured as described above, when the number of bits of the parallel data input to the bit adder is large, the bit adder is replaced by a plurality of adders connected in a hierarchical tree. By configuring
For example, the bit adder can be configured by a combination of commercially available small adders.

In another aspect of the invention, the accumulator in the parallel data counting device of the invention described above has the same bit configuration as the output data of the bit adder, and the ones sequentially output from the bit adder. An accumulator accumulates the number of data for a predetermined clock, and a carry counter for counting the number of carry signals output from the accumulator.

In the parallel data counting device configured as described above, if the clock period for accumulating the number of 1 data is long, the total number of 1 data accumulated in the accumulating section becomes large. An accumulator is required. Therefore,
In the present invention, since the accumulator is constituted by an accumulator having the same bit configuration as the bit adder and a carry counter, the clock period (period) for accumulating the number of 1 data becomes longer. Even so, a parallel data counting device can be realized with a minimum necessary circuit configuration.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram showing a schematic configuration of a parallel data counting device according to a first embodiment of the present invention.

The N-bit parallel data c input from the input terminal 12a is input to a bit adder 13 composed of one-chip circuit elements. The clock signal CK synchronized with the bit rate of the parallel data c input from the clock input terminal 12b is applied to the bit adder 13 and each clock terminal CP of the accumulator 15 of the accumulator 14.

Also, for example, a clear signal (reset signal) C output from a data processing unit 18 such as a computer.
L is the accumulator 15 of the accumulator 14 and the carry counter 1
6. Applied to the holding circuit 17. Further, the holding signal (latch signal) LT output from the data processing unit 18 every predetermined clock period is input to the holding circuit 17 of the accumulating unit 14.

As shown in FIG. 2, the bit adder 13
It has N input terminals 1A-NA and M output terminals 1B-MB, and each time a clock of the clock signal CK is input to the clock terminal CP, the N input terminals 1A-N
The data applied to A is added. Since the data of "0" is still "0" even when the data of "0" is added, the data of "1" substantially applied to each of the N input terminals 1A to NA is added. The addition result is output as binary digital data from the M output terminals 1B to MB.

The M-bit parallel data d output from the bit adder 13 is input to the M-bit accumulator 15 of the accumulator 14. In this accumulator 15, for example, as shown in FIG. 3, every time the clock of the clock signal CK is input to the clock terminal CP, the M bit output from the bit adder 13 applied to the input terminal A is output. The parallel data d having the configuration and the parallel data e output from the output terminal D and input to the input terminal B are added, and output from the output terminal D as parallel data e having an M-bit configuration.

Therefore, in this accumulator 15,
Every time the clock of the clock signal CK is input, the number of 1 data applied to the input terminal A is accumulated and applied to the holding circuit 17 as M-bit parallel data e. When a carry occurs in the process of accumulating the number of 1 data, the carry signal f is sent to the carry counter 16. Carry counter 16 counts the number of input carry signals f and sends the result to next holding circuit 17 as K-bit parallel data j.

The accumulator 15 and carry counter 1
When a clear signal (reset signal) CL is input from the data processing section 18 at the start of the measurement, 6 clears the accumulated value and the counted value, and starts the accumulation and counting. The period of the holding signal latch signal (LT) output from the data processing unit 18 to the holding circuit 17 is calculated by accumulating the number of 1 data obtained in synchronization with each clock of the clock signal CK, and , Is equal to a predetermined clock period (cycle). Each time the holding signal (latch signal) LT is input, the holding circuit 17 holds the current accumulated value and count value of the accumulator 15 and the carry counter 16 until the next predetermined clock period elapses.

The operation of the parallel data counting device according to the first embodiment thus configured will be described with reference to a time chart shown in FIG. In this embodiment, the predetermined clock period (period) is four clock periods (period).

In synchronization with each clock of the clock signal CK
A in parallel data c₁, A_Two, A _Three, A_Four, A_Five, A₆,
A₇, A₈, A₉, A_Ten, A₁₁,… Each bit is added
The signals are sequentially input to the arithmetic unit 13. As a result, bit adder 1
Each data A is delayed by one clock from output terminal 3₁~ A
₁₁Number of 1 data B included in₁, B_Two, B_Three, B_Four, B_Five,
B₆, B₇, B₈, B₉, B_Ten, B₁₁, ... parallel data d
Is output. When the hold signal LT is output, the accumulation and totalization are performed.
The number is held in the holding circuit 17.

Therefore, the data in the parallel data c
At the timing when A ₆ is input, the holding circuit 17 outputs from the holding circuit 17 the data number E ₁ of the lower M bits in the total data number B ₁ , B ₂ , B ₃ , and B ₄ and the upper K in the total data number. Bit data F ₁ is held for a predetermined clock period. As a result, the data number [F ₁ , E ₁ ] that is ₁ / the predetermined clock period is input to the data processing unit 18.

The data processing section 18 calculates the total number of 1 data of the whole parallel data c input as follows.
For example, in FIG. 4, if the data in a certain clock period is [F ₀ , E ₀ ] and the data in the next predetermined clock period is [F ₁ , E ₁ ], the total number of data in the predetermined clock period is [F ₀ , E ₁ ]. ₁ , E ₁ ] − [F ₀ , E ₀ ] = B ₁ + B ₂ + B ₃ + B ₄
Becomes When the count value of the carry counter makes one round, a complement is taken, and the total number of one data in the predetermined click period is [1, F ₁ , E ₁ ] − [F ₀ , E ₀ ].

This will be described below using specific numerical values. Assuming that the carry counter 16 and the accumulator 15 can calculate up to 1000 at a certain timing, if the held data is 300 at a certain timing and the held data after the next clock period is 458, the number of 1 data during that period is 458−
300 is 158. If it is 218 after the next clock period, 218-458 will be a negative number. Therefore, it is considered that the current held data does not exceed 1000, the held data is set to 1218, and 1218-458 = 760 is the number of 1 data in the current clock period.

In the parallel data counting device of the first embodiment thus configured, when one clock of the clock signal CK is input, the bit adder 13
One data of each bit data in the input parallel data d is added and output as one data number. Then, the number of data B ₁ , B ₂ , B ₃ , 1 for each 1 sequentially output from the bit adder 13 in synchronization with the clock
B ₄ , B ₅ , B ₆ , B ₇ , B ₈ , B ₉ , B ₁₀ , B ₁₁ ,... Are accumulated by the predetermined clock accumulating section 14. Then, each accumulation result, that is, the total number of data of each 1 [F ₁ , E ₁ ],
[F ₂ , E ₂ ], [F ₃ , E ₃ ], [F ₄ , E ₄ ],... Are input to the data processing unit 18.

As described above, one data number [F₁, E₁],
[F_Two, E_Two], [F_Three, E_Three], [F _Four, E_Four],…
Function can be constituted by the bit adder 13 and the accumulating unit 14.
Therefore, compared with the conventional parallel data counter 5 shown in FIG.
In comparison, the circuit configuration of the entire parallel data counting device can be simplified.
Wear.

Further, in the parallel data counting device of the first embodiment, the accumulator 14 has an accumulator 15 having the same M-bit configuration as the output data of the bit adder 13;
The accumulator 15 includes a carry counter 16 for counting the number of carry signals f.

Therefore, even if the clock period (period) for accumulating the number of 1 data is significantly increased, it is not necessary to change the specification of the accumulator 15 and the change of the specification of the carry counter 16 occurs. Probability can be greatly reduced,
A parallel data counting device can be realized with a minimum necessary circuit configuration.

As an example of the parallel data counting device, the input parallel data c has a 128-bit configuration (N =
128), and the parallel data d output from the bit adder 13 has a 7-bit configuration (M = 7).
Is 7 bits (M = 8). Further, the carry counter 16 has a bit configuration of 25 bits (K = 25). As a result, the data processing unit 18
Two-bit data is input.

(Second Embodiment) FIG. 5 is a block diagram showing a schematic configuration of a bit adder 19 in a parallel data counting device according to a second embodiment of the present invention. The configuration of the accumulator 14 and the data processor 18 other than the bit adder 19 is the same as that of the parallel data counter of the first embodiment shown in FIG.

As shown, the bit adder 19 in the second embodiment is composed of a plurality of adders 20a, 20b, 20c and 20d arranged in a hierarchical tree. Each adder 20a, 20b, 20c, 2 at each stage
0d is two or three input terminals A, B, C, respectively.
And one output terminal D. Each adder 20
a, 20b, 20c, and 20d add the number of data of 1 inputted from each of the input terminals A to C, and output the result as a new number of data of 1 from the output terminal D.

More specifically, each of the adders 20a located at the forefront stage calculates the number of quotients obtained by dividing the number of bits N of the parallel data c input to the parallel data counting device by 3 which is the number of input terminals. N / 3 pieces are arranged. Then, 1 data at different bit positions of the parallel data c is applied to the input terminals A, B, and C of all the adders 20a. Each adder 20a located at the forefront stage
Is added to the bit data of “1” or “0” applied to its own input terminals A, B, and C in synchronization with the clock input of the clock signal CK, and added to the output terminal as a new data number of 1 Intermediate stage adder 2 located downstream from D
0b to the input terminals A and B.

On the other hand, each adder 20b located at the intermediate stage
Has two input terminals A and B and one output terminal D,
In synchronization with the clock of the clock signal CK, each of the 1's input from the output terminal c of the adder 20a located at the preceding stage thereof is
, And the resulting data is sent from the output terminal D to the input terminal of the adder 20c located at the subsequent stage.

The adder 20d located at the last stage
Calculates the M-bit parallel data d from the output terminal d to the accumulator 14 by adding the number of data of each 1 inputted from the output terminal of each adder located at the preceding stage to obtain a new number of 1 data.
Is sent.

Even in the bit adder 19 configured as described above, similarly to the bit adder 13 of the first embodiment shown in FIG. 2, the input N is synchronized with the clock of the clock signal CK. The number of 1s included in the parallel data c of bits is sequentially added and sent to the next accumulator 14 as parallel data d of M bits.

FIG. 6 is a time chart showing the operation of the parallel data counting device according to the second embodiment. Assuming that the bit adder 19 of the parallel data counting device according to the second embodiment has five stages, A ₁ , A ₂ , and so on in the parallel data c are synchronized with each clock of the clock signal CK.
_{A 3, A 4, A 5} , A 6, A 7, A 8, A 9, A 10, A 11, ...
After five clocks have elapsed from the start of the input of each data to the bit adder 19 in sequence, the number of ₁ data B ₁ , 1 contained in each of the data A _{1 to} A ₁₁ is output from the output terminal of the bit adder 19.
_{B 2, B 3, B 4} , B 5, B 6, B 7, B 8, B 9, B 10,
Output of the parallel data d of B ₁₁ ,. The subsequent operation is the same as the time chart of the first embodiment shown in FIG.

Therefore, it is possible to achieve almost the same operation and effect as the parallel data counting device of the first embodiment shown in FIG.

Further, in the parallel data counting device according to the first embodiment, as shown in FIG.
9, a plurality of small adders 2 connected in a hierarchical tree
0a, 20b, 20c, and 20d. Therefore, when the number of bits of the parallel data c input to the bit adder 19 is large, the small adders 20a, 20b,
By increasing the number of installations 20c and 20d, the bit adder 19 having the desired function can be simply created.

(Third Embodiment) FIG. 7 is a block diagram showing a schematic configuration of a parallel data counting device according to a third embodiment of the present invention. The same portions as those of the parallel data counting device of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and detailed description of the overlapping portions will be omitted.

In the parallel data counting device according to the third embodiment, the accumulator 21 is provided with the carry counter 16 shown in FIG.
, And is constituted by one accumulator 22 and one holding circuit 23. That is, the bit configuration of the accumulator 22 is set to a (M + K) bit configuration that also includes the function of the carry counter 16 so that the carry signal f of a carry is not generated.

Therefore, the data number e _{2 of} one output from the accumulator 21 is applied to the holding circuit 23, and every time a predetermined clock period (cycle) elapses, the total number of one data included in the predetermined clock period is counted. Is held in the holding circuit 23 and sent to the data processing unit 18.

In the parallel data counting device of the third embodiment configured as described above, the carry counter 16 can be omitted, so that the configuration can be further simplified.

It is needless to say that the total number of data "0" can be counted instead of the total number of data "1" by adding a sign inverting circuit before the bit adder 13.

[0056]

As described above, in the parallel data counting device of the present invention, using the bit adder and the accumulator, the bit adder adds 1 data at each bit position in each clock by the bit adder. The number of 1 data obtained by the bit adder is accumulated for a predetermined clock to obtain the final total number of 1 data.

Therefore, the number of counters to be used can be reduced as much as possible, and the total number of 1 in parallel data can be counted with a simple circuit configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a parallel data counting device according to a first embodiment of the present invention.

FIG. 2 is a detailed configuration diagram of a bit adder in the parallel data counting device of the first embodiment.

FIG. 3 is a detailed configuration diagram of an accumulator in the parallel data counting device of the first embodiment.

FIG. 4 is a time chart showing the operation of the parallel data counting device according to the first embodiment;

FIG. 5 is a detailed configuration diagram of a bit adder in a parallel data counting device according to a second embodiment of the present invention.

FIG. 6 is a time chart showing the operation of the parallel data counting device according to the second embodiment;

FIG. 7 is a block diagram showing a schematic configuration of a parallel data counting device according to a third embodiment of the present invention.

FIG. 8 is a schematic diagram showing a test system that employs a technique for measuring a bit error rate included in a test signal.

FIG. 9 is a block diagram showing a schematic configuration of a parallel data counter incorporated in the test system.

FIG. 10 is a block diagram showing a detailed configuration of a counter circuit incorporated in the parallel data counter.

[Explanation of symbols]

 13, 19 bit adder 14, 21 accumulator 15, 22 accumulator 16 carry counter 17, 23 holding circuit 18 data processing unit 20a, 20b, 20c, 20d adder,

Claims (3)

[Claims] 1. A parallel data counting device for counting the total number of 1 data included in a predetermined clock period in parallel data (c) of a plurality of bits inputted in synchronization with a clock, wherein: A bit adder (13,) for sequentially adding and outputting the number of 1 data included in the parallel data
19), and an accumulator (14, 21) for accumulating the number of 1 data sequentially output from the bit adder in synchronization with the clock for the predetermined clock and outputting as a total number of 1 data. Parallel data counting device. 2. The bit adder (19) comprises a plurality of adders (20a to 20d) connected in a hierarchical tree and having a plurality of input terminals and one output terminal. Each of the adders (20a) located at the different stages of the parallel data input to the respective input terminals adds one data at a different bit position and generates a new data number of one from the output terminal to a subsequent adder (20a). 20b), and each of the adders (20b to 20c) located in the intermediate stage adds the number of data of each one input from the output terminal of the adder located in the preceding stage to form a new one. The number of data is sent from the output terminal to the input terminal of the adder located at the subsequent stage, and the adder (20d) located at the final stage receives the number of data of each 1 inputted from the output terminal of each adder located at the preceding stage. Is added and the number of new 1 data 2. The parallel data counting device according to claim 1, wherein the data is transmitted from an output terminal to the accumulation unit. 3. The accumulator (14) has the same bit configuration as output data of the bit adder, and accumulates the number of 1 data sequentially output from the bit adder for the predetermined clock. An accumulator (15) and a carry counter (1) for counting the number of carry signals output from the accumulator.
The parallel data counting device according to claim 1 or 2, further comprising (6).