JP3169922B2 - Signal transfer circuit for asynchronous signals - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous signal transfer circuit, and more particularly to an asynchronous signal transfer circuit having a small circuit size and suitable for LSI.

[0002]

2. Description of the Related Art Conventionally, in a digital transmission device for transmitting a digital signal, a clock serving as a reference for transmitting a transmitted signal differs between digital networks or between a digital transmission device and a digital network. The signal transfer operation is performed so that the transmission signal is transmitted in synchronization with the clock of the transmission destination.

That is, a clock of a transfer signal received by a digital transmission device, this transfer signal is transferred to another signal before transfer, and a signal after transfer is transmitted to the digital network. In the case of an asynchronous signal having a different speed from the transmission clock to be transmitted, the digital transmission device controls the signal so as to synchronize the received transfer signal with the transmission clock of the post-replacement signal, thereby performing the signal transfer.

FIG. 4 shows a block diagram of such a conventional signal transfer circuit for an asynchronous signal, which will be described.

FIG. 4 shows a circuit for holding a transfer signal 1 and a transfer instruction signal 2 for designating a specific time when a signal at only a specific time is to be changed. Is shown.

In FIG. 4, a signal received by the signal transfer circuit is a transfer signal 1, a transfer instruction signal 2 for indicating which signal in the transfer signal 1 is to be transferred, and a signal before the transfer. The signal 16 is a signal output from the signal transfer circuit and is a signal 17 after the transfer.
Further, the clock of the transfer signal 1 is supplied from an external circuit (not shown) as the clock 8 of the transfer signal, and the clock of the signal 16 before the transfer and the signal 17 after the transfer is an external clock (not shown) as the clock 9 of the signal after the transfer. Supplied from the circuit.

The counter 4 is a counter which counts up with the clock 8 of the transfer signal when the transfer signal 1 is a significant valid signal, and its output is connected to the decoder 18. The decoder 18 decodes the output value of the counter 4 and outputs it, and the holding circuit 19 (19-1 to 19-
α) are respectively connected to the enable terminals EN. The number of output signal lines of the decoder 18 is equal to the number of the holding circuits 19, that is, α. Here, α is the number of valid signals for which the transfer signal 1 is significant, and is equal to the number of the holding circuits 19.

[0008] The holding circuit 19 has the transfer signal 1 having the number of significant valid signals, that is, α.
And a transfer holding instruction signal 2 and a decoder 1
8, the signals are captured and held, and the held transfer signal 1 is connected to the α-1 SEL 20, and the held transfer instruction signal 2 is sent to the α-1 SEL 21
Connected to

Α-1SEL20 and α-1SEL21 are
The output of the counter 7 becomes an address, and one output is selected from the α holding circuits and output. The counter 7 is a counter that counts up with the clock 9 of the post-replacement signal when the pre-replacement signal 16 is a significant valid signal,
The output is input to the addresses of α-1SEL20 and α-1SEL21. α-1 SEL 20 is a holding circuit 19
Circuit for selecting the transfer signal held in the .alpha.-1
The SEL 21 is a circuit for selecting the transfer instruction signal held in the holding circuit 19, and the output of the α-1 SEL 20 is connected to the 2-1 selector 15, and the α-1 SEL 21
Is connected to the address of the 2-1 selector 15.

The 2-1 selector 15 outputs the signal 1 before transfer.
6 and the output of the α-1 SEL 20 are selected by the output of the α-1 SEL 21, and output as the post-transfer signal 17.

Next, the operation of the block diagram of the conventional example shown in FIG. 4 will be described with reference to the timing chart of the conventional example of FIG.

FIG. 5 shows that the transfer signal 1 has 7 signals from A to G.
, I.e., when α is 7, the transfer instruction signal 2
Is a diagram exemplifying a case where an instruction is given to change the first, third and sixth signals, that is, three A, C and F. FIG.

The signals 16 before transfer are a, b, c,
In the example shown in FIG.

The transfer signal 1, that is, A to G is received at the clock 8 of the transfer signal, and the transfer instruction signal 2 is High at the same clock and at the first, third and sixth signals, Elsewhere is Low. Here, High indicates that signal transfer is performed, and Low indicates that signal transfer is not performed. The output of the counter 4 is counted up to 1, 2, 3 or more when the transfer signal 1 is a significant valid signal, that is, A to G. The outputs of the decoder 18 are 1 to
There are seven lines up to 7, and each output is High corresponding to the output of the counter 4.

There are seven holding circuits 19 in which the number of transfer signals 1 is the same as the number 7 of significant valid signals.
9-1 to 19-7 hold A to G, and hold the transfer instruction signal 2 as High when there is a transfer instruction and Low when there is no transfer instruction.

Signal 16 before transfer, ie, a, b, c, d
Are received at the clock 9 of the signal after transfer, and the output of the counter 7 is counted up to 1, 2, 3, 4 and so on when the signal 16 before transfer is a significant valid signal.

In the above state, α-1SEL2
0 sequentially outputs the transfer signals A to G held in the holding circuit 19 in synchronization with the outputs 1, 2, 3, 4 to of the counter 7, and the α-1 SEL 21 outputs the counters 1, 3, 3,
In the case of 6, the output signals instructing the transfer are sequentially output as High.
Output as

Finally, the 2-1 selector 15 receives the pre-replacement signal 16 and the output of the α-1 SEL 20, that is, the transfer signal, and when the output of the α-1 SEL 21 is High, that is, when there is a transfer instruction. The signal before transfer is transferred by the transfer signal and output as a post-transfer signal 17. When the output of α-1 SEL 21 is Low, that is, when there is no transfer instruction, the signal before transfer is directly used as post-transfer signal 17. Output. As a result, the first, third, and sixth signals a, c, and f of the pre-replacement signal 16 are replaced by the transfer signals A, C, and F, and the post-replacement signal 17 is represented by A, b, C, d, and The order of e, F, g ~ is completed, and the signal transfer is completed.

[0019]

The above-described conventional signal transfer circuit for asynchronous signals is, as apparent from FIG.
The number of the holding circuits 19 is required to be equal to the number α of the transfer signals, and there is a problem that the circuit scale becomes larger as the number of the transfer signals increases.

An object of the present invention is to provide a signal transfer circuit of an asynchronous signal which is small in circuit scale and suitable for LSI.

[0021]

A signal transfer circuit for an asynchronous signal according to the present invention includes a transfer signal, a transfer instruction signal for designating which of the transfer signals is to be transferred, and a transfer instruction. A signal transfer circuit of an asynchronous signal that receives a previous signal and outputs a post-transfer signal as a transmission signal, wherein the transfer instruction signal indicates a signal transfer, and A first counter that counts up with a clock, a decoder that decodes the output of the first counter, and a second counter that counts up with the clock of the transfer signal when the transfer signal is a significant valid signal A holding circuit for holding the transfer signal and the output of the second counter only when the output of the decoder indicates that the signal is to be transferred; A third counter that counts up with a clock of the post-replacement signal when the pre-replacement signal is a significant valid signal; an output of the second counter held by the holding circuit; A comparison circuit for determining whether the output and the output signal match; and if the determination result of the comparison circuit indicates a match, the transfer circuit signal held by the holding circuit is output as it is; if not, the holding circuit holds the signal. A mask circuit that invalidates and outputs the transfer signal, a first logical sum circuit that calculates the logical sum of the output signals output from the mask circuit, and a logical sum of the output signals output from the comparison circuit. A second OR circuit to take, the signal before transfer, and the output of the first OR circuit selected by the output signal of the second OR circuit to perform signal transfer and perform the signal after transfer. Out 2-1 a selector for, characterized by comprising a.

Further, the number of the holding circuits, the number of the comparing circuits, and the number of the mask circuits are each the same as the number of the transfer instruction signals instructing the signal transfer.

Further, the first counter counts up with the clock of the transfer signal when the transfer instruction signal indicates the transfer of the signal, and the output thereof is a numerical value starting from 1. The output is input to the decoder.

Further, the decoder decodes and outputs the output of the first counter, and the number of output signal lines is the same as the number of the transfer instruction signals instructing the signal transfer, Further, the output signal line is connected to an enable terminal of the holding circuit.

Further, the second counter counts up with the clock of the transfer signal when the transfer signal is a significant valid signal, and its output is a numerical value starting from 1, and its output is The data is input to the holding circuit.

The holding circuit holds the transfer signal and the output of the second counter only when the output of the decoder indicates that the signal is to be transferred, and outputs the signal from the holding circuit. The transfer signal among the outputs is input to the mask circuit, and the output of the second counter among the outputs from the holding circuit is input to the comparison circuit.

Further, the third counter counts up with the clock of the post-replacement signal when the pre-replacement signal is a significant valid signal, the output of which is a numerical value starting from 1, and The output is input to each of the comparison circuits.

Further, the comparison circuit determines whether the output of the second counter held by the holding circuit matches the output of the third counter, and outputs the determination result to the mask circuit. And a determination result output is also input to the second OR circuit.

Further, the mask circuit sends the transfer signal held by the holding circuit to the first OR circuit as it is when the judgment result of the comparing circuit is coincident, and holds the held signal when the judgment result is inconsistent. The transfer signal held by the circuit is invalidated and sent to the first OR circuit.

Further, the first OR circuit takes a logical sum of output signals output from the mask circuits, and the output is input to the 2-1 selector.

Further, the second OR circuit takes the logical sum of the output signals output from the comparison circuits, and the output is input to the address of the 2-1 selector.

The 2-1 selector receives the pre-transfer signal and the output of the first OR circuit,
When the output signal of the second OR circuit indicates that a signal transfer is performed, the output signal of the first OR circuit is selected and output, and the output signal of the second OR circuit is selected. When the output signal does not indicate a signal change, the signal before change is selected and output.

[0033]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a signal transfer circuit for asynchronous signals according to the present invention.

FIG. 1 shows a case in which, when a signal is transferred only at a specific time, only the transfer signal 1 designated by the transfer instruction signal 2 and the transfer time are held and the signal transfer is performed. Is shown.
In FIG. 1, when only the signal at a specific time indicated by the transfer instruction signal 2 is transferred from the transfer signal 1, the counter 3 operates when the transfer instruction signal 2 indicates the transfer. The transfer signal 1 and the transfer time, that is, the output of the counter 4 are sequentially held by the holding circuit 5-1 and the holding circuit 5-2. The held transfer time is constantly compared with the count value of the counter 7, and the signal transfer is performed at the coincident time. Thus, by preparing the minimum holding circuit 5 and the comparison circuit 11, it is possible to transfer signals.

The signals received by the signal transfer circuit of the present embodiment shown in FIG. 1 include a transfer signal 1 and a transfer instruction signal 2 for instructing which signal in the transfer signal 1 is to be transferred. , The signal 16 before the transfer, and the signal output from the signal transfer circuit of the present embodiment is the signal 17 after the transfer. The clock of the transfer signal 1 is supplied from an external circuit (not shown) as the clock 8 of the transfer signal, and the signal 16 before the transfer and the signal 1 after the transfer
The clock 7 is supplied from an external circuit (not shown) as the clock 9 of the post-change signal.

It should be noted that the signals received and output by the signal transfer circuit of the present embodiment described above are shown in FIG.
1 are the same as the received signal and output signal of the conventional example, and the components corresponding to those shown in FIG. 4 in FIG. 1 are denoted by the same reference numerals or symbols.

In FIG. 1, a counter 3 is a counter which counts up by a clock 8 of a transfer signal when the transfer instruction signal 2 indicates a signal transfer, and its output is a numerical value starting from 1. And its output is connected to the decoder 10. The decoder 10 decodes the output value of the counter 3 and outputs the decoded value.
(5-1 to 5-β) are respectively connected to the enable terminals EN. The number of output signal lines of the decoder 10 is equal to the number of the holding circuits 5, that is, β. Here, β is a number indicating how many signals are to be transferred from the transfer signals 1, that is, the number of signals to be transferred, and is equal to the number of the holding circuits 5.

The holding circuit 5 has the same number as the number of signals to be changed, that is, β, and holds the change signal 1 and the output of the counter 4. The output of the decoder 10 is High.
At the time, that is, only when it is indicated that signal transfer is performed, each output signal is taken in and held. The transfer signal held by the holding circuit 5 is connected to the mask circuit 12 (12-1 to 12-β), and the output of the counter 4 held by the holding circuit 5 is output to the comparison circuit 11 (11-1).
To 11-β). The counter 4 is a counter that counts up with the clock 8 of the transfer signal when the transfer signal 1 is a significant valid signal, and its output is a numerical value starting from 1.

The comparison circuit 11 has as many as the number of the holding circuits 5, that is, β, and when the output of the counter 4 from the holding circuit 5 and the signal 16 before the change are significant valid signals, the clock of the signal after the change An output from the counter 7 which is incremented by the counter 9 is inputted, and a circuit for judging whether or not each output coincides with each other.
(12-1 to 12-β) and the OR circuit 14.

The mask circuit 12 has the same number as the number of the holding circuits, that is, β. If the comparison result of the comparison circuit 11 is the same, the masking circuit 12 sends the transfer signal input from the holding circuit 5 to the OR circuit 13 as it is. In the case of a mismatch, the transfer signal input from the holding circuit 5 is invalidated and sent to the OR circuit 13.

The OR circuit 13 is composed of β mask circuits 12
Is a circuit that takes the logical sum of the transfer signal sent from
The output is sent to the 2-1 selector 15. The logical sum circuit 14 is a circuit for calculating the logical sum of the signals output from the β comparison circuits 11, and the output is input to the address of the 2-1 selector 15.

The 2-1 selector 15 outputs the signal 1 before transfer.
6 and the output of the OR circuit 13 are selected by the output signal of the OR circuit 14 to perform signal transfer, and the signal 17 after the transfer.
Is output.

Next, the operation of the block diagram of one embodiment of the present invention shown in FIG. 1 will be described with reference to the timing chart of the asynchronous signal signal transfer circuit of the present invention shown in FIG.

FIG. 2 is a timing chart exemplifying a case where the number of signals to be changed is three, that is, β is three. The transfer signal 1 is seven signals A to G, and the transfer instruction signal 2 is the first, third, and sixth signals, that is, A,
In this example, a case is indicated in which an instruction is given to change three of C and F. Further, the signal 16 before transfer is a, b,
The case where c, d ~ are continuously received is illustrated.

The transfer signal 1, that is, A to G is received at the clock 8 of the transfer signal, and the transfer instruction signal 2 is High at the same clock and at the first, third, and sixth signals. Elsewhere is Low. Here, High indicates that signal transfer is performed, and Low indicates that signal transfer is not performed. The output of the counter 4 is counted up to 1, 2, 3 or more when the transfer signal 1 is a significant valid signal, that is, A to G. When the transfer instruction signal 2 is High, the output of the counter 3 is 1, 2,.
The counter is up to 3 ~. The decoder 10 has three outputs, 10-1, 10-2, and 10-3, and each output is High corresponding to the output of the counter 3. The holding circuit 5 has the same three as the number 3 of the signals to be changed, and the holding circuit 5-1 holds A of the transfer signal 1 and 1 of the output of the counter 4, and the holding circuit 5-2.
Holds the C of the transfer signal 1 and 3 of the output of the counter 4, and the holding circuit 5-3 holds F of the transfer signal 1 and 6 of the output of the counter 4.

Signal 16 before transfer, ie, a, b, c, d
Are received at the clock 9 of the signal after transfer, and the output of the counter 7 is counted up to 1, 2, 3, 4 and so on when the signal 16 before transfer is a significant valid signal.

The comparison circuit 11 compares the output value of the counter 7 with the output value of the counter 4 held in the holding circuit 5 to judge the coincidence or non-coincidence.
Output h. Therefore, since the output value of the counter 4 held by the holding circuit 5-1 is 1, the comparison circuit 11-1 determines that the output value of the counter 7 is 1 when the output value of the counter 7 is 1, and the comparison circuit 11-1 High is output from the circuit 11-1. Similarly, the other comparison circuits 11-2 and 11-3 determine that the output values of the counter 7 match when the output values are 3 and 6, and output High at that time.

The mask circuit 12 outputs the transfer signal held by the holding circuit 5 when the output of the comparison circuit 11 is High. Accordingly, in this case, when the output of the comparison circuit 11-1 is High, the transfer signal A is output from the mask circuit 12-1. Similarly, the other mask circuits 12-2 and 12-
3 indicates that the outputs of the comparison circuits 11-2 and 11-3 are High.
At this time, transfer signals C and F are output, respectively.

The logical sum circuit 14 calculates the logical sum of the output of the comparison circuit 11 and inputs the logical sum to the address of the 2-1 selector 15. The logical sum circuit 13 calculates the logical sum of the output of the mask circuit 12 and calculates the logical sum of the output of the mask circuit 12. 1 is input to the selector 15.

Finally, the pre-replacement signal 16 and the output of the OR circuit 13 are input to the 2-1 selector 15, and the transfer is performed when the output of the OR circuit 14 is High, that is, when there is a transfer instruction. The previous signal is transferred with the transfer signal and output as the post-change signal 17. When the output of the OR circuit 14 is Low, that is, when there is no transfer instruction, the signal before transfer is output as the post-change signal 17 as it is. As a result, 1 of the pre-transfer signal 16,
The third and sixth signals a, c, and f are transfer signals A, C, and F
, And the signal 17 after the transfer is A, b, C,
The order of d, e, F, g and so on is the completion of the signal transfer.

Next, the scale of the circuit according to the present embodiment will be described with reference to FIGS. The scale of the circuit will be described using the number of gates, which is the basic logic of the logic circuit.

FIG. 3 is a diagram showing the number of gates of the signal transfer circuit according to the present invention and the conventional example. In FIG. 3, (1) shows the number of gates of the signal transfer circuit of the present invention, and (2) Indicates the number of gates of the signal transfer circuit in the conventional example.

FIG. 3 (1) shows the whole of the signal transfer circuit of the present invention shown in FIG. 1 subdivided for each circuit element, and the name of each circuit element is described in the column of circuit name. The number of gates required to configure the element is described in the column of required gate number. For example, the holding circuit 5 of FIG.
Since the number of holding circuits 5 is β from 5-1 to 5-β, the required number of gates of the holding circuit 5 is described as 200 gates × β. Also, the 2-1 selector 15
Describes that the required number of gates is 30 because one circuit is composed of 30 gates. By adding all the necessary gate numbers constituting each circuit element in this way, FIG.
, The number of gates described in the column of calculation formula 1 is required. That is, it can be seen that the number of gates of the signal transfer circuit of the present invention is 282 × β + 330 as shown in Expression 1, which depends on the number β of signals to be transferred.

The required number of gates shown in FIG. 3A is an empirical value calculated by the inventor based on his or her experience in circuit design.

Next, the circuit scale of the conventional signal transfer circuit shown in FIG. 4 will be described with reference to FIG.

Similarly to FIG. 3 (1), FIG. 3 (2) also subdivides the entire signal transfer circuit in the conventional example shown in FIG. 4 for each circuit element, and names each circuit element. The number of gates required to configure each circuit element is described in the column of required gate number. Then, when all necessary gate numbers constituting each circuit element are added, FIG.
The number of gates described in the total column of (2) is obtained, and when arranged, the number of gates described in the column of calculation formula 2 is required. That is, the number of gates of the signal transfer circuit in the conventional example is 164 × α + 250 as shown in Expression 2, which depends on the number α of the transfer signal 1.

The required number of gates shown in FIG. 3B is also an empirical value calculated by the inventor based on his or her experience in circuit design.

Next, the number of gates of the signal transfer circuit according to the present invention and the conventional example will be described with reference to a specific example using Formulas 1 and 2 shown in FIG.

The specific example shown here is the signal transfer circuit shown in FIGS. 1 and 4, where the number of transfer signals 1, ie, α, is 7, and the number of signals to be transferred, ie, β, is 3, Here are some cases.

By substituting the values of α and β into Equations 1 and 2 in FIG. 3, Equation 1 = 282 × β + 33
0 = 282 × 3 + 330 = 1176 gates, and calculation formula 2 = 164 × α + 250 = 164 × 7 + 250 = 13
98 gates. Therefore, the signal transfer circuit proposed in the present invention can reduce the number of gates of the entire circuit as compared with the signal transfer circuit in the conventional example.

[0062]

As described above, the signal transfer circuit for asynchronous signals according to the present invention does not use the number of transfer signals,
Since the scale of the circuit depends on the number of signals to be transferred, the circuit scale does not increase even if the number of signals to be transferred increases, and the scale of the circuit depends on the number of signals to be transferred. This has the effect that the circuit scale can be reduced as compared with the circuit in the conventional example.

Further, since the circuit scale can be reduced, there is an effect that the circuit of the present invention is suitable for use in an LSI.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a signal transfer circuit for an asynchronous signal according to the present invention.

FIG. 2 is a timing chart of an asynchronous signal signal transfer circuit of the present invention.

FIG. 3 is a diagram illustrating the number of gates of a signal transfer circuit according to the present invention and a conventional example.

FIG. 4 is a block diagram of a signal transfer circuit for an asynchronous signal in a conventional example.

FIG. 5 is a timing chart of a conventional example.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 transfer signal 2 transfer instruction signal 3 counter 4 counter 5 holding circuit 7 counter 8 clock of transfer signal 9 clock of signal after transfer 10 decoder 11 comparison circuit 12 mask circuit 13 OR circuit 14 OR circuit 15 2- 1 selector 16 signal before transfer 17 signal after transfer 18 decoder 19 holding circuit 20 α-1SEL 21 α-1SEL

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04J 3/00 H04L 7/00

Claims (12)

(57) [Claims] 1. A transfer signal, a transfer instruction signal for instructing which signal in the transfer signal is to be transferred, and a signal before the transfer, and a signal after the transfer is output as a transmission signal. A first counter that counts up with a clock of the transfer signal when the transfer instruction signal indicates a signal transfer, and an output of the first counter. A second counter that counts up with the clock of the transfer signal when the transfer signal is a significant valid signal, and indicates that the output of the decoder performs signal transfer. A holding circuit for holding the transfer signal and the output of the second counter only when the transfer signal is a significant valid signal; A third counter that counts up with a clock signal, a comparison circuit that determines whether the output of the second counter held by the holding circuit matches the output of the third counter, A mask circuit that outputs the transfer signal held by the holding circuit as it is when the determination result matches, and invalidates and outputs the transfer signal held by the holding circuit when it does not match, A first OR circuit for ORing the output signals output from the mask circuit, a second OR circuit for ORing the output signals output from the comparing circuit, A 2-1 selector for selecting an output of the first OR circuit with an output signal of the second OR circuit, changing the signal, and outputting a signal after the change. Asynchronous communication Signal handoff circuit. 2. The method according to claim 1, wherein the number of the holding circuits, the number of the comparison circuits, and the number of the mask circuits are the same as the number of the transfer instruction signals instructing the signal transfer. Signal transfer circuit for asynchronous signals. 3. The first counter counts up with a clock of the transfer signal when the transfer instruction signal indicates the transfer of a signal, and the output thereof is 1.
2. The signal transfer circuit for asynchronous signals according to claim 1, wherein the value is a numerical value starting with "." 4. The decoder decodes and outputs the output of the first counter, and the number of output signal lines is the same as the number of the transfer instruction signals instructing signal transfer, 2. The signal transfer circuit for asynchronous signals according to claim 1, wherein the output signal lines are connected to enable terminals of the holding circuit, respectively. 5. The second counter counts up with the clock of the transfer signal when the transfer signal is a significant valid signal, and its output is a numerical value starting from 1, and its output is 2. The signal transfer circuit for asynchronous signals according to claim 1, wherein the signals are input to the holding circuits. 6. The holding circuit holds the transfer signal and the output of the second counter only when the output of the decoder indicates that the signal is to be transferred, and outputs the signal from the holding circuit. 2. The output circuit according to claim 1, wherein the transfer signal is input to the mask circuit, and an output of the second counter is output from the holding circuit to the comparison circuit. Signal transfer circuit for asynchronous signals. 7. The third counter counts up with a clock of the post-replacement signal when the pre-replacement signal is a significant valid signal, the output of which is a numerical value starting from 1, and 2. The signal transfer circuit for asynchronous signals according to claim 1, wherein outputs are respectively input to the comparison circuits. 8. The comparison circuit judges whether the output of the second counter held by the holding circuit matches the output of the third counter, and outputs the result of the judgment to the mask circuit. 2. The asynchronous signal transfer circuit according to claim 1, wherein each of the input signals and an output of the determination result are also input to the second OR circuit. 9. The mask circuit sends the transfer signal held by the holding circuit to the first OR circuit as it is when the result of the comparison by the comparison circuit matches, and holds the signal when the result of the mismatch does not match. 2. The signal transfer circuit for asynchronous signals according to claim 1, wherein the transfer signal held by the circuit is invalidated and sent to the first OR circuit. 10. The first logical sum circuit calculates a logical sum of output signals respectively output from the mask circuits,
2. The circuit according to claim 1, wherein the output is input to the 2-1 selector. 11. The method according to claim 11, wherein the second OR circuit performs an OR operation on output signals output from the comparison circuits, and the output is input to an address of the 2-1 selector. Item 2. An asynchronous signal signal transfer circuit according to Item 1. 12. The 2-1 selector receives the pre-replacement signal and the output of the first OR circuit, and the output signal of the second OR circuit performs signal transposition. Is selected, the output signal of the first OR circuit is selected and output. If the output signal of the second OR circuit does not indicate signal transfer, the signal before the transfer is selected. 2. A signal is selected and output.
2. A signal transfer circuit for asynchronous signals according to claim 1.