JP2969233B2 - Method for testing frame format of digital transmission system and frame counter used therein - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of testing a frame format of a digital transmission system and a frame counter used for the method. More specifically, the present invention relates to a SONET (Sync) as a wideband ISDN which is a digital transmission system.
(Hronous Optical NETwork), a repeater for controlling information transmission based on the standard, a test method for a function test of an LSI constituting a terminal device, and a frame counter therefor.
In particular, the present invention relates to a test method of pointer processing for indicating a head position of data in a frame and a frame counter used therein.

[0002]

2. Description of the Related Art SONET STS-N (N represents the number of multiplexes,
In the frame format of ∞), a technique called a frame buffer format as shown in FIG. 1 has conventionally been used. That is, as shown in FIG. 1 (a), when transmitting a signal acquired in synchronization with a reception clock in synchronization with a transmission clock, the signal is acquired in units of one frame and temporarily stored in a memory. Then, as shown in FIG. 1 (b), the data was read from the memory and transmitted.

However, in this case, a delay equal to or longer than a time corresponding to one frame occurs between the reception of one frame and the transmission of the frame, so that it is currently called a pointer format as shown in FIG. Methods are becoming mainstream. That is, as shown in FIG. 2 (a), a pointer for designating the head position of the data in the frame is inserted in the header portion of the frame, and the head position of the data in the received frame is detected in accordance with this. As shown in FIG. 2B, by immediately taking out and transmitting from the received frame, it is possible to transmit with a delay of less than one frame.

FIG. 3 is a schematic diagram showing the structure of a SONET STS-12 (12 multiplex) frame format. One frame is composed of 1080 bytes (90 bytes x 12 multiplexes) x 9 lines. The overhead part is a header for data for transmitting frame synchronization signals or various auxiliary signals, and the payload part for transmitting information signals. And divided into Note that the frame repetition period, that is, one frame period is
125 μs.

The overhead section includes a frame synchronization signal,
Various signals necessary for transmission of multiplexed signals such as an error monitoring code, a channel identification signal, a maintenance channel, and an alarm signal are all included. Taking the first row of the frame as an example, overhead bytes A1, A2, and C1 are each composed of 12 bytes from # 1 to # 12 corresponding to 12 multiplexes, and each byte is composed of 8 bits. ing. The overhead bytes H1 and H2 on the fourth line are pointers for designating the head position of the data.

FIG. 4 is a schematic diagram for explaining the procedure of pointer processing.

Now, for example, as shown in FIG. 4 (a), an overhead byte H
When the value of 1, H2 is "01100000 11010101", the value indicated by the lower 10 bits, that is, "213" of the decimal number
And is operating stably. This pointer value "213
"" Is an actually valid pointer value indicating that the byte following the overhead byte H3 starts counting as the "0" byte and indicating that the 231st byte is the first J1 byte of data, that is, an active pointer value.

In the state shown in FIG. 4A, as shown in FIG. 4B, the values of the overhead bytes H1 and H2 are "01100001 10110011", that is, the normal pointer value = Assume that "435" has been received. However, in this case, even if the pointer value changes, the active pointer value is not changed for the first time but remains at the previous value, in this case, “21”.
3 "is maintained.

Next, as shown in FIG. 4 (c), even when the changed normal pointer value "435" is received twice consecutively, the active pointer value is not changed but remains unchanged. The value, in this case "213" is maintained.

[0010] Then, as shown in FIG.
When the changed normal pointer value "435" is received three consecutive times, the active pointer value is changed to "435" in this case. Therefore, as shown in FIG. 4 (d), the head byte J1 of the data starts counting the next byte of the overhead byte H3 as the "0" byte and is changed to the 435th byte.

The reason why such processing is performed is to eliminate the influence of an error in the value of the overhead bytes H1 and H2 designating the head position of the data.
Therefore, when changing the head position of data, it is necessary to change the pointer value two frames before.

[0012]

By the way, in order to perform a test for confirming the pointer processing function as described above in a digital transmission repeater or terminal equipment, at least one frame is received and the next frame is received. Since it is necessary to check whether or not the pointer value is changed in a frame, a time corresponding to at least two frames, that is, a time of 250 μs is required.

FIG. 5 is a circuit diagram showing a configuration of a frame counter for testing such a pointer processing function, and FIG. 6 is a timing chart thereof.

The frame counter shown in FIG.
A "0" register mainly composed of a 10-bit counter 10 for inputting decimal "0" to initial value setting terminals D1 to D10, that is, all "0" to all bits as an initial value.
12 and outputs a signal "1" when the count value output from the count value terminals Q1 to Q10 becomes "809" in decimal "80".
9 "Register 13 and this" 809 "register 13 is a signal"
When a "1" is output, the signal or a timing signal of 8 kHz, which is a frame clock, is inputted to a load terminal L of a 10-bit counter 10 to load an output signal of a "0" register 12. The 10-bit counter 10 is supplied with a 6 MHz clock, which is a synchronous clock of the input signal, as a counting target.
The counting result is output as a timing signal for receiving and transmitting the frame and performing various other processes.

When the processing of one frame is completed, the count value of the 10-bit counter 10 at that point is as shown in FIG.
As shown in FIG. 5 (d), the signal "1" output from the "809" register 13 or 10-bit counter 10 is shown in FIG.
The 8k timing signal is input to the load terminal L, and the count value of the 10-bit counter 10 is initialized to "0".

At this point, the received signal shown in FIG. 6A is inputted in synchronization with the 6 MHz clock shown in FIG. 6B, and thereafter, the count value of the 10-bit counter 10 becomes 6 MHz.
The clock is counted and sequentially incremented. Then, the count value of the 10-bit counter 10 is decimal “270”,
There are overhead bytes H1 and H2 at the byte position in the frame of "271", and a pointer value designating the J1 byte which is the head position of the data is read. Therefore, the information signal after the J1 byte of the frame being received. As soon as a transmission byte is received, it is output as a transmission signal as shown in FIG. 5 (e). The transmission signal is transmitted in synchronization with the 6 MHz clock for transmission shown in FIG.

As described above, at least a time corresponding to two frames is required for a test for confirming whether or not the head position of data can be actually detected from a pointer value in a certain frame. Testing a function requires time equivalent to several tens of frames.
This has led to an increase in the number of development steps and cost when developing and commercializing.

The present invention has been made in view of the above-mentioned circumstances, and a digital transmission system capable of reducing development man-hours and manufacturing costs by shortening the test of the pointer function of the SONET format. And a frame counter used in the test method.

[0019]

FIG. 7 is a timing chart showing the timing of frame processing for explaining the principle of the frame format test method of the digital transmission system according to the present invention.

FIG. 7A shows the processing timing of a frame in a normal state (hereinafter, referred to as a normal mode). That is, in the STS-1 format in which the number of multiplexing is N = 1, one frame of 810 bytes (90 bytes × 1 multiplexing) × 9 rows is processed in 125 μs.

On the other hand, the processing timing of a frame in a state where the pointer function is tested (hereinafter referred to as a test mode) is shown in FIG. 7 (b). In other words, the overhead of the pointer is used for testing the pointer processing function.
It is sufficient to examine the area from the byte H1, H2 to the last byte of the range that can be specified by this, that is, the last 449th byte of the fifth line of the SONET format. Therefore, as shown in FIG. 7 (b), the 270th byte overhead byte H1 from each frame starts with the first byte.
You only have to extract up to the 449th byte and examine it.
Therefore, it is only necessary to prepare a frame counter capable of generating a timing clock as shown in FIG.

[0022]

[Operation] If the above-described test method is employed and a frame counter for that purpose is used, the overhead byte H1 is headed from each frame.
The last byte of the range that can be specified by H1 and H2
Only 449 bytes are extracted, reducing test time.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments.

FIG. 8 is a block diagram showing the configuration of an embodiment of the frame counter according to the present invention, and FIG. 9 is a timing chart for explaining the operation thereof. Note that, in the present embodiment, as shown in FIG.
The case where the present invention is applied to the format 1 will be described.

As apparent from FIG. 10, the overhead bytes H1 and H2 are the 270th and 271st bytes, respectively, and the J1 byte which is the head of the data may be specified up to the 449th byte.

In FIG. 8, reference numeral 10 denotes a 10-bit counter, which has initial value setting terminals D1 to D10 for setting a 10-bit value as a counting initial value. To set the 10-bit count initial value, a predetermined signal is input to the load terminal L, and at that time, the initial value setting terminals D1 to D1 are set.
The value input to 0 is set as the initial count value.

The initial value setting terminals D1 to D10 are provided with a register holding a decimal "0" via the selector 15.
(Hereinafter referred to as "0" register) 12 and decimal number "270"
(Hereinafter referred to as “270” register) 14. In these, when "1" is given as a select signal to the selector 15, the "270" register 14 is selected. In other words, the decimal value "270" is stored in the initial value setting terminals D1 to D10 of the 10-bit counter 10. When "0" is given, the "0" register 12 is selected. In other words, the initial value setting terminal of the 10-bit counter 10 is set.
A decimal "0" is input to D1 to D10. The select signal supplied to the selector 15 is a test signal TST described later.

A 10-bit counter 10 has a 10-bit count value terminal Q1 to Q10, which outputs a signal "1" when it becomes a decimal "809". The "809" register 13 also outputs a decimal "449". "44" which outputs a signal "1" when it becomes ""
The signals are supplied to the 9 "register 16 and are also output as signals for generating various timings which are the original purpose.

The load terminal L of the 10-bit counter 10 has 3
The input NOR gate 11 is connected. This NOR gate
Each of the three inputs 11 includes an 8k timing signal, which is a frame clock for defining one frame period, and the above-described "
809 "The output of the register 13 and the output of the two-input AND gate 17 are provided.

The outputs of the above-mentioned "449" register 16 and the test signal TST are supplied to both inputs of the AND gate 17, respectively. Note that this test signal TST is, as described above,
The selector 15 is also provided as the select signal.

The operation of the frame counter of the present invention having such a configuration is as follows.

In the normal mode, the test signal TST is "0" (non-active) as shown in FIG.
And the initial value setting terminals D1 to D10 of the 10-bit counter 10
Is a decimal number “0” input from the “0” register 12. As a result, as shown in FIG.
Each time an 8k timing signal is input through gate 11,
As shown in FIG. 9A, the 10-bit counter 10
Counting starts from "0" and the counted value is decimal "809"
At this time, the signal "1" is output from the "809" register 13 and is input to the load terminal L of the 10-bit counter 10 through the NOR gate 11, so that counting is started again from "0". That is, when the test signal TST is non-active, the 10-bit counter 10 repeats counting from "0" to "809".

On the other hand, in the test mode, the test signal TST becomes "1" (active) as shown in FIG. 9D, and the test signal TST is also supplied to the selector 15 as its select signal. So a 10 bit counter
Decimal "270" is input to the ten initial value setting terminals D1 to D10. Then, the 8k timing signal or the output signal of the "809" register 13 as shown in FIG.
When it becomes 1, the 10-bit counter 10 loads a decimal number "270" and thereafter counts 6M clocks as shown in Fig. 9 (a). Upon reaching, a signal "1" is output from the "449" register 16 and supplied to the AND gate 17. Since the test signal TST, which is the other input of the AND gate 17, is also "1", A
The output signal of the ND gate 17 also becomes "1", which is supplied to the load terminal L of the 10-bit counter 10 through the NOR gate 11. Therefore, when the test signal TST is "1", the 10-bit counter 10 repeats counting from "270" to "449".

As described above, in the test mode, the normal mode
180 (= 449-269) counts compared to 810 counts when loading
So that one frame can be processed in 2/9 time
Therefore, when the pointer value is changed as described above,
In a test that requires data for 4 frames,
125 μs × 4 = 500 μs, but according to the present invention,
Then, the test can be performed in 2/9 time, that is, about 111 μs.
Will be. In this way, the frame counter calculates the byte at the head position of the data from the position of the overhead byte H1.
Since the counting is performed so that only the last position where J1 can exist is extracted, if the extracted signal is processed in accordance with the count, a desired test can be performed.

[0035]

As described above , according to the present invention , the SONET
Digital transmission system frame like format
Shorter testing of format pointer functionality
With this, it is possible to reduce development man-hours and manufacturing costs.
Digital transmission system frame format
The test method and the frame counter used
Will be revealed.

[Brief description of the drawings]

FIG. 1 is a schematic diagram for explaining a frame buffer format.

FIG. 2 is a schematic diagram for explaining a pointer format.

FIG. 3 is a schematic diagram illustrating a configuration of a SONET STS-12 (12 multiplex) frame format.

FIG. 4 is a schematic diagram for explaining a procedure of pointer processing.

FIG. 5 is a circuit diagram showing a conventional configuration of a frame counter for testing a pointer processing function.

FIG. 6 is a timing chart for explaining an operation state of a conventional frame counter.

FIG. 7 is a timing chart showing the timing of frame processing showing the principle of the frame format test method of the digital transmission system of the present invention.

FIG. 8 is a block diagram showing a configuration of an embodiment of a frame counter according to the present invention.

FIG. 9 is a timing chart for explaining the operation of one embodiment of the frame counter according to the present invention.

FIG. 10 is a schematic diagram showing the format of STS-1 where the number of multiplexing N = 1.

[Explanation of symbols]

 10 10-bit counter 11 NOR gate 14 "270" register 16 "449" register

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Claims (2)

(57) [Claims] 1. Each frame has a predetermined data amount.
It consists of a header part and a data part.
The position of the specific data (J1) that can be
From the data (J1) at a predetermined position in the header
The frame indicated by the placed location information data (H1, H2)
Synchronizes the signal with the frame format with the input clock
And input the position information data (H1, H
In the frame format method of testing a digital transmission system in which the specific data (J1) to test whether present at a position indicated by 2), from each frame of the input signal, the positional information data
A method for testing a frame format of a digital transmission system, comprising extracting data from the next data after (H1, H2) to the end of a range where the specific data (J1) can exist and testing. 2. Each frame has a predetermined data amount.
It consists of a header part and a data part.
The position of the specific data (J1) that can be
From the data (J1) at a predetermined position in the header
The frame indicated by the placed location information data (H1, H2)
Synchronizes the signal with the frame format with the input clock
And input the position information data (H1, H
In the frame format test frame counter of the particular digital transmission system in which data (J1) to test whether present at a position indicated by 2), a counter (10) for counting the input clock, wherein A register (14) holding the number of the input clocks corresponding to the arrangement position of the position information data (H1, H2), and a count value of the counter (10) and a range in which the specific data (J1) can exist. Means (16) for detecting whether or not the number of the input clocks corresponding to the end position matches; and if the means (16) detects a match, the value held in the register (14) is read. A frame counter for testing a frame format of a digital transmission system, comprising: means (11) for setting the counter (10) as an initial value of a count value.