JPH06204963A - Ndf generating circuit for pointer processing circuit of digital transmission system - Google Patents

Abstract

PURPOSE:To provide an NDF generating circuit which can evade the increase of the circuit scale and the complication of the circuit structure. CONSTITUTION:A pointer value comparing part 8 compares the pointer value of the present frame with the pointer value of the precedent frame latched by a precedent frame pointer part latching part 7. If the coincidence is secured between both pointer values, a normal state is decided and normal NDF is transmitted. If not, no normal state is decided and NDFENABLE is transmitted. Therefore the scale of an NDF generating circuit is never increased even though the NDF generating/transmitting frequency is increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital transmission system, for example, new synchronous multiplex communication such as SONET (Synchronous Optical NETwork), from a clock on the receiving side to a transmitting side on a relay device, a multiple conversion device, etc. The present invention relates to pointer processing when transferring to a clock, and particularly to a New Data Flag (NDF) generation circuit associated with the pointer processing.

[0002]

2. Description of the Related Art FIG. 1 shows SO as a digital transmission system.
FIG. 3 is a schematic diagram showing the structure of the STS frame format of NET. Here, for convenience of explanation, the multiplexing number is 1, that is, ST.
It is a schematic diagram which shows the frame format of S-1.

One frame of SONET is composed of 90 bytes × 9 lines, and is mainly composed of an overhead part which is a header for data for transmitting a frame synchronization signal or various auxiliary signals and a payload part for transmitting an information signal. I know. Each line consisting of 90 bytes is called a subframe, and the signal flow is from the beginning of the first line to the end.
It is repeated from the beginning of the second line to the end.

A frame synchronization signal,
It includes all the various signals necessary for transmission of multiple signals such as error monitoring code, channel identification signal, maintenance channel, and alarm signal. Taking the first line of the frame (first subframe) as an example, the first 3 bytes are fixed as overhead bytes (A1, A2, C1), and the subsequent 87 bytes are the payload part for data. Is. One byte of path overhead (hereinafter referred to as POH) bytes is located in the payload section at a position common to each subframe, and one frame constitutes the path overhead section.

The overhead part consisting of 3 bytes on the head side of each subframe is called a section overhead part for the first to third subframes, and a line overhead part for the other subframes.

As shown in the schematic diagram of FIG. 2, the overhead bytes H1 and H2 of the fourth line (fourth sub-frame), in other words, the overhead bytes H1 and H2 of the first line of the line overhead part, are used to store data. This is a pointer that specifies the J1 byte of the path overhead part, which is the start position. The H1 and H2 bytes of this overhead byte are both 16 bytes, and the lower 10 bits of them indicate the position of the J1 byte that is the first byte of the data in the same frame as a pointer value.

Specifically, the overhead bytes H1 and H2
The byte immediately after the H3 byte following the byte is the count value
Corresponding to the byte "0", the count value from the byte with the count value "0" to the J1 byte is stored in the overhead bytes H1 and H2 as pointer values.

The byte immediately after this H3 byte is "
0 ", and the count value that is continuous in each byte of the payload section over each subframe is SPE (Synchrounous Paylo
ad Envelope) address.

FIG. 3 shows a schematic diagram of a frame format to which an SPE address is added. Here, for example, if the J1 byte is located in the byte next to the H3 byte, the pointer values stored in the H1 and H2 bytes of the overhead byte are H1 = XXXXXX00, H2 = 00000000, that is, SPE address = "0". If it is located at the byte next to the K3 byte, H1 = XXXXXX00, H2 = 01010111, that is, S
If PE address = "87" and the byte is located before the H1 byte, H1 = XXXXXX11, H2 = 000011
10, that is, SPE address = "782". However, the bit in the X part has no meaning as a pointer value.

By the way, as shown in the schematic diagram of FIG. 2, the upper 4 bits of the H1 byte are NDF (New Data F).
lag), which is used as information indicating whether or not the pointer value has been changed.

Specifically, when normal data communication is normally performed, the NDF has a value of "0110".
Normal NDF is sent. However, for example, when the device power is turned on, when a line error occurs (alarm occurrence, input clock cutoff, etc.), when recovery is performed after a memory slip occurs, or when pointer control is performed when staff control is performed. When there is a change in the sending pointer value excluding the change, NDF ENABLE having a value of "1001" is sent as the NDF.

On the other hand, on the receiving side, when Normal NDF is received, the receiving process may be continued as before, but when NDF ENABLE is received, the pointer value used in the subsequent receiving process. Should be immediately changed to the pointer value contained in the H1 and H2 bytes sent with NDF ENABLE. This is to cope with a recovery after a line failure or the like or a sudden change in the pointer value.

Under these circumstances, conventionally, the monitoring for each condition when NDF ENABLE is sent, the monitoring of the change of the pointer value, and the No. based on the staff control are performed.
It manages the sending of rmalNDF and NDF ENABLE. However, in such a conventional method, it is necessary to monitor all NDF sending conditions every time pointer processing is performed, which causes an increase in circuit scale and complexity.

FIG. 4 is a block diagram showing a configuration example of a pointer processing circuit and an NDF generating circuit of a conventional digital transmission system. In FIG. 4, reference numeral 1 indicates a pointer value receiving unit, which receives the pointer value from the H1 and H2 bytes of each frame in the received data received from the outside. The pointer value received by the pointer value receiving unit 1 is given to the J1 pulse generating unit 2.

The J1 pulse generation unit 2 includes a pointer value reception unit 1
A pulse signal (hereinafter referred to as a J1 pulse) is generated at a timing corresponding to the position of the J1 byte according to the pointer value received from the memory unit 3 and given to the memory unit 3.

The memory unit 3 is supplied with the J1 pulse given from the J1 pulse generating unit 2, the received data inputted from the outside, the received clock, and the transmitted clock, and between the both clocks. The staff control unit 4 controls the staff for synchronizing the above. Memory part 3
Functions as a buffer memory, temporarily buffers the received data input in synchronization with the reception clock, and outputs the transmission data in synchronization with the transmission clock by outputting the data according to the stuff control by the stuff control unit 4.

At this time, each pointer value in the frame of the transmission data is calculated by the pointer value calculation unit 5, and this pointer value is calculated by the pointer insertion unit 6 in H1 of each frame.
It is inserted in the lower 10 bits of the H2 byte. Specifically, the pointer value calculation unit 5 determines the pointer value depending on which of the addresses up to the address "782" coincides with the timing of the J1 pulse with the byte next to the H3 byte of the SPE address as the address "0". decide.

On the other hand, the pointer insertion unit 6 has an NDF generation circuit.
NDF is given from 20 and inserted into the upper 4 bits of the H1 byte of each frame when the above pointer value is inserted.

Although the details of the configuration of the NDF generation circuit 20 are omitted, it is usually a Normal NDF having a value of "0110".
As described above, for example, when the power is turned on, when a line error occurs (alarm occurs, input clock is cut off, etc.), and when recovery is performed after a memory slip occurs, or when staff control is performed. If there is a change in the send pointer value except for the change in the pointer value of
An NDF ENABLE having a value of 1001 ”is generated, inserted into a frame of transmission data and transmitted.

Therefore, the NDF generation circuit 20 uses Norm as NDF.
al It consists of various circuits to monitor whether NDF should be transmitted or NDF ENABLE should be transmitted, and monitoring by all of these circuits is required every time pointer processing is performed. Therefore, the circuit scale is increased and the complexity is increased.

[0021]

As described above, the conventional
The NDF generation circuit has the problems of increased circuit scale and complexity.

The present invention has been made in view of the above circumstances, and is an NDF capable of avoiding an increase in circuit scale and complication.
The purpose is to provide a generation circuit.

[0023]

FIG. 5 shows a block diagram of a principle configuration example of a pointer processing circuit of a digital transmission system and an NDF generating circuit of the present invention. In addition, in FIG.
Reference numerals 1, 2, 3, 4, 5, 6 indicate the same parts as those in the conventional example described above.

In the present invention, it is designated by the reference numeral 20.
The NDF generation circuit is characterized by being configured as follows. The NDF generation circuit 20 of the present invention mainly comprises a previous frame pointer value latch unit 7, a pointer value comparison unit 8 and the like.

A pulse signal (hereinafter referred to as J1 pulse) indicating the timing of the J1 byte of each frame is output from the memory unit 3 similar to the conventional one, and the pointer value calculation unit 5 and J1−.
It is given to the calculation unit 7 between J1s. The pointer value calculation unit 5 calculates the pointer value as in the conventional example, and supplies the value to the previous frame pointer value latch unit 7, the pointer value comparison unit 8 and the pointer insertion unit 6.

The previous frame pointer value latch unit 7 latches the pointer value given from the pointer value calculation unit 5 until the timing of the next frame, thereby latching it as the pointer value of the previous frame. The pointer value of the previous frame latched by the previous frame pointer value latch unit 7 is given to the pointer value comparison unit 8.

The pointer value comparison unit 8 is a pointer value calculation unit 5
And compares the pointer value of the current frame given from the current frame with the pointer value of the previous frame latched by the previous frame pointer value latch unit 7. Then, this pointer value comparison unit 8
Specifically, depending on the result of comparison, the Normal NDF is output from the pointer value comparison unit 8 to the pointer insertion unit 6 if the comparison results match, and NDF ENABLE if the comparison results do not match.

The pointer insertion unit 6 is a pointer value calculation unit 5
The NDF (Normal NDF or NDF ENABLE) given by the pointer value given by the above and the pointer value comparison unit 8 is inserted into the H1 and H2 bytes of each frame of the transmission data and transmitted.

[0029]

Therefore, in the NDF generation circuit of the present invention, basically, the pointer value of the previous frame latched in the previous frame pointer value latch unit 7 and the pointer value of the current frame output from the pointer value calculation unit 5 are Are compared by the pointer value comparison unit 8, and if they match, the normal NDF is considered to be transmitted and Normal NDF is transmitted. If they do not match, the NDF ENABLE is considered as not normal. Send.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments thereof.

FIG. 6 shows a circuit diagram of a specific configuration example of the pointer processing circuit of the digital transmission system and the NDF generating circuit of the present invention. In the example shown in FIG. 6, the previous frame pointer value latch unit 7 and the pointer value comparison unit 8 are not distinguished from each other, and are shown as the previous frame pointer value latch unit and the pointer value comparison unit 78. .

The pointer value calculator 5 is specifically composed of an up counter 51, a flip-flop 52 and a flip-flop 53.

The up-counter 51 counts the count value from "0" to "783", the 10-bit data input terminals (D0 to D9) are always "0", and the load input terminal is H3 indicating the position of H3 byte. A pulse is input to the transmitter clock at the clock terminal, and TOH is input to the enable terminal.
A signal is being input. This TOH signal is an enable signal for not counting each byte in the overhead part of each frame.

Therefore, when the H3 pulse is input, the up counter 51 starts the up counting of the transmission side clock with "0" as the initial value. That is, the count value of the up counter 51 indicates the address of the SPE byte. The output signal of the up counter 51, that is, the SPE byte address output from the 10-bit output terminals Q0 to Q9 is the flip-flop 52.
Given to.

On the other hand, in the flip-flop 53, the J1 pulse is input to the data input terminal and the transmission side clock is input to the clock terminal. Therefore, the flip-flop 53
Latches the J1 pulse in synchronization with the transmitter clock.
The J1 pulse latched by the flip-flop 53 is given to the clock terminal of the flip-flop 52.

Specifically, ten flip-flops 52 are provided. Each bit of the output signal of the up counter 51 is input to each input terminal of the ten flip-flops 52, and the J1 pulse latched by the above-mentioned flip-flop 53 is input to each clock terminal. Therefore, the flip-flop 52 is synchronized with the J1 pulse and the up counter 51
Holds the count value of. In other words, the SPE address counted by the up counter 51 becomes the pointer value at the timing when the J1 pulse is given to the flip-flop 52. The 10-bit pointer value latched by the flip-flop 52 is given to the flip-flop 50, the previous frame pointer value latch section and the pointer value comparison section 78.

The previous frame pointer value latch unit and pointer value comparison unit 78 are specifically composed of an EXOR gate 71, a flip-flop 72, an AND gate 73 and the like.

Specifically, ten EXOR gates 71 are provided. For each of these 10 EXOR gates 71,
The output signal of each of the flip-flops 52 will be described later.
The output signal of each of the 10 flip-flops 72 is input. Then, the output signals of these 10 EXOR gates 71 are input to the 10 flip-flops 72, respectively.

Specifically, ten flip-flops 72 are provided. The output signals of the ten EXOR gates 71 described above are input to the input terminals of these ten flip-flops 72, and the H1 pulse is input to the clock terminal. And the output signals of the 10 flip-flops 72 are
Input to AND gate 73. The H1 pulse is used to indicate the timing to determine the NDF and pointer value to be sent.

Therefore, the flip-flop 72 EXOR-gates the value held by the flip-flop 52 of the pointer value calculation unit 5 and the value held by itself in synchronization with the H1 pulse.
It is input via 71, held, and output to AND gate 73. As a result, if the pointer value of the previous frame and the pointer value of the current frame match, "0" is held in each of the ten flip-flops 72. In this case, the output signal of the AND gate 73 is held. Becomes "0". on the other hand,
If the pointer value of the previous frame and the pointer value of the current frame do not match, "1" is held in any of the 10 flip-flops 72. In this case, the AND gate 73
Output signal becomes "1".

The output signal of the AND gate 73 is branched into 4 and given to the pointer inserting section 6 as bits 1 to 4 of NDF, of which 2 bits of bits 2 and 3 are inverted by the inverters 74 and 75. Has been done. Therefore, when the pointer value of the previous frame and the pointer value of the current frame match, the output signal of the AND gate 73 becomes "0", so that bits 1 to 4 of NDF have a value of "0110". Normal
When the pointer value of the previous frame and the pointer value of the current frame do not match the NDF, the output signal of the AND gate 73 becomes "1", so that bits 1 to 4 of the NDF have a value of "1001". Each becomes NDF ENABLE.

The flip-flop 50 is provided for latching the pointer value of the current frame output from the flip-flop 52 of the pointer value calculator 5 at the timing of H1 pulse and giving it to the pointer inserter 6.

The operation of the NDF generating circuit of the present invention will be described below together with the operation of the pointer processing circuit.

A signal is output from the memory unit 3 similar to the conventional one at the timing of the J1 byte of each frame and given to the pointer value calculation unit 5. The pointer value calculation unit 5 calculates the pointer value as in the conventional example, and supplies the value to the previous frame pointer value latch unit 7, the pointer value comparison unit 8 and the pointer insertion unit 6.

The previous frame pointer value latch unit and the pointer value comparison unit 78 latches the pointer value given from the pointer value calculation unit 5 until the timing of the next frame, thereby latching it as the pointer value of the previous frame,
Compare both pointer values.

If the comparison results match, AND gate
Since the output signal of 73 becomes "0", it is "011" as NDF.
A Normal NDF having a value of 0 "is output to the pointer insertion unit 6, and if they do not match, the output signal of the AND gate 73 is" 1 ".
Therefore, NDF EN has a value of “1001”.
ABLE is output to the pointer insertion unit 6.

On the other hand, the flip-flop 50 latches the pointer value of the current frame in synchronization with the H1 pulse and outputs the latched value to the pointer inserting section 6. Therefore, in the pointer inserting section 6, the value of NDF given from the AND gate 73 and the flip-flop. Insert the H1 and H2 bytes with the pointer value given by 50 and send.

During normal operation, the pointer value of the current frame is the same as the pointer value of the previous frame, so that the previous frame pointer value latch section and the pointer value comparison section 78 detect the coincidence of both pointer values. Therefore, Normal NDF
Is output.

In the case of a long-time line error, recovery from a memory slip, and when the power is turned on, the pointer value of the previous frame and the pointer value of the current frame are different from each other. The value comparison unit 78 detects a mismatch between the pointer values. Therefore,
NDF ENABLE is output. In this case, the changed pointer value is also output.

[0050]

As described in detail above, according to the present invention,
By comparing the pointer value of the previous frame with the pointer value of the current frame without the need to monitor multiple conditions for NDF generation and transmission in the conventional method, NDF generation and NDF can be sent without monitoring the sending conditions. Therefore, even if the conditions for NDF generation and transmission increase, the circuit scale does not expand.Since it is only necessary to monitor and control two states, the circuit scale can be reduced, the development man-hours can be reduced, and the power consumption can be reduced. Reduction is realized.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a configuration of an STS frame format of SONET as a digital transmission system.

FIG. 2 is a schematic diagram showing a configuration of H1 and H2 bytes of a SONET STS frame format.

FIG. 3 is a schematic diagram of a SONET frame format to which an SPE address is added.

FIG. 4 is a block diagram showing a configuration example of a pointer processing circuit and an NDF generation circuit of a conventional digital transmission system.

FIG. 5 is a block diagram of a principle configuration example of a pointer processing circuit of a digital transmission system and an NDF generation circuit of the present invention.

FIG. 6 is a circuit diagram showing a specific configuration example of a pointer processing circuit of a digital transmission system and an NDF generating circuit of the present invention.

[Explanation of symbols]

7 Previous Frame Pointer Value Latch Unit 8 Pointer Value Comparison Unit 78 Previous Frame Pointer Value Latch Unit and Pointer Value Comparison Unit

Claims (1)

[Claims] 1. A byte (J1) at a byte position indicated by a pointer included in a specific byte (H1, H2) of a header portion of each frame, which constitutes one frame with a predetermined amount of data.
Of a digital transmission system that inputs a signal in which a specific data group arranged at a predetermined interval with the head as an input exists and generates information (NDF) indicating whether the pointer has changed in the frame of the input signal In the NDF generation circuit in the pointer processing circuit, a previous frame pointer value latch unit (7) for holding the pointer of the previous frame of the input signal, a pointer of the current frame of the input signal and the previous frame pointer value latch unit ( The pointer of the previous frame held in 7) is compared, and if the comparison result does not match, the signal indicating that the pointer value has changed (NDF ENABLE) is output. A pointer for a digital transmission system, characterized in that it has a pointer value comparison unit (8) for outputting a signal (Normal NDF) indicating that there is no change. NDF generation circuit in data processing.