JPH05292076A - Pointer control circuit for digital communication - Google Patents

Abstract

PURPOSE:To realize a pointer control circuit for digital communication sending new data flags (NDF) in the shortest time when a pointer value is changed at a reception station being controlled by the pointer. CONSTITUTION:In a pointer control circuit 100 provided with a counter 10, a latch circuit 20, a pointer value comparison circuit 30, and a new data flag insertion circuit 40, is provided with an OR circuit 50 ORing the output of a signal detecting three successive pointer values and the output of the pointer value comparison circuit 30. When a new data flag NDF indicating the change of pointer values and three successive pointer values are detected by the output of the OR circuit 50, the new data flag NDF are immediately transmitted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pointer control circuit for digital communication. With the progress of digital communication in recent years, digital synchronous networks have expanded, and the number of data transmission devices that perform pointer control has increased. In such a data transmission device, when data is transmitted / received between two stations having different timings, the pointer indicating the head position of the data is controlled to transmit / receive the data at correct timing.

FIG. 4 is a diagram for explaining pointer replacement. When there are stations A and B that perform digital communication and the data of station B is transferred to the timing of station A, the separation circuit 1 extracts the pointer in the timing data of station B by the pointer reception circuit 2, Start position of data (V in the figure
(Denoted as 5 TIM) is detected and the received data is written in the memory circuit 3.

On the other hand, the data written in the memory circuit 3 is
By reading at the timing of the station, the timing of the station A is changed. At this time, the head position of the data is detected, the pointer sending circuit 4 sends the pointer value, and the multiplexing circuit 5 writes the pointer value in the data and sends it.

The number 8 in which a thick line is shaded in the drawing indicates that it is 8-bit parallel data. FIG. 5 is a diagram for explaining the structure of the pointer. The figure shows the Synchronous Optical Network used mainly in North America.
It is an example of the pointer in the VT group in k).

The first 1 byte of each VT group is a pointer area. The contents will be described below. -NEW DATA FLAG Normal case NDF = "0110" When a new pointer is sent NDF = "1001" However, NDF = "0110" is valid when all 4 bits match, and NDF = "1001" is at least
Valid if 3 bits match.

VT = SIZE Here, VT is 1.5, and VT = “11” is fixed. -Number of bytes from 10 BIT POINTER V2 to V5.

I (Increment Bit) POS. STUF
Bit to use when doing F. When a 10-bit pointer in which only the I-bit of the 10-bit pointer one frame before is inverted is received, POS. S
Judge as TUFF.

However, it is valid if 3 bits or more of 5 bits are inverted.・ D (Decrement Bit) NEG. Bit used when performing STUFF. When a 10-bit pointer in which only the D-bit of the 10-bit pointer one frame before is inverted is received, NEG. S
Judge as TUFF.

However, it is valid if 3 bits or more of 5 bits are inverted. FIG. 6 is a pointer transfer time chart. In the figure, as the pointer value of station B, the number of bytes from V2 to V5 which is the head of SPE (Synchronous Payload Envelope) data is written in the 10-bit pointer.

When the timing data of station B is changed to the timing of station A, the position of V5 at the beginning of the SPE data does not change, but the timing is different, so the number of bytes from V2 to V5 is Naturally it will be different. Therefore, the number of bytes from V2 to V5 at the time of changing to the timing of station A is written in the pointers of V1 and V2, and NDF indicating that the pointer value has changed is set and the data is transmitted.

[0011]

2. Description of the Related Art FIG. 7 is a diagram for explaining a conventional example.
(A) shows a conventional pointer control circuit. 10 in the figure
Is a counter, 20 is a latch circuit, 30 is a pointer value comparison circuit, and 40 is an NDF insertion circuit.

In the circuit shown in the figure, the counter 10 counts the timing from V2 to V5 in the input data,
The count value is input to the latch circuit 20 and latched for one frame.

Next, when the data of the current frame is input, similarly, the counter 10 counts the timing from V2 to V5 in the input data, and compares the count value of the current frame with the count value of the previous frame by pointer comparison. The circuit 30 compares them, and if they are different, NDF is sent out.

(B) shows a time chart of a conventional example.
In the figure, the timing from V2 to V5 is counted, the count value of the previous frame and the count value of the current frame are compared, and if they are different, NDF is inserted and transmitted.

[0015]

As described above, for example, the pointer value is monitored at the data transmission station (hereinafter referred to as station B), the change in the pointer value is detected, and the ND is detected.
Although F is sent, the NDF is received, and the pointer value of the receiving station (hereinafter referred to as A station) of the data controlled by the new pointer value does not change immediately.

FIG. 8 shows a time chart of a conventional example.
(A) is a time chart of insertion of a new pointer value by three consecutive receptions of NDF and new pointer value. Even if NDF or new pointer value is continuously received three times and changed to a new pointer value, station A Since the NDF is output only by the pointer value comparison error, it takes 2 frames or more until the NDF is output, and the data in the meantime may be in error.

As in (A), (B) takes time to send NDF when the power is turned on or after the alarm is released (“L” level in the figure is in a normal state), and the data during that time is It may cause an error.

According to the present invention, when the pointer value changes, the receiving station controlled by the pointer value performs NDF in the shortest time.
We will try to realize a pointer control circuit for digital communication that can send out.

[0019]

FIG. 1 is a block diagram for explaining the principle of the present invention. In the figure, 100 is a pointer control circuit, 10 is a counter for counting the timing from the reference pointer insertion position to the data head position, and 20 is a counter for holding the count value counted by the counter 10 for one frame. A latch circuit 30 is a counter 10 that counts the timing from the reference pointer insertion position of the current frame to the data start position.
Is a pointer value comparison circuit for comparing the output of the latch circuit 20 holding the count value of the previous frame, and 40 indicates that the pointer value has changed when the pointer value comparison circuit 30 does not match. Is a new data flag insertion circuit (shown as an NDF insertion circuit in the figure) for inserting a signal new data flag NDF indicating

Reference numeral 50 detects that the signal new data flag NDF, which is provided in the pointer control circuit 100 and indicates that the pointer value sent from the data transmission station has changed, and the same pointer value are repeated three times. It is a logical sum circuit that takes the logical sum of the signal and the output of the pointer value comparison circuit 30, and from the output of the logical sum circuit 50, the signal new data flag NDF indicating that the pointer value has changed and the same pointer value are consecutive three times. When it is detected, the new data flag NDF is immediately transmitted.

[0021]

When performing digital communication between two stations at different timings, the pointer indicating the data insertion position is controlled to transmit / receive data.

When the NDF or new pointer value is received three times in succession on the data transmitting station side, the detection signal is passed to the data receiving station side, and the signal and the reference pointer position to the beginning of the data are transmitted. The logical sum circuit 50 takes the logical sum of the output value of the pointer value comparison circuit 30 that compares the count value of the current frame of the counter 10 that counts the timing with the count value of the previous frame.

The output of the OR circuit 50 causes the NDF
By controlling the insertion circuit 40, the receiving station can change the pointer value in the shortest time.

[0024]

FIG. 2 is a time chart of the present invention. The operation of the present invention will be described with reference to a time chart.

Indicates the timing of station B, with -1 indicating N
The DF is received and the new pointer value is changed from -2. NDF at timing of station B, continuous new pointer value 3
It is a received signal.

It is a signal obtained by changing the signal of (1) to the timing of station A. The station A immediately recognizes that the pointer value is changed by the signal No. 2, so that the NDF is inserted at the timing of -1 and the new pointer value detected by the counter 10 is inserted at -2 of the same frame.

By the above operation, when the station B receives the NDF and new pointer value three times in succession, the signal is transmitted to the station A so that the NDF can be immediately transmitted and the pointer value can be immediately changed. Can minimize the data error input.

FIG. 3 is a diagram for explaining an embodiment of the present invention. (A) is a diagram in which a differential circuit for a power-on signal and an alarm recovery signal is added to the principle diagram of FIG. 1, and the logical sum circuit 50 is a three-input logical sum circuit 51.

(B) is a time chart, the operation of which will be described. The timing of station B is shown. It is a power-on signal and an alarm recovery signal generated at -1 of station B.

This signal is generated by differentiating the signal of A at the timing of station A. The station A knows that the pointer value is changed by the signal No. 2, so that the NDF is inserted at the timing of -1 and the new pointer value detected by the counter 10 is inserted at -2 of the same frame.

By the above operation, when the station B receives the NDF and new pointer value three times in succession, the signal is transmitted to the station A, so that the NDF can be immediately sent out and the data error is suppressed to the minimum. be able to.

[0032]

According to the present invention, there are two different timings.
When it is detected that the signal new data flag NDF indicating that the pointer value has changed and the same pointer value has continued three times on the data transmitting station side when the pointer is controlled between the stations and the data is transmitted and received. A pointer pointer control circuit for digital communication that can minimize the data error by immediately transmitting the signal to the data receiving station and immediately changing to the new pointer value on the data receiving station side. Can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a time chart of the invention.

FIG. 3 is a diagram illustrating an embodiment of the present invention.

FIG. 4 is a diagram for explaining pointer replacement.

FIG. 5 is a diagram illustrating the configuration of a pointer.

FIG. 6 Pointer transfer time chart

FIG. 7 is a diagram illustrating a conventional example.

FIG. 8 is a time chart of a conventional example.

[Explanation of symbols]

 10 counter 20 latch circuit 30 pointer value comparison circuit 40 NDF insertion circuit 50, 51 OR circuit 60 differentiation circuit 100 pointer control circuit 1 separation circuit 2 pointer reception circuit 3 memory circuit 4 pointer transmission circuit 5 multiplex circuit

Claims (2)

[Claims] 1. A pointer control circuit for digital communication between two stations at different timings, comprising a counter (10) for counting the timing from a reference pointer insertion position to a data head position, and the counter. A latch circuit (20) for holding the count value counted in (10) for one frame, and an output of the counter (10) which counts the timing from the reference pointer insertion position of the current frame to the data start position. , If the pointer value comparison circuit (30) for comparing the output of the latch circuit (20) holding the count value of the previous frame and the pointer value comparison circuit (30) do not match,
In the pointer control circuit (100) including the new data flag insertion circuit (40) that inserts a signal new data flag (NDF) indicating that the pointer value has changed, the pointer value sent from the data transmission station has changed. A signal new data flag (NDF) indicating that the same pointer value is detected three times consecutively, and an OR circuit (50) for ORing the output of the pointer value comparison circuit (30), When it is detected from the output of the OR circuit (50) that the signal new data flag (NDF) indicating that the pointer value has changed and the same pointer value are consecutive three times,
A pointer control circuit for digital communication, which immediately sends out a new data flag (NDF). 2. A pointer control circuit (100) according to the preceding claim.
The differential circuit (60) for differentiating the signal (ALM) indicating that the fault condition has been recovered is provided in the, and the signal (ALM) indicating that the fault condition has been recovered is detected by the output of the differentiating circuit (60). In this case, immediately by the new data flag insertion circuit (40),
A pointer control circuit for digital communication characterized by transmitting a new data flag (NDF).