KR100228475B1 - Frame data receiver - Google Patents

Abstract

[Technical field to which the invention described in the claims belongs]

A frame data receiving apparatus for receiving data of a frame transmitted without bit insertion by a simple configuration.

[Technical Challenges to Invent]

Provided is a data receiving apparatus capable of receiving data of a frame included in the form of a synchronization field, a size field, an information field, and a CRC field.

[Summary of the solution of the invention]

The synchronization data and the size data included in the received data are detected. The frame counter is used to count the size data, the data field, and the section of the CRC field to generate a data receive enable signal and a byte clock for receiving data, and receive data by the detected size using the frame counter.

[Important Uses of the Invention]

Device for receiving frame data over a data link.

Description

Frame data receiver

1 is a format configuration diagram of a data transmission frame according to the prior art.

2 is a format configuration diagram of a new data transmission frame for improving the problem of the data transmission frame of FIG.

3 is a block diagram of a data receiving apparatus according to an embodiment of the present invention.

4 is an operational waveform diagram of the data receiving apparatus shown in FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for receiving data in units of frames transmitted in a certain format, and more particularly, to a frame data receiving apparatus for receiving data of a frame transmitted without bit insertion by a simple configuration.

Typically, transceivers having a path for transmitting and receiving data, i.e., data links, use some form of protocol to transmit and receive large amounts of data at high speed. For example, the High Data Link Control Procedure (HDLC) of the Bit Oriented Protocol. The HDLC method transmits and receives data in units of frames. Here, a frame is a protocol unit of a data link layer as a basic transmission unit between stations for transmitting and receiving data, and the structure of such a frame is known.

1 is a format configuration diagram of a conventional data transmission frame and a structure of a frame by the HDLC protocol. The frame shown in FIG. 1 includes a start flag, an address field, a control field, an information field, a cyclic redundancy code (CRC) field, an end flag, and the like. Here, each of the start flag and the end flags are data indicating the start and end of the frame transmission, and have a value of “1111110”. The start flag having the above configuration is transmitted for synchronization purpose, and then address information, control information, data information and CRC information are continuously transmitted in the data. Conventional transmission apparatuses using conventional transmission frames having the above frame format have six consecutive "1" s in the same format as the flag of data between the start flag and the end flag (for example, "1111110", etc.). Must have a function that prevents it from In other words, when five bits of "1" of data to be transmitted are consecutive, the transmitting side inserts one "0" into the fifth next bit and transmits the data. When five are received, an operation to remove the next bit "0" must be performed. This is commonly referred to as transparency.

Therefore, in the conventional transmission apparatus using the transmission frame format as shown in FIG. 1, a separate circuit such as a bit inserter or the like must be added. In addition, the receiver for receiving data transmitted in the form of a frame as shown in FIG. 1 should have a bit extraction function for extracting data inserted into a logic "0" and converting the data inserted into a logic "0" to distinguish it from the flag data. . The HDLC protocol controller is manufactured and sold in the form of a one-chip, for example, "MT8952B" sold by Canadian semiconductor maker "MITEL".

The commercially available HDLC protocol controller includes a transmission buffer and a reception buffer, and formats and transmits data stored in the transmission buffer in the structure of the HDLC frame as shown in FIG. However, the commercialized HDLC protocol controller has a complicated configuration by having a bit inserter for transmission and a bit extractor for reception, and the size of the transmission buffer for data transmission and the size of the reception buffer for receiving data is about 20 bytes. When there is a lot of data to be transmitted at a time, it is difficult to use. In addition, there is a problem that the system performance is deteriorated because the system is not scalable.

Therefore, in order to improve the problem of the above-described format of the frame, a data frame format has been developed that does not require the insertion of a frag bit for inserting bits when the same data is continuous.

2 is a format configuration diagram of a newly proposed data transmission frame to improve the problem of the data transmission frame of FIG. 1, which transmits the size information of the data to be transmitted and receives the size information at the receiving side to receive the data correctly. I would have to.

The data transmission frame shown in FIG. 1 is a 2-byte sync field for synchronizing transmission and reception of data frames, a 2-byte size field indicating size information of information data transmitted on one frame, and a 64-byte size. It consists of an information field capable of transmitting data of " CRC "

In order to transmit data in a frame structure as shown in FIG. 2, the transmitter needs a synchronization register and a size information register having a storage capacity of at least 2 bytes, and a transmission buffer having a storage capacity of 64 bytes. You must have a format controller to control this. When data is transmitted in the above-described format, the transmission and reception of data are started by transmitting a synchronization signal so as to have a synchronization signal system of a predetermined type between the transmitting side and the receiving side without using the start flag and the end flag as in the prior art. . In addition, the size information of the data to be transmitted in the information field is first transmitted to the size information field so that the receiving side can correctly receive the predetermined data information. Here, the information of the upper byte and the lower byte in the size field of 2 bytes is the same information.

Data transmitted in the frame format as shown in FIG. 2 cannot be received by a data receiving apparatus having a conventional bit-orient protocol scheme. This is because the format of the frame is different and the protocol cannot be transmitted to the sender. Therefore, in order to receive data transmitted in the format of a frame as shown in FIG. 2, a function for detecting a synchronization signal, a circuit capable of detecting a size signal, and a data reception control function for receiving received data by the size are required. .

SUMMARY OF THE INVENTION An object of the present invention is to provide a frame data receiving apparatus capable of receiving frame data carrying a synchronization signal contracted between a transmitting and receiving side.

Another object of the present invention is to provide a data receiving apparatus capable of receiving data of a frame formatted in the form of a sync field, a size field, an information field, and a CRC field.

Another object of the present invention is to provide a receiving apparatus capable of receiving data transmitted without having a bit extraction function.

According to an aspect of the present invention, there is provided an apparatus for receiving frame data formatted in the form of a synchronization field, a size field, an information field, and a CRC field, wherein serial data received from a transmission is received by parallel data input by a reception clock. Data converting means for converting the data into two data sources; receiving data storing means for storing received data by input of address information and a recording control signal; and comparing the two pieces of data by comparing the synchronization data output from the data converting means with preset reference synchronization data. Receiving frame detecting means for generating a frame synchronizing signal when the synchronizing data of the same is the same, size data detecting means for detecting the size data by comparing the signals of the lower byte and the upper byte with the data output from the data converting means; In response to an input to a frame sync signal, Frame counting means for counting the reception clock to detect the end section of the preset size field, the start section of the data field, and the byte section in the data field section, and output a data enable signal, byte clock, and the section count value of the data field; Receiving data detection means for generating a reception end signal when the detected size data and the counted interval count value are the same, and incrementing and counting address information set in the byte clock in response to the size data detection information. And recording position control means for outputting an address signal and a recording control signal of the reception data storage means, and storing the generated recording address as a setting address in response to the reception termination signal.

Hereinafter, with reference to the timing diagram of Figures 3 and 4 attached to the operation of the preferred embodiment according to the present invention will be described in detail.

3 is a block diagram of a frame data receiving apparatus according to an embodiment of the present invention, which converts serial data received through a transmission path into parallel data and analyzes each piece of information of a frame to obtain a synchronization signal as reception control information of the frame. It shows the configuration to generate and extract only the data of the frame in the receiving buffer 22.

4 is an operational waveform diagram of the data receiving apparatus shown in FIG.

An operation of FIG. 3 will be described in detail with reference to the operation timing diagram of FIG. 4.

Now, when the data Sin of a frame formatted as shown in FIG. 2 and converted into serial data is transmitted from the transmitter to B of FIG. 4, it is converted to the serial-to-parallel converter shown in FIG. 3 (hereinafter referred to as "PSC"). It is supplied to the data input terminal DI of 12 and the data input terminal DI of CRC searcher 20. Each of the PSC 12 and the CRC searchers 20 inputs the reception clock RCLK as shown in FIG.

The PSC 12 corresponding to the data converting means converts the data inputted in series as shown in FIG. 4 (b) in parallel by the input of the reception clock RCLK as shown in FIG. 4 (a), and synchronizes the comparator 16 with the size comparator 18 and the size. The data input terminal of the register 28 and the data input terminal of the receiving buffer 22 are output respectively. At this time, the number of bits of parallel data output from the PSC 12 is 16 bits in total, and the synchronous comparator 16 inputs 16 bits of received data to the terminal A. The size comparator 18 inputs the upper byte HB to the terminal B of the 16-bit data, the lower byte LB to the terminal A, and the receiving butter 22 inputs data in byte units. Note that the data of the upper byte input to the size register 28 and the reception buffer 22 is the data input later.

The terminal B of the synchronous comparator 16 is supplied with synchronous data output from the synchronous register 14. The synchronous register 14 stores two bytes of synchronous data previously agreed with the transmitter, which can be set programmatically, and is set equal to a value stored in the synchronous register at the transmitter for transmitting and receiving data. Therefore, when the initial 16-bit data is output from the PSC 12, the result signal for the comparison between the received synchronization data and the preset synchronization data is output from the synchronization comparator 16. That is, when the synchronization data of the received frame and the preset synchronization data are the same, the frame synchronization signal Sync having the meaning of receiving the data of the received frame is generated "high" as shown in FIG. 4 (c).

When the frame synchronization signal Sync shown in FIG. 4 (c) is output from the synchronization comparator 16, the frame reception counter 24 counts the reception clock shown in FIG. 4 (a) in response to the input of the frame synchronization signal Sync. At this time, the operation of the frame counter 24 counts the reception clock RCL K to distinguish each field section of the frame.

For example, the frame counter 24 outputs the size field end section detection signal 4THCLK as shown in FIG. 4 (g) when the received clock RCLK is counted by the input of the frame synchronization signal Sync of " high " At the same time, the data enable signal DRXS shown in FIG. 4 (e) is outputted. The frame counter 24 which outputs the data enable signal DRXS as shown in FIG. 4 (e) outputs the byte clock BYTECLK as shown in FIG. The coefficient value is supplied to the input terminal A of the received data comparator 32. Accordingly, it can be seen that the frame counter 24 detects the end section and the data field section of the size field of the format shown in FIG. 4 (b), and detects the byte unit in the data field section and generates the corresponding signal.

On the other hand, the size comparator 18 for inputting the data of the lower byte LB and the upper byte HB output from the PSC 12 to the terminals A and B, respectively, has the second size and the data of the first size field in the data section as shown in FIG. 4 (b). When the values of the field data are compared and the values are the same, the size detection signal SIZEEN indicating that the size of the received frame is detected is output as shown in FIG. 4 (d). At this time, the value of the data of the first size field and the data of the second size field among the data formats input as shown in FIG. 4 (b) is the same value, and the reason for detecting this is to store the size data value in the size register 28 to be described later. For sake.

The size detection signal SIZ EEN output from the size comparator 18 as shown in FIG. 4 (d) is supplied to one terminal of the NAND gate 26. At this time, the other input terminal of the NAND gate 26 is connected to the output terminal of the size field end section detection signal 4THCLK of the frame counter 24 described above. Accordingly, the NAND gate 26 negatively multiplies the two signals to generate a reception loading control signal / LDRXP as shown in FIG. 4 (h).

The reception loading control signal / LDRXP as shown in FIG. 4 (h) is supplied to the clock terminal of the size register 28 and the load terminal / LD of the cross-point pointer 38. Accordingly, the size register 28 latches 8 bits of size data currently output from the PSC 12 in response to the rising edge of the reception loading control signal / LDRXP and supplies them to the input terminal B of the reception data comparator 32. The recording pointer 38 then loads the address value output from the temporary register 36 into the internal register area. The write pointer 38 includes a combination of a counter capable of loading data and logic circuits for generating a write enable signal / WE in response to an input of a clock. Therefore, when the information of the initial size field is detected, it can be seen that the recording pointer 38 loads the address value output from the temporary register 36 into an internal register.

At this time, the initial value stored in the temporary register 36 is "0", and this value may vary according to the value of the recording pointer 38. The operation of changing the value of the temporary register 36 will be apparent by the operation description below, but when the information of one frame is correctly received, the output value of the recording pointer 38 is stored.

In the above state, if the frame counter 24 counts 8 bits in the data field section and generates a byte clock BYTECLK as shown in FIG. It increments and supplies it to the address signal of the receiving buffer 22 and outputs the write control signal / WE. Accordingly, the reception buffer 22 stores data of bytes output from the PSC 12 and input to the data terminal in the area of the address output from the recording pointer 38. This data storage operation is executed each time the byte clock BYTECLK is output from the frame counter 24.

In the above operation, the received data comparator 32 compares the counting value of the sum of the sum of the size data output from the size register 28 and the data field output from the frame counter 24 and the CRC field. As a result of the comparison, when the two values are the same, the received data end detection signal / RXDONE indicating that the reception is completed is output from the received data comparator 32 as shown in FIG. 4 (i). The received data end detection signal / RXDONE output from the received data comparator 32 is provided to one input of the end gate 34.

On the other hand, the CRC searcher 20 inputs and checks the serial data of the data field and the CRC field outputted from the PSC 12 by inputting the data enable signal DRXS outputted from the frame counter 24 as shown in FIG. 4 (e). Generate a signal. The CRC signal output from the CRC searcher 20 is supplied to a CRC comparator 30. At this time, the CRC of the received data field is equal to G (x) = X ¹⁶ + X ¹² + X ⁵ + 1 as in the transmission. The CRC comparator 30 compares the CRC signal output from the CRC searcher 20 with the CRC value F0B8 (hexadecimal) previously set as a reference value and searches for the same value. If the search result is the same value, the CRC comparator 30 outputs a high signal as shown in FIG. 4 (j). If the two values are different, the CRC comparator 30 outputs a low signal to indicate a data reception error. Signal is output.

If there is no error in the received data, the AND gate 34 outputs the address increase signal AI as shown in FIG. 4 (k) to the temporary register 36. Therefore, when no error occurs, the temporary register 36 stores the final output of the recording pointer 38 in the internal register 36 by the address increase signal AI output from the AND gate 34. By this operation, when data of a new frame is received later, the loadable write pointer 38 generates an address incremented from the address value stored in the temporary register 36.

However, if an error occurs in the received data, the CRC searcher 20 generates a CRC signal indicating that an error has occurred. At this time, the CRC signal generated from the CRC searcher 20 is different from the reference CRC signal set in the CRC comparator 30. Therefore, a signal of "low" is output from the CRC comparator 30. Thus, even if the received data comparator 32 outputs the received data end detection signal / RXDONE as shown in FIG. 4 (i), the output of the AND gate 34 remains unchanged. Low "state. The value of the AND gate 34 continues to output a "low" value so that the address value stored in the temporary register 36 retains the previously stored value. In other words, the temporary register 36 cannot store the address supplied from the recording pointer 38 to the receiving buffer 22. Therefore, in order to ignore all the information of the received frame, it is returned to the recording pointer before reception.

As described above, the present invention can transmit and receive a large amount of data by receiving data of a frame having a format capable of easily adjusting the size of data to be transmitted by a simple configuration, and the bit inserter has a function such as bit deletion. There is an advantage that you can simply send and receive data without the need.

Claims (5)

An apparatus for receiving frame data formatted in the form of a synchronization field, a size field, an information field, and a CRC field, comprising: data conversion means for converting serial data received from a transmission into parallel data by an input of a reception clock; Receive data storage means for storing data by input of address information and write control signal, and synchronous data output from the data conversion means and preset reference synchronous data are compared to generate a frame synchronous signal when the two synchronous data are the same. Receiving frame detecting means for comparing the signals outputted from the data converting means with a signal of a lower byte and an upper byte to detect size data, and the receiving clock counting in response to an input to the frame synchronization signal. Preset size Frame counting means for detecting an end section of the card, a start section of the data field, and a byte section in the data field section and outputting a data enable signal, a byte clock, and a section coefficient value of the data field, and the detected size data and the Reception data detection means for generating a reception termination signal when the counted interval count value is the same and the address information set in the byte clock is incremented and counted in response to the size data detection information to obtain an address signal of the reception data storage means. And recording position control means for outputting a recording control signal and storing the generated recording address as a setting address in response to the reception end signal. 2. The frame counting means according to claim 1, wherein the frame counting means counts a reception clock to a final position of a size field by inputting the frame synchronization signal, and generates a size field end section detection signal in the last section of the size field. Frame data receiving device. 3. The apparatus according to claim 2, wherein the size data detecting means comprises: size comparing means for generating a size detecting signal when the data of the lower byte and the value of the upper byte are compared with each other and the size detecting signal; Gating means for gating the size field end section detection signal to generate a data receiver enable signal, and data holding means for storing size data outputted from the data conversion means in response to the data receiver enable signal. Frame data receiving device characterized in that. 4. The frame data reception according to claim 3, further comprising CRC detection means for detecting a CRC code corresponding to the data received from the transmission path and for interrupting the output of the reception termination signal in an error state. Device. 5. The address of claim 3 or 4, wherein the recording position control means includes: a temporary register for storing the recording address in response to a reception end signal and an address output from the temporary register in response to the input of the data reception enable signal. Is stored in an internal register, and the write address is formed by counting the input of the byte clock and comprising a write pointer for generating an address of the received data storage means.