KR0176867B1 - Apparatus for synchronized data processing of cd-rom decoder - Google Patents

Abstract

The present invention relates to a synchronous data processing apparatus of a CD-ROM decoder. In the case of detecting and storing synchronous data in the related art, when the synchronous data is input, the synchronous data processing is performed. There is a problem that the memory usage time is increased because the storage must be started, and when the synchronization data is detected and stored, additional hardware for the buffer to store subsequent data input during the storage after the synchronization is detected is needed. There is a delay in the overall storage time, and there is a method of storing the sync data after the sync is detected without storing the sync data. Therefore, the present invention simplifies the hardware configuration by configuring a circuit and a multiplexer that generates synchronization data to be compared with the synchronization input at the time of synchronization detection, and improves the overall performance by storing the synchronization separately when detecting similar synchronization data. Try to eliminate time delays.

Description

Synchronous data processing device of CD-ROM decoder

1 is a block diagram of a typical CD-ROM decoder.

2 is a block diagram of a synchronization data processing apparatus of a CD-ROM decoder according to the present invention.

FIG. 3 is a detailed configuration diagram of the sync detector and sync store request unit in FIG.

4 is a diagram illustrating a configuration and input / output chart of a first synchronization generator.

5 is a diagram illustrating a configuration of a second synchronization generator and an input / output chart in FIG.

6 is an operation timing diagram of the synchronization detector in FIG.

7 is an operation timing diagram of a synchronous storage request unit in FIG.

8 is another operation timing diagram in addition to the synchronization detector in FIG.

9 is another operation timing diagram of the synchronous storage request unit in FIG.

* Explanation of symbols for main parts of the drawings

1: CD data input unit 2: Memory management unit

3: memory 4: error detection correction unit

5: interface unit 11: data conversion unit

12: memory storage requesting unit 13: synchronization detecting unit

14: Synchronous save request unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous data processing apparatus of a CD-ROM decoder for detecting and storing synchronous data in CD-ROM data, and in particular, to simplify the circuit configuration and to store and synchronize the syncs when detecting similar sync data. The present invention relates to a synchronous data processing apparatus of a CD-ROM decoder that improves performance and eliminates time delay.

Synchronous processing of a conventional CD-ROM decoder can be classified into two methods. First, a method of simultaneously detecting and storing synchronous data and a second method of detecting and storing synchronous data.

However, in the prior art as described above, in the case of the first method, when data similar to synchronous is inputted, the data is stored, and when the synchronous data detection fails, storage must be started again from the beginning. In the case of the second method, a buffer hardware is needed to store subsequent data input during storage after the synchronization is detected, resulting in a delay in the overall storage time, and synchronization data after the synchronization is detected. There is also a method of storing after the synchronization data without storing, but in this case, there is a big problem that the synchronization of the first block cannot be stored.

Accordingly, an object of the present invention is to simplify the circuit configuration when detecting and storing synchronous data at the time of data input, and to improve overall performance by eliminating SYNC in case of detecting similar synchronous data, and to eliminate time delay. A synchronization data processing apparatus of a CD-ROM decoder is provided.

As shown in FIG. 1, the block structure of a typical CD-ROM decoder converts serial data (SDATA) input from a CD digital signal processor (CD DSP) into parallel data, and then converts the data when synchronizing data is detected. A CD data input unit 1 for outputting the data, a memory management unit 2 for storing the data transmitted from the CD data input unit 1 in the memory 3, and data stored in the memory 3 by reading an error. An error detection correcting unit 4 for detecting and error correcting, and an interface unit 5 for transmitting data of the error corrected memory 3 through the error detecting correcting unit 4 to a computer. .

As shown in FIG. 2, the synchronous data processing unit in the CD data input unit 1 has 8 bits of the serial data SDATA input from the CD digital signal processor in accordance with the timing of the clocks LRACK and BCK. Or a data converter 11 for converting the data into 16-bit parallel data, a sync detector 13 for detecting sync data from the parallel data output from the data converter 11, and the sync detector 13 from the data converter 11; A synchronous storage unit 14 for outputting a write request signal WRRQ for storing parallel data output from the data conversion unit 11 into a memory according to the transferred synchronous write enable signal SWREN; When the write request signal WRRQ is input from the request unit 14, the data output from the data conversion unit 11 is transferred to the memory storage request unit 12. Configure.

When described in detail with respect to the operation and effect of the present invention configured as described above.

First, the operation of the CD-ROM decoder will be described with reference to FIG. 1. When the serial data SDATA is input to the CD data input unit 1 from the CD digital signal processor (CD DSP), the input data is converted into parallel data. In addition, the synchronization data is detected.

When the synchronization data is detected by the CD data input unit 1, the converted parallel data is stored in the memory 3 through the memory manager 2.

At this time, the error detection correction unit 4 reads the data stored in the memory 3 to perform error detection and error correction, and the interface unit 5 serves to transfer the data in the memory 3 to a computer.

Here, the operation of the synchronization data processing unit of the CD data input unit 1 will be described with reference to FIG.

When the serial data SDATA is input from the CD DSP, the data is input from the data converter 11 to convert the parallel data into 8-bit or 16-bit parallel data according to the clock (LRCK and BCK) timings. Output one data (WDATA).

In this case, 16-bit data is used.

At this time, the synchronization detector 13 detects the six-word synchronous data indicating the head of one block of data from the parallel data WDATA output from the data converter 11, that is, OOFF, FFFF, FFFF, FFFF, FFFF, and FFOO. When the synchronization data is detected, the synchronization write request signal 14 outputs the synchronization write enable signal SWREN.

Accordingly, the synchronous storage request unit 14 searches for 6-word synchronous data from the parallel data WDATA output from the data converter 11 starting with the synchronous write enable signal SWREN transmitted from the synchronous detection unit 13. The write request signal WRRQ outputted to the memory storage request unit 12 is output to the memory storage request unit 12.

Therefore, when the write request signal WRRQ transmitted from the synchronous storage request unit 14 is received, the memory storage request unit 12 transfers the data transmitted from the data conversion unit 11 to the memory manager 2 of FIG. 1. .

The configuration and operation of the sync detector 13 and the sync store request unit 14 will be described in detail with reference to FIG. 3 as follows.

As shown in FIG. 3, the detailed circuit of the synchronization detector 13 includes a first synchronization generator 13a for creating a synchronization SYNC to be compared, and data generated by the first synchronization generator 13a. The first comparator 13b for comparing the data input from the data converter 11 and the number compared with the first comparator 13b when the word clock WCLK is input from the data converter are counted and A synchronous storage request for a synchronous write enable signal SWREN generated by combining a first counter 13c for outputting a counted signal DETECT, a count signal of the first counter 13c, and a word clock of the data converter. It consists of a signal generation part 13d to convey to negative.

Referring to the operation of the synchronization detecting unit 11 having such a configuration, the data WDATA and the first synchronous generating unit 13a as shown in FIG. 6 (b) input from the data converting unit 11 are made. The first comparison unit 13b receives and compares the same data SYNCD1 as shown in (c) of FIG. 6 and outputs the result of the comparison. When the comparison result is the same as in FIG. The signal SAME1 is output, and if it is different, a comparison signal of row 0 is output.

At this time, the first counter 13c counts the comparison signal SAME1 of the first comparison unit 13b whenever the data converter 11 receives the word clock WCLK as shown in FIG. A count signal CNT1 and a detection signal DETCT are generated and outputted. The count signal CNT1 is counted by increasing the count value whenever the comparison result is the same as in (e) of FIG. 6, and the detection signal DETCT6. When the comparison signal SANE1 is detected for six consecutive times, the signal is set to high 1 as in (g) and notified to the other part, and the detection signal DETCT1 is instantaneously when the comparison signal SAME1 becomes the first one. As shown in (f) of FIG. 6, the signal is output as high 1 to be used as an operation start signal of the synchronous storage request unit 14.

In this case, the synchronous write enable signal SWREN used by the synchronous storage request unit 14 is output from the word clock WCLK output from the data converter 11 and the first counter 13c of the synchronous detection unit 13. It is made by the detection signal DETCT1, which is generated by the signal generator 13d.

The signal generator 13d uses an AND gate, and the sync write enable signal SWREN has the same value as the word clock WCLK when the detection signal DETCT1 is 1.

The count signal CNT1 indicates a sequence of synchronization data to be generated internally as a count value of the comparison signal SAME1. That is, if the count signal CNT1 is 0, it indicates OOFF, 1-4 FFFF, and 5 FFOO.

The first synchronous generator 13a receiving the count signal CNT1 is configured as a multiplexer as shown in FIG. 4, and outputs the synchronous data SYNCD1 shown in the diagram in accordance with the input of the count signal CNT1. .

In addition, the configuration and operation of the synchronization storage request unit 14 will be described. The configuration of the synchronization storage request unit 14 is the same as that of the synchronization detection unit 13 as shown in FIG. Let's look at it.

The data WDATA as shown in (b) of FIG. 7 input from the data converter 11 and the data SYNCD2 as shown in (c) of FIG. 7 produced by the second synchronous generator 14a are converted into second data. When compared with the input from the comparator 14b, as shown in FIG. 7 (d), the high comparison signal SAME2 is output, and when different, the low comparison signal is output.

At this time, the second counter 14c outputs the comparison signal SAME2 whenever the sync write enable signal SWREN input from the sync detector 13 is input. For example, as shown in FIG. When the enable signal SWREN is input, the comparison signal SAME2 is counted to generate and output the count signal CNT2 and the write request signal WRRQ as shown in FIG.

The count signal CNT2 indicates a comparison value of the synchronization data to be generated internally and a synchronization data to be stored. That is, 0 indicates OOFF, 1-4 indicates FFFF, and 5 indicates FFOO.

As described above, when the value counted by the second counter 14c is transferred to the second sync generator 14a, the second sync generator 14a is composed of a multiplexer as shown in FIG. As shown in Fig. 2, the synchronization data SYNCD2 corresponding to the count signal CNT2 is output.

Here, when the comparison signal SAME2 is 1 for 6 consecutive synchronous write enable signals SWREN as shown in (a) of FIG. 7, the synchronization signal of 6 words is stored. As shown in (G) of FIG. The synchronous ok signal SYNCOK is set to high to notify the other part. The write request signal WRRQ becomes high when the comparison signal SAME2 is high when the synchronous write enable signal SWREN is input. Save it to

By the way, if only the data WDATA of the type shown in FIG. 6 and FIG. 7 are inputted, the synchronization detection unit and the synchronization storage request unit need to be stored at the same time as the detection without the separate configuration, but similar to the synchronization data as shown in FIG. Can be input, so synchronization detection and synchronization storage must be done separately.

Therefore, data WDATA such as synchronization data SYNCD1 is input at two time points of the word clock WCLK shown in FIG. 8A to start detection and storage.

However, since the data such as 1000 (WDATA) and the second synchronization data (SYNCD1) are not the same at three time points of the word clock (WCLK), the detection can be initialized at this time, but the synchronization of one word at two time points of the word clock (WCLK) is performed. Since the data OOFF has already been stored in the memory, the synchronous storage request unit 14 must wait for the synchronous data FFFF of the next word to come out.

At this time, in FIG. 9, which is an operation timing diagram of the synchronization storage request unit 14, when OOFF, which is the first synchronization data, is input, storage is started, and the same data WDATA as the synchronization data generated by the second synchronization generation unit 14a is started. If is inputted, it can be seen that it works by saving.

Here, of course, you can store the remaining 5 words of synchronous data consecutively regardless of the data (WDATA) when the recording starts, but if you use the memory of the CD-ROM decoder for a long time at once, Since it may adversely affect the operation of the interface unit 5 to transmit, it is necessary to store and store the same as in FIG. 9 unless continuous synchronization data is input as shown in FIG. It will increase the efficiency.

As described in detail above, the present invention simplifies the hardware configuration by configuring a circuit that generates synchronous data to be compared with the synchronous input when synchronous detection is performed, by simplifying the hardware configuration and by dividing the synchronous data whenever a similar synchronous data is detected. It has the effect of improving overall performance and eliminating time delay.

Claims (5)

Data conversion means for converting serial data input from the CD digital signal processor into parallel data in units of 8 bits or 16 bits in accordance with synchronization timing; Synchronization detection means for detecting synchronization data indicating the first block data output from the data conversion means; Synchronization storage means for outputting a reat request signal for finding synchronization data from the parallel data output from the data conversion means and storing it in a memory according to the synchronization write enable signal transmitted from the synchronization detection means; And memory storing request means for storing data from the data converting means in a memory according to the write request signal of the synchronous storage means. 2. The synchronizing detection means according to claim 1, wherein the synchronizing detecting means comprises: synchronizing generating means for creating a synchronizing (SYNC) to be compared, comparing means for comparing the data produced by the synchronizing generating means and data input from the data converting means, and a word for data converting means. Synchronous storage means for counting the number of comparisons through the comparing means and outputting the counted signal at the time of clock input, and for synchronizing write enable signal generated by combining the count signal of the counter and the word clock of the data conversion means; CD-ROM decoder synchronous data processing device, characterized in that consisting of a signal generating means for transmitting. The apparatus of claim 2, wherein the synchronization generating means is a multiplexer. 3. The apparatus of claim 2, wherein the signal generating means is an end gate. The apparatus of claim 1, wherein the synchronization storage means has the same configuration as the synchronization detection means.