JP3017213B1 - FIFO memory monitoring device - Google Patents

Abstract

Abstract: PROBLEM TO BE SOLVED: To increase the scale of a FIFO memory,
Provided is a FIFO memory monitoring device capable of performing fault monitoring and phase monitoring of a FIFO memory. SOLUTION: CRC data of main signal data to be written to a FIFO memory 10 is calculated, and a CRC calculation result 20 is calculated.
And the data head instruction bit 21 indicating the head of the data is multiplexed by the multiplexing unit 19 and then written in synchronization with the head of the next frame data. On the read side, the multiplexed data 31 is read from the read data based on the timing instructed by the write side and the FP 28 in the apparatus, and separated by the separation unit 25. Separated accumulated CRC calculation result 32
Performs the failure monitoring of the FIFO memory by comparing with the CRC data calculated from the read data. The separated stored data head instruction bit 33 is compared with a head instruction signal 40 generated by the read counter circuit 24 to monitor the phases of the write counter circuit 15 and the read counter circuit 24.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a FIFO memory monitoring device, and more particularly, to a FIFO memory monitoring device that monitors FIFO memory control used for format conversion between and within devices.
The present invention relates to an IFO memory monitoring device.

[0002]

2. Description of the Related Art Conventionally, when converting frame data from an opposite device into a frame format in the device, a FIFO (First In First Out) memory is provided in the device. Then, after temporarily storing the frame data from the opposite device in this FIFO memory, the data is firstly stored in the FIFO memory and converted into the frame format in the device in order from the stored data. By using such a FIFO memory, the inter-device clock, which is the reference timing of the transmission timing with the opposing device, and the internal clock, which is the reference timing of the processing timing in the device, are asynchronous with each other and have different operation speeds. However, the frame format can be converted by absorbing these.

In such a FIFO memory, a counter circuit is connected to each of a writing side and a reading side. The write-side counter circuit designates a write entry in the FIFO memory based on a frame pulse (hereinafter, abbreviated as FP) synchronized with the inter-device clock and generates the write timing. The read-side counter circuit designates a read entry in the FIFO memory based on the FP synchronized with the internal clock and generates the read timing. In order to improve the reliability of the frame format conversion by the FIFO memory, there is a FIFO memory monitoring device that monitors the phases of the counter circuit on the writing side and the counter circuit on the reading side of the FIFO memory. This is because the data write instruction bit which indicates the start of data is written into the FIFO memory on the write side, and the data read out at the read timing generated by the read side counter circuit with reference to the FP synchronized with the internal clock of the device. This is performed by comparing the position of the instruction bit with the head position of the data generated by counting by the read-side counter circuit under the read control from the write-side counter circuit.

[0004] Such a FIFO memory monitoring device has an F
In addition to monitoring the phase synchronization between the write timing to the IFO memory and the read timing, the FIFO
A failure of data stored in the O memory is detected. FIF
For example, a Cyclic Redundancy Check (hereinafter, referred to as CR)
Abbreviated as C. ) The arithmetic circuit is connected. This is performed by comparing the CRC operation result of the write data written to the FIFO memory on the write side with the CRC operation result calculated on the read data read on the read side. In order to detect a failure of the data stored in the FIFO memory, a parity bit is generated instead of calculating the CRC data by the CRC calculation circuit.

[0005]

However, the conventional F
The IFO memory monitoring device transmits, on the writing side, a data head bit indicating the head of data, CRC data or a parity bit, in addition to a main signal which is transmitted as frame data from the opposite device and converted into a frame format in the device. Since it is necessary to write data into the FIFO memory and read it out on the reading side, there is a problem that the scale of the FIFO memory becomes large.

SUMMARY OF THE INVENTION An object of the present invention is to provide a FIFO memory monitoring device capable of monitoring a failure and a phase of a FIFO memory without increasing the size of the FIFO memory.

[0007]

According to the first aspect of the present invention, (a) a first monitoring bit for monitoring a main signal portion of frame data for monitoring occurrence of a failure in data of the main signal portion is generated. (B) multiplexing for generating multiplexed data obtained by multiplexing the first monitoring bit generated by the first monitoring bit generation means and a data head indication bit indicating the head of frame data. Means, (c) a main signal part of the frame data and a FIFO memory for storing the multiplexed data generated by the multiplexing means, and (d) a main signal part of the frame data read from the FIFO memory. Second monitoring bit generation means for generating a second monitoring bit for monitoring the occurrence of a failure in the data of the section, and (e) whether the multiplexed data read from the FIFO memory Separating means for separating the first monitoring bit and the data head indication bit; (f) the first monitoring bit separated by the separating means and the second monitoring bit generated by the second monitoring bit generating means (G) a data head instruction signal generating means for generating a data head instruction signal corresponding to the data head instruction bit separately from the data head instruction bit. A) phase monitoring means for monitoring the phases of the write operation and the read operation of the FIFO memory by comparing the data head instruction bit separated by the separation means with the data head instruction signal generated by the data head instruction signal generation means; To FI
The FO memory monitoring device is provided.

That is, according to the first aspect of the present invention, the FIF
On the writing side of the O memory, a first monitoring bit for monitoring the occurrence of a failure in the data of the main signal portion is generated from the main signal portion of the frame data stored in the FIFO memory, and this and the head of the frame data are indicated. And the data leading instruction bit to be multiplexed by the multiplexing means. And
The multiplexed data generated by the multiplexing means is stored together with the main signal portion of the frame data. FIF
On the read side of the O memory, the separating means separates the first monitoring bit and the data head indication bit from the multiplexed data read from the FIFO memory, while the second monitoring bit generating means separates the first monitoring bit from the main signal portion of the frame data. A second monitoring bit for monitoring the occurrence of a failure in the data of the main signal portion is generated, and a data head instruction signal corresponding to the second monitoring bit is generated separately from the data head instruction bit by the data head instruction signal generating means. I did it. Then, a failure monitoring means for monitoring a failure of the FIFO memory by comparing the first monitoring bit with the second monitoring bit, and a write of the FIFO memory by comparing the data head instruction bit with the data head instruction signal. Phase monitoring means for monitoring the phases of the operation and the read operation is provided.

According to the second aspect of the present invention, (a) a FIFO
A memory, and (b) first monitoring bit generation means for generating, from the main signal portion of the frame data, a first monitoring bit for monitoring occurrence of a failure in the data of the main signal portion;
The first monitoring bit generated by the first monitoring bit generation means
Multiplexing means for generating multiplexed data by multiplexing the monitor bit of the frame data and the data head indication bit indicating the head of the frame data, and (d) the first frame from the data start position information described in the header part of the frame data. A frame pulse generating means for generating a pulse, and (e) a main signal portion of frame data based on the first frame pulse generated by the frame pulse generating means and the multiplexed data multiplexed by the multiplexing means in a FIFO memory. FIFO memory writing means for writing, and (f) FIFO memory reading means for reading frame data and multiplexed data from the FIFO memory based on the second frame pulse,
(G) A second monitoring bit for generating a second monitoring bit for monitoring the occurrence of a failure in the data of the main signal portion from the main signal portion of the frame data read from the FIFO memory by the FIFO memory reading means. Generating means;
(H) separating means for separating a first monitoring bit and a data head indication bit from multiplexed data read from the FIFO memory by the FIFO memory reading means; and (iii) first monitoring separated by the separating means. Bit and second
A failure monitoring means for detecting a failure in the FIFO memory by comparing the second monitoring bit generated by the monitoring bit generation means with the second monitoring pulse, and indicating the head of frame data based on the (nu) second frame pulse. Comparing the data head instruction signal generated by the data head instruction signal generated by the data head instruction signal separated by the data head instruction signal generation means with the data head instruction signal generated by the data separation instruction means. By F
The FIFO memory monitoring device is provided with phase monitoring means for detecting a phase mismatch between the FIFO memory writing means and the FIFO memory reading means.

That is, according to the second aspect of the present invention, the FIF
On the writing side of the O memory, a first monitoring bit for monitoring the occurrence of a failure in the data of the main signal portion is generated from the main signal portion of the frame data stored in the FIFO memory, and this and the head of the frame data are indicated. And the data leading instruction bit to be multiplexed by the multiplexing means. Further, the first frame pulse is generated by the frame pulse generation means from the head position information of the data described in the header part of the frame data, and the first signal is generated by the main signal part of the frame data and the multiplexing means based on the first frame pulse. The multiplexed data is written by the FIFO memory writing means. On the reading side of the FIFO memory, the demultiplexing means demultiplexes the multiplexed data read from the FIFO memory by the FIFO memory reading means on the basis of a second frame pulse on the reading side different from the first frame pulse.
While separating the monitoring bit of
The second monitor bit generation means generates a second monitor bit from the main signal part of the frame data for monitoring the occurrence of a failure in the data of the main signal part, and the data start instruction signal generation means generates the second monitor bit. A data head indication signal for indicating the data head of the frame data based on the pulse is generated. A failure monitoring means for monitoring the failure of the FIFO memory by comparing the first monitoring bit with the second monitoring bit, and writing the FIFO memory by comparing the data head instruction bit with the data head instruction signal. Means and phase monitoring means for monitoring the phase of the FIFO memory reading means.

According to a third aspect of the present invention, in the FIFO memory monitoring device according to the second aspect, after a predetermined timing has elapsed after writing to the FIFO memory by the FIFO memory writing means, the FIFO memory reading means is used. Reading is performed.

That is, according to the third aspect of the present invention, the FIF
By starting the read operation to the O memory after a predetermined timing has elapsed since the start of the write operation, reading of the same entry immediately after writing to the FIFO memory or starting from this entry before the end of writing to the FIFO memory is performed. Inconvenience caused by the read operation is avoided.

According to a fourth aspect of the present invention, in the FIFO memory monitoring apparatus according to the second or third aspect, when the phase monitoring means detects a phase mismatch, the FIFO memory monitoring apparatus detects the phase mismatch.
The memory and the FIFO memory writing means and the FIFO memory reading means are initialized.

That is, when the phase monitoring means detects that the phases do not match on the writing side and the reading side, it is determined that the read data is unreliable, and By returning to the initialized state, output of erroneous read data is avoided.

According to a fifth aspect of the present invention, in the FIFO memory monitoring apparatus according to the first to fourth aspects, the multiplexing means is a first memory.
A decoding circuit that outputs multiplexed data uniquely determined in advance by a combination of a monitoring bit and a data head instruction bit, and the separating unit is an encoding circuit that outputs uniquely determined bit data from the multiplexed data. Features.

That is, in the invention according to claim 5, the multiplexing means is a decoding circuit for outputting multiplexed data uniquely determined in advance by a combination of the first monitor bit and the data head indication bit, and the demultiplexing means is configured to output the multiplexed data from the multiplexed data. By using an encoding circuit that outputs bit data uniquely determined in advance, the speed of complicated processing such as multiplexing and demultiplexing can be increased, and the circuit scale can be reduced.

According to a sixth aspect of the present invention, in the FIFO memory monitoring apparatus according to the first to fifth aspects, the multiplexed data multiplexed by the multiplexing means is the first frame of the frame next to the frame data corresponding to the multiplexed data. FIF in sync with
It is characterized in that it is written to the O memory.

That is, in the invention according to claim 6, the multiplexed data multiplexed by the multiplexing means is written into the FIFO memory in synchronization with the head of the next frame of the frame data corresponding to the multiplexed data. The separation processing time allows a margin for the writing timing to the FIFO memory, thereby increasing the processing speed of the entire apparatus.

According to a seventh aspect of the present invention, in the FIFO memory monitoring apparatus according to the first to sixth aspects, the protection means for outputting the result only when the monitoring results of the failure monitoring means are the same by a predetermined number of frames. It is characterized by having.

In other words, according to the seventh aspect of the present invention, when the monitoring result of the failure monitoring means is the same as a predetermined number of frames by the protection means, the result is output for the first time. It is possible to prevent the phase from being inadvertently detected as being inconsistent in spite of the coincidence, thereby improving the reliability of the device.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

FIG. 1 shows a FIFO according to an embodiment of the present invention.
1 shows an outline of a configuration of a memory monitoring device. The FIFO memory monitoring device according to the present embodiment accumulates a main signal for a plurality of frames, and allows the writing side and the reading side to access the FIFO signal independently.
An O memory 10 is provided. On the writing side of the FIFO memory 10, an OH terminating unit 12 where an overhead (Overhead: hereinafter abbreviated as OH) portion of the input inter-device data 11 is terminated, and a main portion which is a data portion of the inter-device data 11. A CRC generator 13 for calculating CRC data as an error correction code of a signal, and a write counter circuit 15 for generating a write timing to the FIFO memory 10 in synchronization with an inter-device clock 14 are provided. The inter-device clock 14 is also input to the OH termination unit 12.

Information indicating the head position of the data is described in a predetermined position of the OH portion of the frame data. The OH terminal unit 12 synchronizes with the inter-device clock 14 from the information indicating the head position of the data, and FP16 is generated, and this transmission path FP16 is supplied to the write counter circuit 15. The write counter circuit 15 counts in synchronization with the inter-device clock 14 based on the transmission path FP16. That is, the write counter circuit 15 performs a CRC operation which is a pulse signal that changes by B clocks from the A-th clock of the inter-device clock 14 based on the transmission path FP16 and indicates a range of a main signal portion which is a data portion of frame data. Control signal 17 is CR
It is supplied to the C generator 13. Further, the write counter circuit 15
Supplies a write enable signal 18 to the FIFO memory 10. The FIFO memory 10 has a plurality of entries, and can store desired write data in a write entry designated at the time of writing. In the write entry of the FIFO memory 10, data is written while sequentially changing the entry by toggling the write enable signal 18. Therefore, the write counter circuit 15 toggles the number of D clocks corresponding to the number of write data from the C-th clock of the inter-device clock 14 with reference to the transmission line FP16.

Further, the FIFO memory monitoring device 10
Has a multiplexing unit 19 on the writing side. And
CRC calculation result 2 generated by CRC generation unit 13
0 is multiplexed with a data head indicating bit 21 indicating the head of data from the outside, and this is multiplexed data 22 as
The data can be stored in the FIFO memory 10 in synchronization with the writing of the inter-device data 11 in the next frame of the corresponding main signal. As a result, the writing to the FIFO memory 10 is prevented from being delayed due to the processing time of the operation, so that the overall processing speed is not reduced. Multiplexer 19
Is composed of a decoder circuit, and converts "n + 1" -bit bit data composed of a plurality of n-bit CRC operation results 20 and, for example, 1-bit data head indication bit 21 into a predetermined "n + 1" It is possible to generate multiplexed data 22 of m bits smaller than bits. That is, m-bit multiplexed data 22 corresponding to a combination of the n-bit CRC calculation result 20 and the 1-bit data head instruction bit 21 is assigned in advance, and this conversion is performed by the decoder circuit of the multiplexing unit 19. The multiplex data 22 generated in this manner
Writes the data into the FIFO memory in synchronization with the head of the inter-device data which is the main signal after the next frame.

On the read side of the FIFO memory 10, the FIFO is synchronized with an internal clock 23 input from the outside.
A read counter circuit 24 for generating a read timing of the O memory 10, a separating unit 25 for separating the CRC operation result multiplexed by the multiplexing unit 19 from the data read from the FIFO memory 10 and a data head instruction bit, A CRC checker 26 for checking the CRC of the output data. The write counter circuit 15 supplies a read control signal 27 instructing the operation of the read counter circuit 24 to the read counter circuit 24 after a lapse of a predetermined number of clocks after the start of the operation. By starting the read control several clocks after the write control, inconveniences such as read immediately after the write and read before the end of the write are avoided.

When a start of counting is instructed by the read control signal 27 from the write counter circuit 15 and an internal FP 28 (not shown) is input from outside, the read counter circuit 24 starts counting in synchronization with the internal clock 23. I do. Then, the read counter circuit 24 supplies the read enable signal 29 to the FIFO 10, and reads the data stored in the device 30 from the read entry designated at that time. The read entry of the FIFO memory 10 reads data while changing the entry in order by toggling the read enable signal 18.

The multiplexed data 22 multiplexed by the multiplexing unit 19 is read out as stored multiplexed data 31 in synchronization with the reading of the internal data 30 from the FIFO 10.
The accumulated multiplex data 31 is input to the separation unit 25. The separating unit 25 separates the CRC operation result multiplexed by the multiplexing unit 19 from the data head instruction bit. Such a separation unit 25 is configured by an encoder circuit, and outputs the encoding logic corresponding to the code logic in the multiplexing unit 19. For example, from the accumulated multiplexed data 31 of m bits,
“N +” which is composed of a plurality of n-bit accumulated CRC operation results 32 and a 1-bit accumulated data head instruction bit 33
1 "bit data can be generated. In other words, the m-bit accumulated multiplexed data 31 is a combination of an n-bit CRC operation result 32 and a 1-bit data start instruction bit 33. The conversion is performed by the encoder circuit of the separation unit 25.

On the read side of the FIFO memory 10, further, a protection unit 35 for protecting the CRC inspected by the CRC inspection unit 26 and a phase guarantee based on the accumulated head data instruction bit 33 separated by the separation unit 25 are provided. And a phase assurance unit 36 for performing the operation. In the protection unit 35, the CRC inspection unit 2
For the first time, when the CRC check signal 37 output from the control unit 6 has the same result for several frames continuously,
Recognize the test results. That is, a comparison mismatch determination is made as the CRC check signal 37 from the CRC checker 26. When the same mismatch determination is made continuously for several frames, this is indicated by the failure detection signal 38 as a FIFO memory failure due to CRC or higher. Notify external devices that do not. The protection circuit control pulse 39 is supplied from the read counter circuit 24 to the protection unit 35 for each frame, and the protection circuit control pulse 39 is supplied a predetermined number of times, and the same result is continuously obtained. Sometimes make them aware for the first time. As a result, it is possible to avoid a coincidence in which a comparison mismatch is determined even though the phases match due to the influence of noise or the like. The protection circuit control pulse 39 is
It is output at the same cycle as the internal FP 28, for example, every 125 microseconds, except that the internal FP 28 is output at the head position of the frame and the protection circuit control pulse 39 is output at a predetermined position in the frame. .

The phase assurance unit 36 is supplied with a head instruction signal 40 from the read counter circuit 24 in addition to the accumulated data head instruction bit 33. The head instruction signal 40 is transmitted to the internal FP2
It is counted in synchronization with the internal clock 23 on the basis of 8, and is output as an instruction of the head of data after a predetermined number of clocks. The phase assurance unit 36 compares the accumulated data head instruction bit 33 separated by the separation unit 25 with the head instruction signal 40 generated by the read count circuit 24, thereby making the write counter circuit 15 and the read counter circuit 24 Phase monitoring. If the accumulated data head instruction bit 33 and the head instruction signal 40 are at different positions in the phase assurance unit 36, the write counter circuit 15 and the read counter circuit 2
4, the data 30 in the apparatus is determined to be unreliable, and the master reset signal 4
Outputs 1. Master reset signal 41 is input to FIFO memory 10, write counter circuit 15, and read counter circuit 24, and initializes all internal states.

FIG. 2 shows an outline of the configuration of frame data in each section of the FIFO memory monitoring device in this embodiment. FIG. 1A shows an outline of the configuration of frame data of the inter-device data 11. 1
The frame data having the data length F of the frame is
And a data section 43. The OH section 42 describes various control information for frame control, for example, data head instruction information 43 indicating a head position of the above-described data at a predetermined position. The OH terminating unit 12 refers to the data head instruction information 44 of the OH unit 42 of the frame data and generates the transmission path FP16 when it is indicated that the data is the head of data. FIG. 2B shows the FIFO memory 1
This shows an outline of the configuration of the write data written in 0. That is, in each write entry of the FIFO memory 10, the multiplexed data 22 in which the data 43, which is the main signal of the inter-device data 11, the CRC operation result 20 and the data head instruction bit (SP) 21 are multiplexed are written. FIG. 3C shows the outline of the configuration of the in-device data 30 read from the FIFO memory 10. As described above, only the main signal portion of the inter-device data 11 is output as the in-device data 30.

Hereinafter, the operation of the FIFO memory monitoring apparatus according to the present embodiment will be described in detail with reference to FIGS.

FIG. 3 shows the write operation timing of the FIFO memory monitoring device in this embodiment. FIG. 5A shows a data phase reference 5 between devices (not shown).
0, which is a phase reference in transmitting frame data to and from the opposite device. The following operation will be described with reference to this phase reference. Frame data from the opposite device is transmitted with a delay of a predetermined α bits from the inter-device data phase reference 50. This frame data is shown in FIG.
Are those shown in (a), each frame is composed of OH portion and a data portion, the first frame 51 ₁ after the second frame 51 _{and second} frame data length F, the third frame 51 ₃ It shall be transmitted continuously (Fig. 3
(B)). In the OH part of the transmitted frame data, the data head instruction information 44 indicating the head of the data is described, and the OH terminal part 12 refers to this and refers to the transmission path FP.
16 is generated (FIG. 3 (c)). The transmission path FP16 is input to the write counter circuit 15, and starts counting in synchronization with the inter-device clock 14 based on the input. Then, after counting by a predetermined number of clocks, a CRC calculation control signal 17 indicating the range of the data portion of the frame data is generated (FIG. 10D), and supplied to the CRC generation unit 13.

The CRC generator 13 calculates the CRC of the main signal part of the frame data indicated by the CRC calculation control signal 17 and outputs the result to the multiplexer 19 as a CRC calculation result 20. The multiplexing unit 19 has a data head instruction bit 2
1 is input as shown in FIG. As described above, in the multiplexing unit 19, the data head instruction bit 21
And the CRC calculation result 20 are multiplexed, and the result is written to the FIFO memory 10 in synchronization with the head of the inter-device data of the next frame. That is, the FIFO memory 10, the frame data 51 ₁ and CRC operation result 20 and data head instruction bit 21 of the main signal, in synchronization with the beginning of the write data 52 ₂ of the next rather than write data 52 ₁ frame written It is. The frame data 51 _2, like, written in synchronization with the beginning of the next write data 52 _3. The write data to the FIFO memory 10 is written with a delay of “α + a” bits from the inter-device data phase reference 50 under the control of the write enable signal 18 after a lapse of a predetermined number of clocks by the write counter circuit 15. The writing is started, and the writing is performed while changing the entries one after another by toggling the write enable signal 18 (FIGS. (F) and (g)).

FIG. 4 shows the read operation timing of the FIFO memory monitoring device in this embodiment. FIGS. 7A and 7B show the inter-device data phase references 50 and F at the write timing shown in FIG.
This is the same as the IFO memory write data 52 _{1 to} 52 ₃ , and the description is omitted. Here, at the timing shown in FIG. 4C, the read control signal 27 is supplied from the write counter circuit 15 to the read counter circuit 24 at a predetermined interval after the start of writing. Further, it is assumed that the internal FP 28 is input from the outside at a fixed period at the timing shown in FIG. The read counter circuit 24 reads the read control signal 2
7, when it is determined that there is a read instruction from the write counter circuit 15, the counting is started in synchronization with the internal clock 23 based on the internal FP 28. After a lapse of a predetermined number of clocks from the internal FP 28, the read enable signal 29 is supplied to the FIFO memory 10 with a delay of, for example, “α + b” bits, and the accumulated F
Reading of IFO data is performed.

The reading of such data from the FIFO memory 10 is started by the reading counter circuit 24 after a lapse of a predetermined number of clocks, with a delay of "α + b" bits from the inter-device data phase reference 50. By causing the enable signal 29 to toggle, the read data 53 _{1 to} 53 ₁ are changed while changing the entry one after another.
3 ₃ read is performed (FIG. (E), (f)) .
In synchronization with this, the accumulated multiplexed data 31 is read from the FIFO memory 10, and the separating unit 25 separates the accumulated CRC operation result 32 and the 1-bit accumulated data leading instruction bit 33 as described above. The read counter circuit 24 supplies a CRC control pulse 34 indicating the range of the main signal portion of the read data to the CRC checker 26 after a predetermined number of clocks has elapsed with reference to the FP 28 in the apparatus (FIG. 9 (g)). ). In the CRC inspection unit 26, the CRC control pulse 3
Then, the CRC of the main signal part designated by 4 is calculated, and this is compared with the accumulated CRC calculation result 32 read out in synchronization with the head of the next frame and separated by the separation unit 25. As described above, the protection unit 35 notifies the failure detection or normality to the outside as the failure detection signal 38 when the comparison result is the same continuously for the predetermined number of times as described above.

In the read counter circuit 24, the internal F
A leading instruction bit 40 is generated based on P28, and the leading instruction bit 40 read out in synchronization with the beginning of the next frame and separated by the separating unit 25 is separated from the leading instruction bit 33 by the phase assurance unit 3.
6 and if they do not match, the master reset signal 40
To initialize the internal states of the FIFO memory 10, the write counter circuit 15, and the read counter circuit 24. Reading data for such normal FIFO memory fault monitoring and phase monitoring was carried out, the inter-device from the data phase reference 50 "α + b + c" bits only with a delay, and is output as device data 54 ₁ to 54 ₃ (Figure (h)).

As described above, the FI in this embodiment is
The FO memory monitoring device calculates the CRC data of the main signal data to be written to the FIFO memory 10, multiplexes the CRC calculation result 20 and the data head indicating bit 21 indicating the head of the data in the multiplexing unit 19, Write in synchronization with the beginning of frame data. Then, on the read side, based on the timing specified by the write side and the internal FP 28, the stored multiplexed data 31 is read from the read data, and the CRC operation result and the data head instruction bit stored are separated by the separation unit 25. The separated accumulated CRC calculation result 32 is compared with the CRC data calculated from the read data to monitor the failure of the FIFO memory. On the other hand, the separated stored data head instruction bit 33 is compared with the head instruction signal 40 generated by the read counter circuit 24 to monitor the phases of the write counter circuit 15 and the read counter circuit 24. As a result, it is possible to provide a FIFO memory monitoring device which enables phase monitoring on the writing side and reading side and failure monitoring of the FIFO memory without increasing the capacity of the FIFO memory 10, thereby achieving high reliability and low cost. become able to.

In the FIFO memory monitoring device according to the present embodiment, C is used as the memory monitoring bit of the FIFO memory.
Although the RC data was used, the present invention is not limited to this.

[0040]

As described above, according to the first aspect of the present invention, the multiplexed data obtained by multiplexing the first monitoring bit and the data head indication bit generated on the writing side to the FIFO memory is used as the main data of the frame data. They are stored in synchronism with the signal section, separated on the read side, and compared with the newly generated second monitoring bit and the data head indication signal, respectively, to monitor the failure of the FIFO memory and read from the write side of the FIFO memory. Side phase monitoring.
As a result, the phase monitoring on the write side and the read side and the FIFO
It is possible to provide a FIFO memory monitoring device that enables monitoring of memory failures and achieves high reliability and low cost.

According to the second aspect of the present invention, the FIF
In the O memory, the first monitor bit is generated based on the first frame pulse generated from the head position information of the data described in the header part of the frame data, and writing is performed in the FIFO memory while the reading side performs the first monitoring bit. Based on a second monitor bit generated by reading the FIFO memory based on a second frame pulse different from the first frame pulse and a data head instruction signal, the failure monitoring of the FIFO memory and the write side of the FIFO memory are performed. By performing phase monitoring on the read side, it is possible to simplify complicated fault monitoring and phase monitoring processing.

Further, according to the third aspect of the present invention, the FI
By starting the read operation to the FO memory after a predetermined timing has elapsed since the start of the write operation, the same entry immediately after writing to the FIFO memory is read, or the same entry before the end of writing to the FIFO memory is read. Can be avoided.

Furthermore, according to the invention of claim 4,
When the phase monitoring means detects that the phases do not match on the write side and the read side, it is determined that the read data is unreliable, and all of the data is returned to the initialized state, thereby causing incorrect read data. Output can be avoided.

According to the fifth aspect of the present invention, the multiplexing means is a decoding circuit for outputting multiplexed data uniquely determined in advance by a combination of the first monitoring bit and the data head indication bit, and the demultiplexing means is a multiplexing means. By using an encoding circuit that outputs bit data uniquely determined in advance from data, it is possible to increase the speed of complicated processing such as multiplexing and demultiplexing, and to reduce the circuit scale.

Further, according to the invention of claim 6,
The multiplexed data multiplexed by the multiplexing means is written into the FIFO memory in synchronization with the head of the next frame of the frame data corresponding to the multiplexed data. With a margin, the processing speed of the entire apparatus can be increased.

According to the seventh aspect of the present invention, when the monitoring result of the failure monitoring means is the same as a predetermined number of frames by the protection means, the result is output for the first time. It is possible to avoid accidentally detecting that the phases do not match even though the phases match, thereby improving the reliability of the device.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an outline of a configuration of a FIFO memory monitoring device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram illustrating an outline of a configuration of frame data in each unit of the FIFO memory monitoring device according to the embodiment.

FIG. 3 is a timing chart showing a write operation timing of the FIFO memory monitoring device in the embodiment.

FIG. 4 is a timing chart showing a read operation timing of the FIFO memory monitoring device in the embodiment.

[Explanation of symbols]

 Reference Signs List 10 FIFO memory 11 Inter-device data 12 OH termination unit 13 CRC generation unit 14 Inter-device clock 15 Write counter circuit 16 Transmission line FP 17 CRC operation control signal 18 Write enable signal 19 Multiplex unit 20 CRC operation result 21 Data start instruction bit 22 Multiplexed data 23 Internal clock 24 Read counter circuit 25 Separator 26 CRC checker 27 Read control signal 28 Internal FP 29 Read enable signal 30 Internal data 31 Stored multiplexed data 32 Stored CRC operation result 33 Stored data start instruction bit 34 CRC control pulse 35 protection unit 36 phase assurance unit 37 CRC check signal 38 failure detection signal 39 protection circuit control pulse 40 start instruction signal 41 master reset signal

──────────────────────────────────────────────────続 き Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 5/06 311 G11C 7/00 318 H04L 7/00

Claims (7)

(57) [Claims] A first monitor bit generator for generating a first monitor bit for monitoring occurrence of a failure in data of the main signal portion from a main signal portion of the frame data; Multiplexing means for generating multiplexed data by multiplexing the first monitor bit generated by the means and a data head indication bit indicating the head of the frame data; a main signal part of the frame data; A FIFO memory for storing the read multiplexed data, and a second monitoring bit for monitoring the occurrence of a failure in the data of the main signal portion from the main signal portion of the frame data read from the FIFO memory. Second monitoring bit generation means; and the first monitoring bit and the data head from the multiplexed data read from the FIFO memory. The FIFO separating means for separating the shown bit by comparing the second monitor bits generated by the separated first monitoring bit and the second monitoring bit generating means by the separating means
Failure monitoring means for monitoring a memory failure; data head instruction signal generating means for generating a data head instruction signal corresponding to the data head instruction bit separately from the data head instruction bit; and the data head instruction separated by the separation means And a phase monitoring means for monitoring the phases of the write operation and the read operation of the FIFO memory by comparing the bits with the data head instruction signal generated by the data head instruction signal generating means. Memory monitoring device. 2. A FIFO memory; first monitoring bit generation means for generating, from a main signal portion of frame data, a first monitoring bit for monitoring occurrence of a failure in data of the main signal portion; A multiplexing unit that generates multiplexed data obtained by multiplexing the first monitoring bit generated by the monitoring bit generation unit and a data head indication bit that indicates the head of the frame data; and a multiplexing unit that is described in a header part of the frame data. A frame pulse generating means for generating a first frame pulse from the head position information of the data, and a main signal part of the frame data and the multiplexing means based on the first frame pulse generated by the frame pulse generating means. FIFO memory writing means for writing the multiplexed multiplexed data to the FIFO memory; FIFO memory reading means for reading the frame data and the multiplexed data from the FIFO memory on the basis of a pulse signal; and a main signal part of the frame data read from the FIFO memory by the FIFO memory reading means. To monitor the occurrence of data failure
Second monitoring bit generation means for generating the monitoring bits of the above, and separation for separating the first monitoring bits and the data head indication bits from the multiplexed data read from the FIFO memory by the FIFO memory reading means. Means for comparing the first monitor bit separated by the separating means with the second monitor bit generated by the second monitor bit generating means.
A failure monitoring unit that detects a failure in the memory; a data head instruction signal generating unit that generates a data head instruction signal that instructs a data head of the frame data based on the second frame pulse; Phase monitoring means for detecting a mismatch between the phases of the FIFO memory writing means and the FIFO memory reading means by comparing the data head instruction bit with the data head instruction signal generated by the data head instruction signal generating means. A FIFO memory monitoring device, comprising: 3. The FIFO memory according to claim 2, wherein the FIFO memory is read by the FIFO memory reading means after a lapse of a predetermined timing from the writing to the FIFO memory by the FIFO memory writing means. FIFO memory monitoring device. 4. When the phase monitoring means detects a phase mismatch, the FIFO memory and the F memory
4. The FIFO memory monitoring device according to claim 2, wherein the FIFO memory writing unit and the FIFO memory reading unit are initialized. 5. The multiplexing means is a decoding circuit for outputting multiplexed data uniquely determined in advance by a combination of the first monitor bit and the data head indication bit, and the demultiplexing means is a unique multiplexed data from the multiplexed data in advance. 5. The FIFO memory monitoring device according to claim 1, further comprising an encoding circuit for outputting bit data determined in accordance with (1). 6. The multiplexed data multiplexed by the multiplexing means is written to the FIFO memory in synchronization with the head of the next frame of the frame data corresponding to the multiplexed data. The FIFO memory monitoring device according to claim 5. 7. The apparatus according to claim 1, further comprising a protection unit that outputs the result of monitoring only when the monitoring result of the failure monitoring unit is the same as a predetermined number of frames.
A FIFO memory monitoring device as described in claim 1.