JPH09172425A - Data error monitoring device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the generation of erroneous synchronization by phase- synchronizing based on CRC data and comparing each of this synchronized frame data so as to output a bit error. SOLUTION: A higher-order group signal is separated from the output of a multiplexer 14 to prepare the same signal as the low-order group signal of the multiplexer 14 by a separation part 3 to select a signal to monitor by a selector 4. The selected signal is frame-synchronized, has CRC data extracted by an extraction part 21 and successively stored in memory 5. On the other hand, the low-order group signal is inputted from the input of the multiplexer 14 to a selector 7 so that a signal to monitor is selected from this to frame- synchronize to extract CRC data by an extraction part 22 and successively stored in a memory 8. Next, a phase synthesizing part 9 executes bit shift by basing on data of one of the memories 5 and 8 as reference to output a bit error at the time of detecting an error.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of monitoring devices for monitoring data errors in data transmission devices such as multiplex converters.

[0002]

2. Description of the Related Art In recent years, the amount of communication associated with data communication has been increasing, reflecting the information society. For this reason, it is required that the communication quality of the data transmission device such as the multiplex conversion device is high, that is, that the data error is immediately dealt with. Multiplexing device (MU
X: MUlitpleX) is a device that is installed in a communication station and transmits data as a high bit rate signal (high order group signal) by time-division multiplexing a low bit rate signal (low order group signal).

The transfer rate (bit rate) in each of the above groups is 1.5 Mbit / s in the primary group and 6.3 Mbit / s in the secondary group.
In the case of H (Presiochronous Digital Hierarcly) system,
The third group is 32 Mbit / s, the fourth group is 100 Mbit / s
s, 5th order group is 400 Mbit / s, SDH
In case of (Synchronous Digital Hierarchy) system, ST
M-0 is 50 Mbit / s, STM-1 is 150 Mbi
It is t / s.

In order to immediately deal with a data error, a monitoring function for detecting the occurrence of the data error is required. In response to such a request, conventionally, there was a function to monitor the occurrence of a failure inside the multiplex conversion device, but this monitoring function covers all from the input to the output of the multiplex conversion device. It was generally not possible to monitor. FIG. 6 is a diagram for explaining a conventional monitoring section area, and shows a case where the low-order group signal is 4.
Note that FIG. 6 shows an example in which the signal on the transmission path is transmitted by the bipolar code.

That is, as shown in FIG. 6, B / U (Bipolar / Unipoler) 11a to 11d,
Synchronization detectors 12a to 12d, ES (Erastic Store) 1
3a to 13d, 15, a synchronization generator 16, U / B (Unipol
er / Bipolar) 17, multiplex converter 18, and the like, and the monitoring section thereof monitors the areas of ESs 13a to 13d and 15 where parity and pattern monitoring are performed and output interruption. Only the area of U / B17 is available. For this reason, for example, there are many devices that cannot monitor the connection of connectors and the like, and in particular, data errors have not been monitored.

Therefore, conventionally, as shown in FIG. 7, the data error monitoring device 1 serving as an external monitoring device branches the input and output (low-order group signal and high-order group signal) of the multiplex converter 14 with high impedance. The method of monitoring the bit error is adopted. FIG. 7 is a circuit block diagram showing a configuration of a conventional data error monitoring device.

As shown in FIG. 7, the data error monitoring apparatus 1 is composed of buffers 2 and 6, a separation unit 3, selectors 4 and 7, memories 5 and 8, a phase synchronization unit 9 and a bit comparison unit 10. . The buffer 2 amplifies a high-order group signal obtained by branching the output signal of the multiplex conversion device 14 and outputs the amplified high-order group signal to the separation unit 3. The separation unit 3 separates the input high-order group signal and The same low order group signal as the 14 low order group signals is created.

The selector 4 selects a signal to be monitored from a plurality of (four in this case) low-order group signals created by the separating unit 3, and the selected signal is stored in the memory 5. The buffer 6 amplifies a plurality of low-order group signals obtained by branching the input signal of the multiplex converter 14 and outputs the amplified signals to the selector 7. The selector 7 selects a signal to be monitored from the plurality of input low-order group signals, and the selected signal is stored in the memory 8.

The phase synchronization unit 9 outputs the signals stored in the memory 5 and the memory 8 to the internal delay of the multiplex conversion device 14, the delay of the monitoring cable, the internal delay of the data error monitoring device 1, and the like, respectively. Since the phases are out of phase with each other due to various delays, the signals are stored in either the memory 5 or the memory 8 as a reference, and bit synchronization is performed by performing a bit shift.

The bit comparison unit 10 starts bit comparison when the phase synchronization unit 9 has achieved phase synchronization, detects a bit error, and outputs a bit error.
In the above configuration, the signals stored in the memory 5 and the memory 8 are bit-shifted and compared as shown in FIG. 8 to constantly monitor the data error (bit error). In the example shown in FIG.
The case where comparison is performed in 8-bit units is shown.

[0011]

However, in the conventional data error monitoring apparatus 1 as described above, after the bit shift is performed by using the signal of either the memory 5 or the memory 8 as a reference, phase synchronization is achieved. Since the signals are compared, there is a problem as described below.

That is, the number of bits of signals to be compared is
If the number of bits is short, the probability of incorrect synchronization increases, and
If the number of bits is long, the probability of missing synchronization due to transmission errors increases. Therefore, it is necessary to determine the optimum number of bits based on the transmission quality and the randomness of data. However, the randomness of data is often "1" or "0" and cannot be guaranteed unless the user uses the line.

Even if an all "1" or all "0" signal is converted by scrambling the signal, if the user data is all "1" or all "0", a scramble pattern is generated. However, the randomness of the data cannot be guaranteed. Therefore, in the data comparison as in the conventional example, when the number of users is small, it is very difficult to reduce the occurrence of false synchronization regardless of the number of bits.

An object of the present invention is to provide a data error monitoring apparatus which solves the above problems and reduces the occurrence of false synchronization.

[0015]

According to another aspect of the present invention, there is provided a data error monitoring device which is generated between a high-order group signal output from a multiplex converter and a plurality of low-order group signals input to the multiplex converter. A data error monitoring device for monitoring a data error, wherein the conversion unit converts a high-order group signal output from the multiplex conversion device into a low-order group signal that is the same as an input signal of the multiplex conversion device; A first selection unit that selects a signal to be monitored from a plurality of low-order group signals output from the first selection unit, a first extraction unit that extracts CRC data from the signal selected by the first selection unit, and the first selection unit. A first storage unit that stores frame data including CRC data extracted by one extraction unit, and a second selection unit that selects a signal to be monitored from a plurality of low-order group signals input to the multiplex conversion device. And the above A second extracting unit for extracting CRC data from the signal selected by the second selecting unit, a second storing unit for storing frame data including the CRC data extracted by the second extracting unit, the first storing unit and the A phase synchronization unit that synchronizes each frame data stored in the second storage unit based on CRC data, and a comparison unit that compares each frame data synchronized by the phase synchronization unit and outputs a bit error. , Are provided.

The data error monitoring apparatus according to claim 2 is
A data error monitoring device for monitoring a data error occurring between a high-order group signal output from a multiplex converter and a plurality of low-order group signals input to the multiplex converter, the data error monitoring device outputting the multiplex converter A high-order group signal to be converted into the same low-order group signal as the input signal of the multiplex conversion device, and a signal to be monitored is selected from a plurality of low-order group signals output from the conversion section. A first selection unit, a first extraction unit that extracts only CRC data from the signal selected by the first selection unit, and a first storage unit that stores the CRC data extracted by the first extraction unit, A second selection unit that selects a signal to be monitored from a plurality of low-order group signals that are input to the multiplex converter, and a second extraction that extracts only CRC data from the signal selected by the second selection unit. Part and the above A second storage unit that stores the CRC data extracted by the extraction unit, a phase synchronization unit that synchronizes the phases of the CRC data stored in the first storage unit and the second storage unit, and the phase synchronization unit. And a comparator that compares the synchronized frame data and outputs a bit error.

Then, the first extraction unit and the second extraction unit in the data error monitoring device according to claim 1 or 2 are reset at the head of the frame pattern and the CRC bit is set as described in claim 3. Exclusive counter of the outputs of the first counter and the second counter, the first counter that counts one frame bit except the second counter, the second counter that resets at the beginning of the frame pattern and counts one frame bit including the CRC bit It is effective to provide a CRC extraction unit having a logic gate that outputs a sum.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit block diagram showing the configuration of the data error monitoring apparatus of the present invention. In FIG. 1, the same elements as those of the conventional example shown in FIG. 7 are designated by the same reference numerals.

The data error monitoring apparatus 1 of the present invention is shown in FIG.
As shown in, buffers 2 and 6, a separation unit 3 that serves as a conversion unit, a selector 4 that serves as a first selection unit, an extraction unit 21 that serves as a first extraction unit, a memory 5 that serves as a first storage unit, and a second selection unit. It is composed of a selector 7, which is a second extraction unit, an extraction unit 22 which is a second extraction unit, a memory 8 which is a second storage unit, a phase synchronization unit 9, and a bit comparison unit 10 which is a comparison unit.

The extraction section 21 and the extraction section 22 are for extracting CRC data from the signals output from the selector 4 and the selector 7, and are provided with a CRC extraction section 31 as shown in FIG. FIG. 2 is a circuit block diagram showing the configuration of the CRC extraction unit. As shown in FIG. 2, the CRC extraction unit 31 includes a counter 32 that serves as a first counter that counts one frame bit excluding CRC bits, and a counter 33 that serves as a second counter that counts one frame bit including CRC bits. , Counter 32 and counter 3
And an exclusive OR gate 34 which is a logic gate for outputting an exclusive OR of the outputs of FIG.
The counter 32 and the counter 33 are both reset at the head of the frame pattern.

Generally, the low-order group signal, as shown in FIG. 3, has a frame synchronization signal (Fsync) and a C for error detection.
RC data and are included. Here, the data length of one frame is 789 bits, and the CR included in one frame is
If the data length of C data is 5 bits, the counter 3
2 is a 789-5 (= 784) bit counter, and the counter 33 is configured as a 789 bit counter.

FIG. 4 is a waveform diagram showing the waveform at each node when a clock signal is input to the circuit shown in FIG. That is, the counter 32, after being reset by the reset signal indicating the frame pattern position, outputs a count-up signal (= “H”) to one input end of the exclusive OR gate 34 at the time point when the clock signal is counted by 784 pulses. (See node A). Similarly, the counter 33 outputs a count-up signal (= “H”) to the other input end of the exclusive OR gate 34 at the time when the clock signal is counted by 789 pulses (see node B).

As a result, the output of the exclusive OR gate 34 becomes "H" based on the count-up signal from the counter 32, and the output becomes "L" based on the count-up signal from the counter 33. That is, since the output timing of "H" from the exclusive OR gate 34 matches the CRC data, only the CRC data can be extracted based on the output signal from the exclusive OR gate 34.

Next, the operation of the above embodiment will be described. First, the high-order group signal is separated from the output of the multiplex conversion device 14, and the same low-order group signal as the low-order group signal of the multiplex conversion device 14 is created by the separating unit 3 via the buffer 2. Then, the selector 4 selects a signal to be monitored from the plurality of low-order group signals generated by the separation unit 3. The signal selected by the selector 4 is subjected to frame synchronization to extract CRC data by the extraction unit 21, and only the CRC data is sequentially stored in the memory 5.

On the other hand, a low-order group signal is input from the input of the multiplex conversion device 14 to the selector 7 via the buffer 6, and the signal to be monitored is selected from this. With respect to the signal selected by the selector 7, the CRC data is extracted by the extraction unit 22 in frame synchronization, and only the CRC data is sequentially stored in the memory 8. Next, with reference to any of the data stored in the memory 5 or the memory 8, the phase synchronization unit 9
Phase synchronization is achieved by performing a bit shift with. Then, when phase synchronization is achieved by the phase synchronization unit 9, bit comparison is started, and if a bit error is detected, a bit error output is performed.

CRC data differs from normal data in that
Unless all the data is unused, it has the property of constantly changing. Therefore, by comparing the CRC data instead of comparing the data as in the conventional example, the randomness of the data to be phase-synchronized can be guaranteed, and the occurrence of unmonitoring due to erroneous synchronization can be reduced. You can As described above, according to the present invention, by extracting and comparing CRC data, it is possible to prevent deterioration of the monitoring capability even with a multiplex conversion device in which the line usage of the user is small, and thus more reliable. It is possible to maintain various monitoring functions.

In the above embodiment, only CRC data is monitored, but if the memory capacities of the memory 5 and the memory 8 are sufficiently large, inter-frame phase synchronization is performed with CRC data and all bits are compared. Is also possible. That is, considering the frame format shown in FIG. 5, the low-order group data is stored in the memory 8 and the high-order group data is stored in the memory 5. And CRC data CR
After detecting only C1 to CRC3 and finding a match between CRC1 and CRC1 ′ in the CRC string, all bits are bit-compared from the data next to CRC1. by this,
More reliable bit comparison can be performed.

[0028]

According to the present invention, by using the CRC data as the comparison data, the randomness of the data can be secured and the occurrence of erroneous synchronization can be reduced. Therefore, it is possible to prevent the data error monitoring device from becoming unmonitorable due to erroneous synchronization.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a configuration of a data error monitoring device of the present invention.

FIG. 2 is a circuit block diagram showing a configuration of a CRC extraction unit.

FIG. 3 is a diagram showing an example of a frame format of a general low-order group signal.

FIG. 4 is a waveform diagram showing waveforms at each node when a clock signal is input to the circuit shown in FIG.

FIG. 5 is a diagram for explaining a data comparison method according to another embodiment.

FIG. 6 is a diagram for explaining a conventional monitoring section area.

FIG. 7 is a circuit block diagram showing a configuration of a conventional data error monitoring device.

FIG. 8 is a diagram for explaining a conventional data monitoring method.

[Explanation of symbols]

 1 Data Error Monitoring Device 2 Buffer 3 Separation Unit 4 Selector 5 Memory 6 Buffer 7 Selector 8 Memory 9 Phase Synchronization Unit 10 Bit Comparison Unit 11a to 11d B / U 12a to 12d Sync Detection Unit 13a to 13d ES 14 Multiplexing Device 15 ES 16 synchronization generator 17 U / B 18 multiplex converter

Claims (3)

[Claims] 1. A data error monitoring device for monitoring a data error occurring between a high-order group signal output from a multiplex converter and a plurality of low-order group signals input to the multiplex converter, said data error monitor comprising: A conversion unit that converts the high-order group signal output from the multiplex conversion device into the same low-order group signal as the input signal of the multiplex conversion device, and monitors from among the plurality of low-order group signals output from the conversion unit. A first selection unit that selects a power signal; a first extraction unit that extracts CRC data from the signal selected by the first selection unit; and frame data that includes the CRC data extracted by the first extraction unit. A first storage unit, a second selection unit that selects a signal to be monitored from a plurality of low-order group signals input to the multiplex conversion device, and CRC data from the signal selected by the second selection unit. Extract A second storage unit for storing frame data including CRC data extracted by the second extraction unit, and CRC for storing each frame data stored in the first storage unit and the second storage unit. A data error monitoring device comprising: a phase synchronization unit that performs phase synchronization based on data; and a comparison unit that compares each frame data synchronized by the phase synchronization unit and outputs a bit error. 2. A data error monitoring device for monitoring a data error occurring between a high-order group signal output from a multiplex conversion device and a plurality of low-order group signals input to the multiplex conversion device, said data error monitoring device comprising: A conversion unit that converts the high-order group signal output from the multiplex conversion device into the same low-order group signal as the input signal of the multiplex conversion device, and monitors from among the plurality of low-order group signals output from the conversion unit. A first selecting section for selecting a power signal, a first extracting section for extracting only CRC data from the signal selected by the first selecting section, and a first storing section for storing CRC data extracted by the first extracting section One storage unit, a second selection unit that selects a signal to be monitored from a plurality of low-order group signals input to the multiplex conversion device, and only CRC data from the signals selected by the second selection unit Second to extract Out section and said a second storage unit for storing CRC data extracted by the second extracting unit, each stored in the first storage unit and the second storage unit CR
A data error monitoring device, comprising: a phase synchronization unit that performs phase synchronization of C data; and a comparison unit that compares each frame data synchronized by the phase synchronization unit and outputs a bit error. 3. The first extracting unit and the second extracting unit are reset at the beginning of a frame pattern, and are reset at the beginning of a frame pattern and a first counter that counts one frame bit excluding CRC bits. A CRC extraction unit having: a second counter that counts one frame bit including a bit; and a logic gate that outputs an exclusive OR of outputs of the first counter and the second counter. The data error monitoring device according to claim 1 or 2.