JPH11215088A - Interconnection system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an interconnection system which performs serial-parallel signal conversion by performing parallel-serial signal conversion, without increasing the transmission capacity at a sending side and establishing frame synchronization based on the data at a receiving side. SOLUTION: A parallel-serial signal converting means 54 converts an arbitrary parallel number of data and a signal from a C-bit generating means 52 into a serial signal, based on a multiplexed clock that is synchronized with a clock in a device. The means 52 makes parallel data an input and outputs the inverted data of the input data, when a frame pulse is insignificant and an interconnection frame generating means 50 outputs non-inverted data when a frame pulse is significant. A synchronous establishing means 56 detects word synchronization and frame phase of a serial signal. A parallel-serial signal converting means 57 terminates arbitrary parallel data and a frame pulse, based on a word identification pulse and a frame phase indicative pulse from the means 56.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a connection between packages in a device, and more particularly to a method of connecting a frame pulse after terminating an SOH (Section Over Head) and a plurality of parallel signals between the packages by reducing the number of connections and increasing the number of parallel signals. The present invention relates to an interconnection system that can be connected with the same transmission capacity as the transmission capacity.

[0002]

2. Description of the Related Art FIG. 16 shows a configuration example of a conventional SOH termination circuit disclosed in, for example, JP-A-8-331088. 1 is RSO
H (Regenerator Section Over Head) Termination, 2 is MSOH
(Multiplex Section Over Head) Terminator, 3 is a pointer processor, 4 is an MSOH generator, and 5 is an RSOH generator.

Next, the configuration of the SOH termination circuit will be described. STM-1 (Synchronous Transport Module -1) data 6
Is input to the RSOH termination unit 1. FIG. 17 shows ITU-T (internat
ionalTelecommunication Union-Telecommunication Sta
This is the frame configuration of the STM-1 data 6 indicated in (ndardization Sector) recommendation G707. The STM-1 data 6 is composed of 270 bytes × 9 rows, and the frame period is 8 kHz. The transmission speed is 270 × 8 × 9 × 8k = 155.52 Mbit /
s. Also, in FIG. 17 (first line, second line, third line)
× 9 bytes for RSOH, (5th to 9th lines) × 9 bytes for MS
Call it OH.

In FIG. 16, the RSOH termination unit 1
The frame synchronization of the M-1 data 6 is established, and a frame pulse 7 indicating the head of the frame is output. Terminate RSOH (processing such as descrambling and RSOH separation)
Then, STM-1 data 8 is output.

At the time of RSOH termination, parallel signal processing is generally adopted from the viewpoint of power consumption and operation speed. Therefore, the STM-1 data 8 after the RSOH termination is also output as a parallel signal. FIG. 16 is a configuration diagram showing a case where eight parallel signal processing is adopted. At this time, the transmission rate per parallel signal is 155.52 Mbit / s × 1/8 = 19.44 Mbit / s.
Note that the hatched lines and “8” added to the STM-1 data line in FIG. 16 indicate that this data is a parallel signal composed of eight lines.

The frame pulse 7 is a section (1 / 19.44) of the synchronization pulse (A1) indicating the beginning of the STM-1 data 6.
MHz) is significant (significant: L).

[0007] The MSOH termination unit 2 receives the input STM-1 data 8
Of the MSOH (processing of MSOH separation, output of K1 and K2 bytes, etc.), the frame pulse 9 and ST after MSOH termination
Outputs M-1 data 10.

The pointer processor 3 replaces or stuffs the pointer value of the STM-1 data with the frame pulse 9, the STM-1 data 10, the frame pulse 11 in the device and the clock 26 in the device from the MSOH terminator 2. , The frame pulse 13 synchronized with the internal clock 26 and
Outputs STM-1 data 14.

[0009] The MSOH generation unit 4 receives the data from the pointer processing unit 3.
A parity operation is performed on the STM-1 data 14, the operation result is multiplexed at a predetermined position of the MSOH, and other data is also multiplexed.
6 is output.

[0010] The RSOH generator 5 adds a frame synchronization bit to the frame pulse 15 and the STM-1 data 16 from the MSOH generator 4.
(A1 / A2) etc. are multiplexed and 8 parallel STM-1 data are serialized into STM-
Convert to 1 data 17.

FIG. 18 is a configuration diagram of an STM-N termination circuit which can be easily constructed from the conventional SOH termination circuit shown in FIG. The STM-N termination circuit terminates each of a plurality of input STM-1 data 6 and multiplexes the data to generate STM-N data. FIG. 18 illustrates a case where N = 16 as an example.

The operation of the STM-N (N = 16) termination circuit shown in FIG. 18 will be described below. The terminating circuit includes 16 reception terminating units 20 each including the RSOH terminating unit 1, the MSOH terminating unit 2, and the pointer processing unit 3, each of which is arranged in parallel. Input 6. Each reception terminating unit 20 performs the above-described RSOH terminating unit 1, MSOH terminating unit 2, pointer processing unit 3 on the input STM-1 data 6.
Performs each signal processing, and STM-
1 Data 14 is output.

The 16 MSOH generating section 21 has 16 receiving terminating sections 2
From 0, the frame pulse 13 and eight parallel STM-1 data 14 are received. Then, the signal processing similar to that of the MSOH generating unit 4 is performed on the STM-1 data 14 in eight parallel with the frame pulse 13 from each reception terminating unit 20, and the frame pulse 15 and the STM-1 data 16 of 16 systems are output. I do.

The 16RSOH generating section 22 multiplexes the frame synchronization bits (A1 / A2) on the 16-system frame pulse 15 and the STM-1 data 16 from the 16MSOH generating section 21 to form an 8 parallel × 16 STM.
-1 data is converted to serial STM-16 data 23.

In the configuration shown in FIG. 18, the number of connections between the 16 reception termination units 20 and the 16 16 MSOH generation units 21 is (1 + 8) × 16 = 144. In other words, when configuring the STM-N termination circuit, if the 16 reception termination units 20 and the 16 16MSOH generation units 21 are respectively arranged in different packages, a large number of connections are required as described above. Become. The number of pins of a connector arranged in a package is limited, and it is required that the number of connections be as small as possible.

In response to this requirement, the mB1C serial transmission system has been adopted as an interconnection system. In the STM-N termination circuit shown in FIG. 18, the STM-1 signal in eight parallel with the frame pulse 13 from each reception termination unit 20
It adopts a 9B1C serial transmission system that transmits 14 with one serial signal.

FIG. 19 shows an ST adopting the 9B1C serial transmission method.
3 shows an MN termination circuit. This circuit uses the conventional STM shown in FIG.
A 9B1C generation unit 24 and a 9B1C termination unit 25 are added to the -N termination circuit. Hereinafter, the operations of the 9B1C generation unit 24 and the 9B1C termination unit 25 will be described.

FIG. 20 shows, for example, the Journal of the Institute of Television Engineers of Japan, Vol1
46, No. 4, pp 413 to pp 417 (1992) is a configuration diagram of a 9B1C serial transmission system that can be easily configured from the conventional 10B1C serial transmission system. 27 is a C bit generation unit, 28 is a P / S conversion unit, 29 is a PLL 1 unit, 37 is a synchronization establishment 1 unit, 38 is a timing extraction unit, and 39 is an S / P conversion unit.

The C bit generation unit 27 inverts the input frame pulse 13 from the reception termination unit 20 and outputs the inverted frame pulse 13 to a P / S conversion unit 28 described later. The P / S converter 28 includes the reception termination unit 20
A 10-parallel signal composed of the frame pulse 13 and the 8-parallel STM-1 data 14 and the signal from the C-bit generating unit 27 is converted into a serial signal 31 based on a multiplexed clock 30 from a PLL 1 unit 29 described later. The PLL1 unit 29 outputs the clock 2 in the device.
A multiplexed clock 30 synchronized with 6 is generated.

FIG. 21 is a block diagram showing a conventional example of the PLL 1 unit 29. 32 is a phase comparison unit, 33 is an LPF unit, 34 is a VCO 1
Reference numeral 35 denotes a 1/10 frequency divider. Next, the operation of each unit will be described. The phase comparing unit 32 compares the phase of the internal clock 26 with the phase of an output signal from a 1/10 frequency dividing unit 35 described later, converts the phase difference into an electric signal, and outputs the electric signal. The LPF unit 33
The high-frequency component contained in the electric signal from the phase comparator 32 is removed, and a VCO control voltage 36 described later is output. VCO1
The unit outputs the multiplexed clock 30 according to the VCO control voltage 36.

Now, the internal clock 26 is set to eight parallel STM-1s.
Assuming a clock synchronized with signal 14, the frequency is 19.44MHz
Becomes At this time, the frequency of the multiplexed clock output from the VCO 1 is 194.4 MHz. The 1/10 frequency divider 35 is
The multiplexed clock 30 from the VCO 1 unit 34 is frequency-divided by 1/10 and output to the phase comparison unit 32.

A timing extracting section 38 provided in the 9B1C terminating section 25 in FIG. 20 extracts a clock from the serial signal 31 from the 9B1C generating section 24. Synchronization establishment 1
The unit 37 establishes 10-bit word synchronization based on the serial signal 31 from the 9B1C generation unit 24 and the clock from the timing extraction unit 38, and outputs a word identification signal 40. The S / P conversion unit 39 converts the serial signal 31 from the 9B1C generation unit 24 based on the clock from the timing extraction unit 38 and the word identification signal 40 from the synchronization establishment unit 37.
After the conversion into 10 parallel signals, the C pulse is removed and the frame pulse 13 and the 8 parallel STM-1 data 14 are output.

[0023]

Since the conventional interconnection apparatus is configured as described above, if the mB1C serial transmission system is adopted as the interconnection system, the amount of input information (8 Parallel
There is a problem that the amount of information corresponding to C bits is increased with respect to the STM-1 signal 14 and the frame pulse 13), and the transmission speed after the parallel / serial signal conversion is increased accordingly.

The C bit is information transmitted in order to detect a word identification pulse for establishing word synchronization on the receiving side in the mB1C serial transmission system. The / P conversion cannot be performed accurately, and the 8-parallel STM-1 signal 14 and the frame pulse 13 input to the transmission side cannot be reproduced.

The present invention has been made in order to solve the above-described problem. The transmission capacity of the serial signal 31 from the 9B1C generation unit 24 becomes equal to the amount of information to be input, and the parallel-to-serial signal conversion is performed. The purpose of the present invention is to obtain an interconnection system in which the transmission speed does not need to be increased later.

[0026]

An interconnection system according to a first aspect of the present invention comprises a multiplexed clock generating means for generating a multiplexed clock synchronized with an internal clock, an arbitrary parallel number of data and a C bit to be described later. The parallel-to-serial signal converting means for converting a signal from the generating means into a serial signal, and one of the arbitrary parallel number data is input, and when a frame pulse is insignificant, inverted data of the input data is output. Interconnection frame generating means for outputting non-inverted data when a pulse is significant; timing extracting means for extracting a clock from a serial signal; and detecting word synchronization and frame phase of the serial signal. Synchronization establishment means, based on a word identification pulse and a frame phase indication pulse from the synchronization establishment means And a parallel serial signal conversion means for terminating any number of parallel data and frame pulse, in which a interconnection frame termination unit having a.

In an interconnection system according to a second aspect of the present invention, the synchronization establishing means includes a delay means for delaying the serial signal by one bit in accordance with a transmission line clock, and an exclusive logic for the serial signal and data from the delay means. C-bit operation means for performing a sum operation, frame period generation means for dividing the transmission line clock to generate a frame period pulse, and dividing the transmission line clock by the number of bits of a period in which C bits are inserted. A word discrimination pulse generating means for generating a word discrimination pulse, and detecting a C bit insertion position and a frame head position based on signals from the transmission line clock, the C bit calculating means, the frame period generating means and the word discrimination pulse generating means. Word identification pulse detection means, wherein the word identification detection means has only one C bit error in one frame. And outputs a word identification pulse and a frame phase indication pulse.

An interconnection system according to a third aspect of the present invention provides a multiplexed clock generating means for generating a multiplexed clock synchronized with an internal clock, an arbitrary number of parallel data and frame data as inputs, and a frame pulse is insignificant. At the time of outputting the arbitrary number of parallel data, and outputting a frame data when the frame pulse is significant, a frame data inserting unit, and converting the signal from the frame data inserting unit and a C bit generating unit described later into a serial signal. Parallel-to-serial signal converting means for converting, and inputting one data of the arbitrary number of parallel data and outputting inverted data of the input data when the frame pulse is insignificant, and outputting the frame data when the frame pulse is significant. C-bit generating means for outputting non-inverted data of one of the following: A frame generation unit, the multiplexed signal 51
A timing extracting unit for extracting a clock from the memory, a synchronization establishing unit for detecting a word synchronization and a frame phase of a serial signal, and an arbitrary parallel number of data based on the word identification pulse and the frame phase indicating pulse from the synchronization establishing unit. Interconnection frame termination means comprising: a parallel / serial signal conversion means for terminating a frame pulse; and frame data termination means for terminating frame data based on the serial data, the transmission line clock, and a frame phase indication pulse from the synchronization establishing means. It is provided with.

An interconnection system according to a fourth aspect of the present invention provides a multiplexed clock generating means for generating a multiplexed clock synchronized with an internal clock, and an arbitrary number of parallel data and a signal from a parity bit generating means to be described later. The parallel / serial signal converting means for converting to a serial signal and the arbitrary parallel number of data are input and odd parity is output when the frame pulse is insignificant, and even parity is output or the frame pulse is insignificant when the frame pulse is significant. C-bit generating means for outputting an even parity and outputting an odd parity when a frame pulse is significant; timing extracting means for extracting a clock from a serial signal; word synchronization of the serial signal; Synchronization establishing means for detecting a frame phase and word identification from the synchronization establishing means Based on pulse and frame phase indication pulse, in which a interconnection frame termination unit and a parallel-serial signal conversion means for terminating any number of parallel data and the frame pulse.

In the interconnection system according to a fifth aspect of the present invention, the synchronization establishing means shifts an arbitrary number of parallel data to generate a parity for each input parallel number data, and divides the transmission line clock. A frame cycle generating means for generating a frame cycle pulse, and a word identification pulse generating means for generating a word identification pulse by dividing the transmission path clock by the number of bits of a cycle in which C bits are inserted; A word identification pulse detection unit for detecting a parity insertion position and a frame head position based on a clock, the parity calculation unit, the frame period generation unit, and a signal from the word identification pulse generation unit; Detecting that there is only one parity error in the frame, the word identification pulse and the frame position are detected. And outputs an instruction pulse.

An interconnection system according to a sixth aspect of the present invention provides a multiplexed clock generating means for generating a multiplexed clock synchronized with an internal clock, an arbitrary number of parallel data and frame data, and a frame pulse is generated. A frame data insertion unit for outputting the arbitrary parallel number of data and outputting the frame data when a frame pulse is significant, and converting a signal from the frame data insertion unit and a parity bit generation unit described later into a serial signal. Parallel-to-serial signal conversion means for inputting the arbitrary parallel number data and the frame data, outputting an odd parity of the arbitrary parallel number data when the frame pulse is insignificant, and outputting the frame data when the frame pulse is significant. Output even parity, or output even parity when frame pulse is insignificant. Interconnection frame generation means for outputting an odd parity when a pulse is significant, timing extraction means for extracting a clock from a serial signal, and synchronization for detecting word synchronization and frame phase of the serial signal. Establishing means, a parallel serial signal converting means for terminating an arbitrary number of parallel data and frame pulses based on the word identification pulse and the frame phase indicating pulse from the synchronization establishing means, the transmission line clock, the serial signal, An interconnection frame termination unit including a frame data termination unit for terminating frame data based on a frame phase instruction pulse.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a configuration diagram showing an embodiment of an interconnection system according to the present invention, and shows an application example to a conventional STM-N termination circuit. This interconnection system has 8 parallel
The STM-1 data 14 and the frame pulse 13 are converted into a serial signal 51.
An interconnection frame terminator 4 for reproducing the 8-parallel STM-1 data 14 and frame pulses from the interconnection frame generator 50 and the serial signal 51
9 is comprised.

Hereinafter, the interconnection frame generation unit 50 and the interconnection frame termination unit 49
Will be described. FIG. 2 is a configuration diagram showing one embodiment of the interconnection frame generation unit 50 and the interconnection frame termination unit 49 according to the present invention. 52
Is a C bit generator 2, 53 is a PLL 2 unit, 54 is a P / S converter, 55 is a timing extractor, 56 is a synchronization establishment 2 unit, 5
Reference numeral 7 denotes an S / P converter.

Next, the interconnection frame generator 50 and the interconnection frame terminator 4 shown in FIG.
9 will be described. The reception termination unit 20 shown in FIG.
8 are input to the P / S converter 54 and the C bit generator 2 52 in FIG. When the frame pulse 14 and the LSB 13h of the STM-1 data are input and the frame pulse is insignificant (H level), the C bit generation 2 unit 52 outputs the inverted data 5 of the LSB 13h of the STM-1 data.
2a is output and S when the frame pulse is significant (L level)
The non-inverted data 52a of the LSB 13h of the TM-1 data is output.

FIG. 3 is a block diagram showing an example of the PLL2 unit 53. 32 is a phase comparison unit, 33 is an LPF unit, 58 is a VCO 2 unit,
59 is a 1/9 frequency divider. Next, the PLL 2 unit 5 shown in FIG.
3 will be described. The phase comparison unit 32
The phase of the internal clock 26 is compared with the phase of an output signal from a 1/9 frequency divider 59, which will be described later, and the phase difference is converted into an electric signal and output. The LPF unit 33 removes high-frequency components included in the electric signal from the phase comparison unit 32 and outputs a VCO control voltage 36 described later.

The VCO2 unit 58 outputs a multiplexed clock 60 according to the VCO control voltage 36. Now, assuming that the internal clock 26 is a clock synchronized with the 8-parallel STM-1 data 14, the frequency is 19.44 MHz. At this time, the frequency of the multiplexed clock output from the VCO 2 is 174.96 MHz, which is nine times the internal clock frequency. The 1/9 frequency divider 59 is
The multiplexed clock 60 from the VCO 2 unit 58 is frequency-divided by 1/9 and output to the phase comparison unit 32.

The P / S converter 54 shown in FIG. 2 uses the multiplexed clock 60 to convert the 8-parallel STM-1 data 13 and the data from the C bit generator 2 52 into a serial signal 51.
Convert to The timing extracting unit extracts the transmission line clock 61 from the serial signal 51 and outputs the same to the synchronization establishing unit 56 and the S / P converter 57 described later.

The synchronization establishing unit 56 outputs a word identification pulse 62 and a frame phase instruction pulse 63 from the serial signal 51 and the transmission line clock 61. FIG.
FIG. 6 is a configuration diagram illustrating an example of a unit 56. 64 is delay 1
, 65 is a C-bit operation unit, 66 is a frame period generation unit, 67 is a word identification pulse generation unit, and 68 is a word identification pulse detection unit.

Next, the operation of the synchronization establishing section 2 shown in FIG. 4 will be described. The delay unit 1 receives the serial signal 51 and the transmission line clock 61 as input, delays the serial signal by one time slot of the transmission line clock, inverts the data itself instead of the bit, and outputs the inverted data to the C-bit operation unit 65.

The C-bit operation unit 65 outputs the serial signal 51
And the data from the first delay unit are input, an exclusive OR operation is performed, and the result is output to a word identification pulse detection unit 68 described later. FIG. 7 shows signals of the respective units. As shown in FIG. 7, the C-bit operation unit 65 outputs a signal which becomes the "L" level every 9 bits as the serial signal 51. However, the frame pulse 14 becomes significant in the C bit generation unit 52, and the time slot to which the non-inverted data is input is at the “H” level.

Referring to FIG. 4, a frame cycle generation section 66
Generates a 8 KHz frame period pulse 69 by dividing the transmission line clock 61. The frame cycle generation unit 66
The transmission line clock 61 is frequency-divided by 1 / (2430 × 9) to generate an 8 KHz frame period pulse 69, which is output to a word identification pulse detector 68 described later.

The word identification pulse generation section 67 is composed of a ring type counter, and outputs a pulse 71 having a word identification cycle having an output frequency of 1/9 of the transmission line clock 61 and a duty of 1/9 at nine phases. Output to the word identification pulse detector 68.

The word identification pulse detector 68 calculates the transmission path clock 61 and the calculation result 7 from the C bit calculator 65.
0, the 9-phase word identification period pulse 71 and the frame period pulse 69 are input, and a word identification pulse 62 and a frame phase instruction pulse 63 are output. FIG. 5 is a configuration diagram showing an example of the word identification pulse detector 68. 72a
72i is a C bit detection unit, and 73 is a selection unit.

Next, the operation of the word identification pulse detector 68 shown in FIG. 5 will be described. C bit detector 72a
Receives the transmission line clock 61, the operation result 70 from the C-bit operation unit 65, the word identification period pulse 71, and the frame period pulse 69, and outputs a C-bit detection pulse 73
a, frame phase indication pulse 74a, and word identification pulse 71a
Is output. Similarly, the other C bit detection units 72b to 72b
Similarly, the transmission line clock 61 and the C-bit operation unit 6
5, the calculation result 70, the frame period pulse 69, and the word identification period pulse 71 are input.

However, nine-phase pulses having different phases are input as the word identification pulse 71. Then, from each C bit detection unit, C bit detection pulses 73b to 73i are output.
And frame phase indication pulses 74b to 74i and word identification pulse
71b to 71i are output. The selection unit 73 monitors the C bit detection pulses 73a to 73i from each of the C bit detection units 72a to 72i, and outputs the word identification pulse 62 and the frame phase indication from the C bit detection unit that outputs a significant signal. The pulse 63 is output.

FIG. 6 is a configuration diagram showing an example of the configuration of the C bit detection units 72a to 72i. 77 is an enable pulse generation unit, 78 is a counting unit, 79 is a comparison unit, 80 is a detection protection unit,
81 is a frame pulse generator, and 82 is a delay 2 unit.

In the following, the C bit detector 72 shown in FIG.
The operation will be described below with reference to a as an example at the timing shown in FIG. Enable pulse generator 7
7 outputs to the counting unit 78 the calculation result 75 of the logical sum of the calculation result 70 from the C-bit calculation unit 65 and the word identification period pulse 71a from the word identification pulse generation unit 67.

The counting section 78 shown in FIG. 6 is a counter which counts up according to the transmission line clock 61 when the operation result 75 from the enable pulse generating section 77 is at L level. Further, the count value is reset every frame period by the frame period pulse 69 from the frame period generation unit 66.

The comparing section 79 compares a preset reference value with the count value from the counting section 78, and outputs a significant signal only when the values are equal. The detection protection unit 80 outputs a significant C-bit detection pulse when the comparison result from the comparison unit 79 receives a significant signal for an arbitrary frame period.

The frame pulse generator 81 shown in FIG.
The exclusive OR operation of the word identification period pulse 71a and the operation result 75 from the enable pulse generator 77 is performed.
The delay unit 82 delays the pulse from the frame pulse generation unit 81 to generate a frame phase instruction pulse 74a that indicates the start position of each frame.

The condition under which the C-bit detection pulse 73a shown in FIG. 6 becomes significant and word synchronization is established is that the C-bit phase of the output signal 70 from the C-bit operation unit 65 matches the phase of the word identification pulse 71a. Is the case. As shown in FIG. 7, the output signal 70 from the C-bit operation unit 65 is
In the time slot where C bit is inserted, L
Level.

However, the C bit generator 2 shown in FIG.
Then, the C bit of the time slot in which the frame pulse 14 becomes significant becomes H level because the non-inverted data is inserted as the C bit. Therefore, when word synchronization is established, the enable pulse generator 77 outputs a significant pulse that is one bit less than the number 2430 of C bits in one frame period. At this time, the count value of the counting section 78 is 24
It becomes 29. If this count value is set in advance to the reference value of the comparison unit 79, a significant signal is output only when word synchronization is established.

The S / P converter 57 serially connects the serial signal 51 and the frame phase indication pulse from the synchronization establishment 2 unit based on the word identification pulse 62 from the synchronization establishment 2 unit.
/ Perform parallel conversion and reproduce 8-parallel STM-1 data and frame pulse.

FIG. 8 is a configuration diagram showing another example of the configuration of the interconnection frame generation unit 50 and the interconnection frame termination unit 49 according to the present invention. The example is
A frame data insertion unit 85 and a frame data termination unit 86 are added to the embodiment shown in FIG. In the drawings, the same functional units are denoted by the same reference numerals.

Next, the operation will be described. The frame data insertion unit 85 receives the eight parallel STs from the reception termination unit 20.
The M-1 data 13, the 8-parallel frame data 87, and the frame pulse 14 are input. When the frame pulse 14 is insignificant, the 8-parallel STM-1 data 13 is output. When the frame pulse 14 is significant, the frame data 87 is output. Output.

The C bit generation 2 unit 52 generates the frame pulse 14, the LSB 13 h of the eight parallel STM-1 data and the frame data 8.
When the LSB of 7 is input and the frame pulse 14 is insignificant,
Output the inverted data of LSB13h of the parallel STM-1 data,
When the frame pulse 14 is significant, the frame data 8
7 outputs the non-inverted data of the LSB.

The PLL2 unit generates a clock having a nine-fold frequency (174.96 MHz) synchronized with the internal clock, and generates a transmission line clock 60. Since the detailed contents of the PLL 2 unit 52 have already been described with reference to FIG. 3, the description is omitted here.

The P / S converter 54 is provided with the multiplexed clock 6
Using 0, the data from the frame data insertion unit 85 and the C bit generation unit 52 are converted into a serial signal 51.

The timing extractor 55 is provided with the serial signal 5
1, a transmission line clock 61 is extracted, and a synchronization establishment 2 unit 56, an S / P conversion unit 57, and a frame data termination unit 86 described below are extracted.
Output to

The synchronization establishing unit 56 outputs a word identification pulse 62 and a frame phase instruction pulse 63 from the serial signal 51 and the transmission line clock 61. The detailed contents of the synchronization establishment 2 unit 56 have already been described with reference to FIGS. 4, 5, and 6, and a description thereof will be omitted.

The S / P converter 57 is provided with the synchronization establishment 2
From the serial signal 51 based on the word identification pulse 62 from
Then, serial / parallel conversion is performed on the frame phase instruction pulse 63 from the synchronization establishment 2 unit 56 to reproduce eight parallel STM-1 data and a frame pulse.

The frame data termination unit 86 terminates the frame data in the serial signal 51 based on the frame phase instruction pulse 63 from the synchronization establishing unit 56.

Embodiment 2 FIG. 9 is a configuration diagram showing another embodiment of the interconnection system according to the present invention, and shows the configurations of the interconnection frame generation unit 50 and the interconnection frame termination unit 49. In the figure, reference numeral 87 denotes a parity generation unit;
Reference numeral 8 denotes a synchronization establishment 3 part. In the figure, for the same function,
The same symbols are given.

Next, the interconnection frame generator 50 and the interconnection frame terminator 4 shown in FIG.
9 will be described. The 8-parallel STM-1 data 13 from the reception termination unit 20 is sent to the P / S conversion unit 54 and the parity generation unit 87.
Is input to The parity generation unit 87 receives the frame pulse 14 and the STM-1 data 13 and outputs an odd parity of the STM-1 data 13 when the frame pulse 14 is insignificant (H level). L level) when S
The even parity of the TM-1 data 13 is output.

However, as described above, the parity generation section 87 can obtain the same effect if the parity logic output when the frame pulse 14 is insignificant is opposite to the parity logic output when the frame pulse is significant. Therefore, even parity may be output when the frame pulse 14 is insignificant, and odd parity may be output when the frame pulse 14 is significant.

The PLL 2 unit 53 generates a multiplexed clock 60 synchronized with the internal clock 26. Multiplexed clock 6
The frequency of 0 is nine times the internal clock frequency.174.
96 MHz. Since the details of the PLL2 unit 53 have already been described with reference to FIG. 3, the description is omitted here.

The P / S converter 54 is provided with the multiplexed clock 6
By using 0, the 8-parallel STM-1 data 13 and the data from the parity generation unit 87 are converted into a serial signal 51. The timing extracting unit 55 extracts the transmission line clock 61 from the serial signal 51 and outputs the same to the synchronization establishing unit 88 and the S / P converter 57 described later. The synchronization establishment 3 unit 88 outputs the serial signal 5
1 and a transmission line clock 61, a word identification pulse 62 and a frame phase instruction pulse 63 are output.

FIG. 10 is a configuration diagram showing an example of the configuration of the synchronization establishing unit 88. In the figure, reference numeral 89 denotes a parity operation unit, and 90 denotes a word identification pulse detection 2 unit. In addition,
In the drawings, the same reference numerals are given to the same functional units.

FIG. 11 is a block diagram showing an example of the configuration of the parity operation section 89 shown in FIG.
The shift register section 94 composed of 91h and each D
It comprises a parity check unit 92 that performs a parity check by using an output signal from the FF as an input.

Next, the operation will be described with reference to FIGS. In FIG. 11, a parity check unit 92
Is the frame pulse 14 in the parity generation section 87.
When an odd parity is output, an odd parity check is performed, and an L level is output when there is no parity error, and an H level is output when there is a parity error.

FIG. 14 shows the waveform of each part. As can be seen from FIG. 14, when the parity check unit 92 has the same data sequence as the data sequence multiplexed by the P / S conversion unit 54, the parity check unit 92 always outputs the L level to the other slots except the frame pulse time slot. Is output. This L level is output every 9 bits. Word identification pulse 6
Reference numeral 2 denotes a pulse synchronized with the L level which appears every 9 bits.

The word identification pulse generation section 67 is composed of a ring type counter, and word identification pulses 71 having an output frequency of 1/9 of the transmission line clock 61 and a duty of 1/9 in nine phases are word-identified, respectively. The signal is output to the pulse detection unit 90.

The word discrimination pulse detection section 90 calculates the transmission path clock 61 and the calculation result 9 from the parity calculation section 89.
3, the word identification period pulse 71 and the frame period pulse 69 are input, and the word identification pulse 62 and the frame phase instruction pulse 63 are output. FIG. 12 is a configuration diagram showing a configuration example of the word identification pulse detection unit 90. FIG.
In 95, reference numerals 95a to 95i denote parity detection units, and 73 denotes a selection unit.

Next, the operation of the word identification pulse detector 2 shown in FIG. 12 will be described. The parity bit detection unit 95a is provided with the transmission line clock 61 and the parity operation unit 8
9, the word identification pulse 71 a and the frame period pulse 69, and the parity bit detection pulse 96 a, the frame phase pulse 97 a, and the word identification pulse 71 are input.
a and the error monitoring result 98a are output. Similarly, the other parity bit detection units 95b to 95I similarly perform the transmission line clock 61, the operation result 93 from the parity operation unit 89, the frame period pulse 69, and the word identification period pulses 71b to 71i.
And input.

However, as the word identification pulses 71a to 71i, nine-phase pulses having different phases are input. Each of the parity bit detection units 95b to 95i includes a parity bit detection pulse 96b to 96I and a frame phase indication pulse 97b to 9
7I, word identification pulses 71b to 71i, and error monitoring results 98b to 98I
Is output. The selection unit 73 monitors the parity bit detection pulses 96a to 96i of the respective parity bit detection units 95a to 95I, and outputs the word identification pulse 62 and the frame phase instruction pulse 63 from the parity detection unit that outputs a significant signal as the parity bit detection pulse. And output the error monitoring result.

FIG. 13 shows the parity bit detectors 95a to 95a.
It is a block diagram showing a configuration example of 5i. Parity bit detector
95a to 95i are the C bit detection units 72a to 72I shown in FIG.
In which an error monitoring unit is added. 99 is an error monitoring unit. In the drawings, the same reference numerals are given to the same functional units.

In the following, the C bit detection unit in FIG.
The operation will be described below with reference to 95a as an example at the timing shown in FIG. The enable pulse generator 77 outputs to the counter 78 the operation result 100 of the logical sum of the operation result 93 from the parity bit operation unit 89 and the word identification pulse 71a from the word identification pulse generation unit 67.

The counting section 78 is a counter which counts up in accordance with the transmission line clock 61 when the operation result 100 from the enable pulse generating section 77 is at L level. Also, the count value is reset every frame period by the frame period pulse 69 from the frame period generation section 66.

The comparing section 79 compares a preset reference value with the count value from the counting section 78, and outputs a significant signal only when the values are the same. The detection protection unit 80 outputs a significant parity bit detection pulse when the comparison result from the comparison unit 79 receives a significant signal during an arbitrary frame period.

The frame pulse generator 81 performs an exclusive OR operation on the word identification pulse 71a and the operation result 100 from the enable pulse generator 77. Delay 2 part 82
Is the pulse 101 from the frame pulse generator 81
To generate a frame phase indicating pulse 97a for indicating the frame head position.

The condition that the parity bit detection pulse 96a becomes significant and word synchronization is established is when the parity bit phase of the output signal 93 from the parity operation unit 89 matches the phase of the word identification pulse 71a.

As shown in FIG. 14, the parity bit operation unit 89
Output signal 93 surely goes to L level in the time slot in which the odd parity bit is inserted. However, the parity bits in the phase of the frame pulse are H
Level. Therefore, when word synchronization is established, the enable pulse generator 77 outputs a significant pulse that is one bit less than the number of parity bits 2430 in one frame period. At this time, the count value of the counting unit 78 is
2429. If this count value is set in advance to the reference value of the comparison unit 79, a significant signal is output only when word synchronization is established.

The error monitoring unit 99 counts the difference between the count value from the counting unit 78 and the count value (2429) of the even parity when there is no error, and counts the number of errors. Further, addition is performed over a plurality of frames to set an arbitrary error rate. When the error rate exceeds the set value, a significant error monitoring result 98a is output.

The S / P converter 57 serially connects the serial signal 51 and the frame phase indication pulse from the synchronization establishing unit 2 based on the word identification pulse 62 from the synchronization establishing unit 2.
/ Perform parallel conversion and reproduce 8-parallel STM-1 data and frame pulse.

FIG. 15 is a block diagram showing another embodiment of the interconnection frame generating section 50 and the interconnection frame terminating section 49 according to the present invention. This embodiment is different from the embodiment shown in FIG.
5 and a frame data termination unit 86 are added.
In the drawings, the same functional units are denoted by the same reference numerals.

Next, the operation will be described. The frame data insertion unit 85 is provided with the eight parallel STM-
1 data 13, 8 parallel frame data 87, and frame pulse 14 are input. When the frame pulse 14 is insignificant, 8 parallel STM-1 data 13 is output, and when the frame pulse is significant, frame data 87 is output.

The parity bit generation unit 87 includes a frame pulse 14, eight parallel STM-1 data 13, and a frame data 87.
When the frame pulse 14 is insignificant, the parallel
Outputs odd parity of STM-1 data 13 and outputs frame pulse 1
When 4 is significant, the even parity of the frame data 87 is output.

However, the parity generation section 87 can obtain the same effect if the parity logic output when the frame pulse 14 is insignificant and the parity logic output when the frame pulse is significant are inconsistent as described above. Therefore, even parity may be output when the frame pulse 14 is insignificant, and odd parity may be output when the frame pulse 14 is significant.

The PLL 2 generates a clock having a nine-fold frequency (174.96 MHz) synchronized with the internal clock, and generates a transmission line clock 60. Since the detailed contents of the PLL 2 unit 52 have already been described with reference to FIG. 3, the description is omitted here.

The P / S converter 54 is provided with the multiplexed clock 6
Using 0, the data from the frame data insertion unit 85 and the C bit generation unit 52 are converted into a serial signal 51.

The timing extractor 55 is provided with the serial signal 5
The transmission line clock 61 is extracted from 1 and output to the synchronization establishment unit 88, S / P conversion unit 57, and frame data termination unit 86 described later.

The synchronization establishing unit 88 outputs a word identification pulse 62, a frame phase instruction pulse 63 and an error monitoring result 102 from the serial signal 51 and the transmission line clock 61. The details of the synchronization establishment 3 unit 56 have already been described in FIGS. 10, 11, 12, and
13, the description is omitted here.

The S / P converter 57 is provided with the synchronization establishment 3
From the serial signal 51 based on the word identification pulse 62 from
Then, serial / parallel conversion is performed on the frame phase instruction pulse 63 from the synchronization establishment 2 unit 56 to reproduce 8-parallel STM-1 data and the frame pulse.

The frame data terminating section 86 terminates frame data from the serial signal 51 based on the frame phase instruction pulse 63 from the synchronization establishing section 88.

[0095]

As described above, according to the first aspect, the inverted data of the input data is arranged in the significant time slot of the frame pulse, and the non-inverted data of the input data is arranged in the insignificant time slot of the frame pulse. Since the arranged signal is generated and transmitted instead of the frame pulse, it is not necessary to transmit the signal in which only the C bit is arranged so far. Therefore, the total amount of the input parallel data and the amount of the parallel-to-serial signal converted data Are equal. .

According to the second aspect of the present invention, the number of C bits in one frame is counted, word synchronization can be established by detecting the position of the C bit, and frame synchronization can be established by detecting the position of the frame pulse. Conversion can be realized stably.

According to the third aspect of the present invention, since arbitrary data of a frame pulse time slot can be inserted on the transmitting side and data can be terminated on the receiving side, there is an effect that data transmission efficiency is improved. .

According to the fourth invention, contradictory parities (even parity or odd parity with respect to odd parity) are arranged in significant time slots and insignificant time slots of frame pulses, respectively. Since a signal in which non-inverted data of input data is arranged in an insignificant time slot of a pulse is generated and transmitted instead of a frame pulse, there is no need to transmit a signal in which only C bits are arranged so far. You. The sum of the parallel data amount and the data amount after the parallel-to-serial signal conversion become equal. Further, by monitoring the result of the parity check on the receiving side, there is an effect that a failure in the transmission path can be grasped. .

According to the fifth aspect of the present invention, the number of parity bits in one frame is counted and the position of the parity bit can be detected, so that word synchronization can be established, and further, frame synchronization can be established by detecting the position of the frame pulse. There is an effect that the serial-parallel conversion can be stably realized. .

According to the sixth aspect of the present invention, since arbitrary data of a time slot of a frame pulse can be inserted on the transmitting side and data can be terminated on the receiving side, there is an effect that data transmission efficiency is improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an STM-N circuit to which an interconnection system according to the present invention is applied.

FIG. 2 is a configuration diagram showing an embodiment of an interconnection system according to a first embodiment of the present invention;

FIG. 3 is a configuration diagram illustrating a configuration example of a PLL2 unit illustrated in FIG. 2;

FIG. 4 is a configuration diagram showing a configuration example of a synchronization establishing unit shown in FIG. 2;

FIG. 5 is a configuration diagram illustrating a configuration example of a word identification pulse detection unit illustrated in FIG. 4;

FIG. 6 is a configuration diagram illustrating a configuration example of a C-bit detection unit illustrated in FIG. 5;

FIG. 7 is a waveform of each part in the configuration example of the interconnection system shown in FIG. 2;

FIG. 8 is a configuration diagram showing a mode of a second embodiment of the interconnection system according to the present invention.

FIG. 9 is a configuration diagram showing a third embodiment of an interconnection system according to the present invention.

10 is a configuration diagram illustrating a configuration example of three units for establishing synchronization illustrated in FIG. 9;

11 is a configuration diagram illustrating a configuration example of a parity operation unit illustrated in FIG. 10;

12 is a configuration diagram illustrating a configuration example of two units of a word identification pulse detection unit illustrated in FIG. 10;

13 is a configuration diagram illustrating a configuration example of a parity bit detection unit illustrated in FIG. 12;

14 is a waveform of each part in the configuration example of the interconnection system shown in FIG.

FIG. 15 is a diagram showing a fourth embodiment of the interconnection system according to the present invention.

FIG. 16 is a configuration diagram illustrating an embodiment of an SOH termination circuit according to an embodiment.

FIG. 17 is a frame configuration of STM-1 data shown in ITU-T Recommendation G707.

FIG. 18 is a configuration diagram illustrating an embodiment of an STM-N termination circuit according to an embodiment.

FIG. 19 is a configuration diagram showing an embodiment of an STM-N termination circuit employing a conventional interconnection system (9B1C serial transmission system).

FIG. 20 is a configuration diagram showing an embodiment of a conventional interconnection system.

21 is a configuration diagram illustrating a configuration example of a PLL1 unit illustrated in FIG. 20;

[Explanation of symbols]

 49 Interconnection frame termination unit 50 Interconnection frame generation unit 52 C bit generation 2 unit 53 PLL2 unit 54 P / S conversion unit 55 Timing extraction unit 56 Synchronization establishment 2 unit 57 S / P conversion unit 64 Delay 1 unit 65 C bit operation Unit 66 frame period generation unit 67 word identification pulse generation unit 68 word identification pulse detection unit 72a to 72i C bit detection unit 73 selection unit 77 enable pulse generation unit 78 counting unit 79 comparison unit 80 detection protection unit 81 frame pulse generation unit 82 delay 2 unit 85 frame data insertion unit 86 frame data termination unit 87 parity generation unit 88 synchronization establishment 3 unit 89 parity operation unit 90 word identification pulse detection 2 unit 91a to 91h DFF unit 92 parity check unit 95a to 95i parity bit detection unit 99 error Monitoring unit

Claims (6)

[Claims] 1. A multiplexed clock generating means for generating a multiplexed clock synchronized with an internal clock, and a parallel-to-serial signal conversion for converting an arbitrary number of parallel data and a signal from a C-bit generating means to be described later into a serial signal. Means, and C-bit generation for inputting one of the arbitrary parallel number data as input, outputting inverted data of the input data when a frame pulse is insignificant, and outputting non-inverted data when the frame pulse is significant. Means, an interconnection frame generating means, a timing extracting means for extracting a clock from a serial signal, a synchronization establishing means for detecting word synchronization and a frame phase of the serial signal, and a word identification pulse from the synchronization establishing means. And a parallel serial signal that terminates an arbitrary number of parallel data and frame pulses based on the frame phase indication pulse An interconnection system comprising: an interconnection frame terminating unit including a conversion unit. 2. Synchronization establishment means: delay means for delaying a serial signal by one bit in accordance with a transmission line clock; C-bit operation means for performing an exclusive OR operation on the serial signal and data from the delay means; Frame period generating means for generating a frame period pulse by dividing the transmission line clock; and a word identification pulse for generating a word identification pulse by dividing the transmission line clock by the number of bits of a period in which C bits are inserted. Generating means, and a word identification pulse detecting means for detecting a C bit insertion position and a frame head position based on signals from the transmission line clock, the C bit calculating means, the frame period generating means, and the word identification pulse generating means, The word identification detecting means detects that there is only one C bit error in one frame, and detects a word identification pulse and a frame. Interconnection system according to claim 1, wherein outputting the phase instruction pulses. 3. A multiplexed clock generating means for generating a multiplexed clock synchronized with a clock in the apparatus, and an arbitrary parallel number of data and frame data as inputs, and when the frame pulse is insignificant, said arbitrary parallel number of data. And frame data insertion means for outputting the frame data when the frame pulse is significant, parallel-serial signal conversion means for converting a signal from the frame data insertion means and a C bit generation means described later into a serial signal, Of the arbitrary number of parallel data, one data is input, and when a frame pulse is insignificant, inverted data of the input data is output.When the frame pulse is significant, one non-inverted data of the frame data is output. An interconnection frame generating means having output C bit generating means; Timing extracting means for extracting, synchronizing means for detecting word synchronization and frame phase of the serial signal, and an arbitrary number of parallel data and frame pulses based on the word identification pulse and the frame phase indicating pulse from the synchronizing means. Terminating parallel-to-serial signal conversion means, and frame data terminating means for terminating frame data based on the serial data, the transmission line clock, and a frame phase instruction pulse from the synchronization establishing means; An interconnection system characterized by being constituted. 4. A multiplexed clock generator for generating a multiplexed clock synchronized with an internal clock, and a parallel-to-serial signal converter for converting an arbitrary parallel number of data and a signal from a parity bit generator described later into a serial signal. Means for inputting the arbitrary number of parallel data and outputting odd parity when the frame pulse is insignificant, outputting even parity when the frame pulse is significant or outputting even parity when the frame pulse is insignificant, Interconnection frame generating means for outputting an odd parity when a pulse is significant; timing extracting means for extracting a clock from a serial signal; synchronization for detecting word synchronization and frame phase of the serial signal Establishing means and a word identification pulse and a frame phase indicating pulse from the synchronization establishing means. And an interconnection frame terminating means comprising an arbitrary number of parallel data and a parallel / serial signal converting means for terminating a frame pulse. 5. Synchronization establishing means for shifting an arbitrary number of parallel data to generate a parity for each input parallel number data, and a frame for dividing the transmission path clock to generate a frame period pulse. A period generation unit, a word identification pulse generation unit that divides the transmission line clock by the number of bits of a period in which C bits are inserted to generate a word identification pulse, the transmission line clock, the parity calculation unit, and the frame A period generation unit; and a word identification pulse detection unit that detects a parity insertion position and a frame head position based on a signal from the word identification pulse generation unit, wherein the word identification detection unit has one parity error in one frame. Detecting a word identification pulse and outputting a word identification pulse and a frame phase indication pulse. 4. The interconnection system according to 4. 6. A multiplexed clock generating means for generating a multiplexed clock synchronized with an internal clock, and inputting arbitrary parallel number data and frame data, and converting the arbitrary parallel number data when a frame pulse is insignificant. A frame data insertion unit that outputs the frame data when the frame pulse is significant; a parallel-serial signal conversion unit that converts a signal from the frame data insertion unit and a parity bit generation unit described below into a serial signal; An arbitrary parallel number data and the frame data are input, and an odd parity of the arbitrary parallel number data is output when a frame pulse is insignificant,
C-bit generating means for outputting even parity of the frame data when the frame pulse is significant, or outputting even parity when the frame pulse is insignificant, and outputting odd parity when the frame pulse is significant. Frame generation means, timing extraction means for extracting a clock from the serial signal, synchronization establishment means for detecting the word synchronization and frame phase of the serial signal, based on a word identification pulse and a frame phase indication pulse from the synchronization establishment means, An interface comprising: a parallel / serial signal converting means for terminating an arbitrary number of parallel data and frame pulses; and a frame data terminating means for terminating frame data based on the transmission line clock, the serial signal, and the frame phase instruction pulse. That the connection frame termination means Interconnection system to butterflies.