JP2644304B2 - Data transmission method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a digital data transmission system used in a system for digitally transmitting a video signal and an audio signal, for example.

(Prior Art) In general, various noises occur on a transmission path, which may cause a transmission data to have a code error. For this reason, in a conventional transmission system, for example, a transmission side adds a bit error detection signal such as a parity bit or a CRC code to digital data and transmits the digital data, and a reception side detects a code error in the received data based on these codes. In addition, the transmission side adds an error correction code such as a BCH code to the digital data and transmits the data, and the reception side performs an error correction operation based on the error correction code to correct the code error of the received data. Much has been done.

However, in this type of conventional transmission system, generally, a transmission side adds a code error detection signal or an error correction code to main digital data and transmits the main digital data. For this reason,
It has been difficult to apply it to a transmission line having transparency. In addition, in order to apply this, the transmission rate of the main digital data must be rate-converted and a signal for code error detection or an error correction code must be added. In this case, a buffer memory for rate conversion and a new Since a complicated clock signal source and the like must be provided, the apparatus becomes complicated and large in size, and further, there is a problem that jitter is easily generated in transmission data due to speed exchange.

(Problems to be Solved by the Invention) As described above, in the conventional method, a signal for detecting a code error or an error correction code is added to main data and transmitted, so that a transmission line having transparency is required. It is difficult to apply it as it is, and there is a problem that the transmission equipment becomes complicated and large in size due to the speed exchange and the transmission quality deteriorates due to an increase in jitter, so the present invention focuses on this point. It is another object of the present invention to provide a data transmission system which can be sufficiently applied to a transmission line having transparency without causing the transmission device to become complicated and large and to reduce the transmission quality.

[Means for Solving the Problems] The present invention relates to a data transmission system for exchanging digital data forming a frame with a zero-continuation suppressing code and transmitting the data. The information for detecting a code error of the digital data of the previous frame is superimposed on the main data by generating a coding rule violation at a predetermined bit position, and is transmitted. The information for code error detection is reproduced by detecting the presence / absence of a code rule violation at the bit position of (1), and a code error detection operation of the received digital data is performed based on the code error detection information.

Still another aspect of the present invention is that the transmission side superimposes an error correction code of digital data of a previous frame on a predetermined bit position in transmission digital data for each frame by generating a code rule violation in main data and transmits the data. On the receiving side, the error correction code is reproduced by detecting the presence or absence of a coding rule violation at the predetermined bit position in the received digital data for each frame, and based on the error correction code, an error of the received digital data is detected. The correction operation is performed.

(Operation) As a result, it is possible to transmit the code error detection information or the error correction code without increasing the data transmission amount,
As a result, even a transmission line having transparency can be sufficiently transmitted as it is. Therefore, speed conversion of transmission data is not required, thereby making it possible to simplify and reduce the size of the transmission device, and further eliminate the occurrence of jitter due to speed conversion, thereby preventing deterioration of transmission data quality. can do.

(Embodiment) FIGS. 3 and 4 show the main components of a transmitting apparatus and a receiving apparatus to which a data transmission system according to an embodiment of the present invention is applied, respectively.

The transmitting device converts the digital data DT comprising the NRZ code into B
A BCH operation unit 11 for performing a CH operation to generate an error correction code BS;
A frame generation circuit 11 for generating a transmission frame signal; a multiplexing unit 13 for multiplexing the error correction code BS and the frame synchronization signal FS in synchronization with the transmission frame signal generated from the frame generation circuit 11; And an encoding circuit 14. The CMI code circuit 14 receives the transmission digital data DT composed of an NRZ code, converts the input digital data DT into a CMI (Coded Mark Inversion) code, which is one of the zero continuous suppression codes, and performs multiplexing on the converted data. Code rule violation CR according to the sign of the superimposed signal CS output from the unit 13
It generates V (Code Rule Violation).
The CMI code is, for example, "01" for "0" of the NRZ code.
Is a code determined so that “11” and “00” appear alternately with respect to “1”. So, like this
The CRV of the CMI code is “10” when the CMI code is “01”, and is “11” and “00” when the CMI code is “00” and “11”.

On the other hand, the receiving apparatus has a CMI code decoding circuit 21. The CMI decoding circuit 21 separates the CRV from the reception digital data CDT including the CMI code arriving via the transmission path, and converts the reception digital data CDT including the CMI code including the CRV into an NRZ code. . Further, the receiving apparatus includes a synchronization signal detection circuit 22 for detecting a synchronization signal FS from the CRV signal sequence CS separated by the CMI decoding circuit 21.
And the synchronization signal detected by the synchronization signal detection circuit 22.
A receiving frame generating circuit 23 for generating a receiving frame signal in synchronization with FS;
Separation unit 245 that separates and extracts only the error correction code from the signal sequence
And an error correction operation circuit 25. The error correction operation circuit 25 converts the NRZ code converted by the CMI decoding circuit 21.
The reception digital data DT composed of a code is operated on the error correction code separated by the separation unit 24, thereby correcting a code error of the reception digital data DT.

With such a configuration, when digital data DT composed of an NRZ code is input to the transmitting device, the digital data DT is introduced into the CMI encoding circuit 14, and the CMI
The code is converted to a CMI code by the coding circuit 14 and transmitted. The digital data DT is also introduced into the BCH operation unit 11, and the BCH operation unit 11 outputs an error correction code K1 for each frame.
KK13 are calculated and introduced into the multiplexing unit 13. And
The error correction codes K1 to K13 obtained for each frame are
The multiplexing unit 13 multiplexes with the separately introduced frame synchronization signal FS in synchronization with the transmission frame signal of the next frame generated from the frame generation circuit 12 and
Introduced to the terminal. Therefore, when exchanging the digital data DT for the CMI code, the CMI encoding circuit 14 violates a coding rule according to the frame synchronization signal FS and the error correction code BS.
The CRV is applied, and the transmission digital data CDT to which the CRV is applied is transmitted to the transmission path.

The bit positions of the frame synchronization signal FS and the error correction codes K1 to K13 in one frame are
Is set as follows, for example. That is, the first
As shown in the figure, the frame synchronization signal FS is arranged at the first bit of each frame, and the error correction codes K1 to K13 are arranged at a fixed interval (5 bit interval in the figure) from the third bit for each frame. Is done. Further, the CMI encoding circuit 14 controls the generation of CRV according to the logic levels of the frame synchronization signal FS and the error correction code BS. For example,
When the logic level is "1", a CRV is generated, and when the logic level is "0", no CRV is generated. This makes it possible for the receiving side to reproduce the frame synchronization signal FS and the error correction code based on the presence or absence of the CRV.

Therefore, for example, the second
Digital data DT as shown in FIG.
If the synchronization bit F of the frame synchronization signal is "1" and the superimposition signal CS in which the error correction codes K1 to K13 of the previous frame are "110010" is input to the CMI encoding circuit 14, the second
First, as shown in FIG. 7B, a CRV indicating the synchronization bit F = "1" is generated at the first bit of the digital data. on the other hand,
The error correction code K1 =
A CRV indicating "1" is generated, and a CRV indicating the error correction code K2 = "1" is generated in the fifth bit from this bit. Thereafter, when the CMI encoding is performed in the same manner, the error correction codes K3, K4, K5, and K6 are added to the digital data at 5-bit intervals.
A CRV is generated according to the logical level of, and transmitted to the transmission path.

On the other hand, in the receiving apparatus, when digital data CDT composed of a CMI code is received and input, the received data is
The decoding circuit 21 converts the code into an NRZ code. At this time, the CRV bit in the received data CDT is returned to the normal code and then
Converted to NRZ code. Therefore, the main data D1 to D63 can be reproduced without losing even one bit.

Also, the CMI decoding circuit 21 outputs a CR from the received data CDT.
The V bit is detected and separated, and the synchronizing signal detecting circuit 22 detects the frame synchronizing signal FS from the CRV bit string by, for example, a multipoint monitoring method. This frame sync signal FS
Is detected, a reception frame signal is generated from the reception frame generation circuit 23, and the separation unit 24 separates and reproduces the error correction code in synchronization with the reception frame signal. In this separation and reproduction method, the insertion position of the CRV indicating the error correction codes K1 to K13 is set in advance so that the third bit is the leading position for each frame and the interval is 5 bits thereafter. First, the presence or absence of a CRV is determined at each of the bit positions from the CRV bit string. When the error correction codes K1 to K13 are separated and reproduced in this manner, the error correction operation circuit 25 performs an error correction operation between the error correction codes K1 to K13 and the received digital data DT one frame before. This corrects an error in the received data. In this embodiment, since a 13-bit BCH code is transmitted for 63-bit data per frame, 2-bit error correction is possible.

As described above, according to the present embodiment, the first bit of the main data is used as the superimposition position of the frame synchronization signal FS for each frame, and each bit position set at 5 bit intervals with the third bit as the top position is error-corrected. Since the frame synchronization signal FS and the error correction codes K1 to K13 are transmitted by generating the CRV according to the logical level of the code at these bit positions as the superposition positions of the codes K1 to K13,
The frame synchronization signal and the error correction code can be transmitted using only the bits of the main data without particularly providing the frame synchronization signal and the bit for transmitting the error correction code in the frame. Therefore, it is not necessary to increase the data input speed in the transmission device, and therefore, a circuit such as a buffer memory for speed conversion and a new clock generator is not required, which simplifies the circuit configuration of the transmission device and reduces its size. Can be Further, since the speed conversion operation is not required, no jitter occurs with the speed conversion operation, so that high transmission quality can be maintained.

Next, a data transmission method according to another embodiment of the present invention will be described. In the method of the present embodiment, an error detection signal such as a CRC code or a parity bit is created for each frame, and the error detection signal is superimposed on a predetermined bit position in the main data using a CRV and transmitted. It is like that.

FIG. 6 and FIG. 7 show the configurations of a transmitting device and a receiving device to which the present system is applied. The difference between these devices in the configuration of the transmitting device and the receiving device of the above embodiment is that the transmitting device uses a CRC instead of the BCH calculating unit 11.
The operation unit 31 is provided, and the receiving apparatus is provided with a CRC operation unit 41 instead of the error correction operation circuit 25, and the operation result is compared with the CRC code separated and reproduced by the separation unit 24 by the comparator 42 to determine the error. This is to detect the presence or absence. still,
6 and 7, the same parts as those in FIGS. 3 and 4 are denoted by the same reference numerals, and detailed description thereof will be omitted.

With such a configuration, when digital data DT composed of an NRZ code is input, this digital data DT
Is converted into a CMI code by the CMI code circuit 14, and the CRC
The calculation unit 31 calculates the CRC code ES. Then, the CRC code ES is multiplexed with a synchronization bit constituting the frame synchronization signal FS by the multiplexing unit 13 in synchronization with the transmission frame signal generated from the frame generator 12 for each frame. Introduced to CRV pin. In the CMI encoding circuit 14, the transmission digital data corresponding to the synchronization bit output from the multiplexing unit 13 and the logic level of the CRC code
A coding rule violation CRV is added to the CMI code bit and transmitted to the transmission path.

The multiplexing unit 13 sets the synchronization bit of the frame synchronization signal FS and the bit position of the CRC code ES (C1 to C5) in one frame as shown in FIG. 5, for example. That is, the synchronization bit F is set at the head bit position of one frame, and the CRC code is set at five bit positions separated from the head bit position at a constant interval (five bit intervals in the figure). Therefore, as shown in FIG. 5, the transmission data CDT output from the CMI encoding circuit 14 and transmitted to the transmission path includes the synchronization bit F superimposed on the data D1 of the first bit for each frame depending on the presence or absence of the CRV, as shown in FIG. It is assumed that CRC codes are respectively superimposed on data D6, D11,. Note that the logic levels of the synchronization bit F and the CRC code ES are the same as those of the previous embodiment.
Is represented by the presence or absence of

On the other hand, in the receiving apparatus, when digital data CDT composed of a CMI code arrives via a transmission path, the data CT
The DT is first code-converted by the CMI decoding circuit 21 into an NRZ code. Then, the digital data DT composed of the NRZ code is supplied as received data to the next-stage circuit as it is, and is also introduced into the CRC operation unit 41, where the CRC operation unit 41 calculates the CRC code.

On the other hand, in the CMI decoding circuit 21, CR
The V bit is detected, the synchronization signal detection circuit 22 detects the synchronization bit F from the bit string of the CRV bit, and the separation unit 24 separates and reproduces the CRC code. As in the case of the error correction code BS of the above-described embodiment, the separation and reproduction of the CRC code is performed at each bit position preset as a superposition bit of the synchronization bit F and the CRC code ES for each frame. This is performed by determining the presence or absence.
When the CRC code is separated and reproduced, the reproduced CRC code and the 1 calculated by the CRC calculation unit 41 are calculated by the comparison circuit 42.
The CRC code of the received data DT before the frame is compared with the CRC code by the comparing circuit 42, and if they do not match, an error signal is generated from the comparing circuit 42 to notify that a code error has occurred.

As described above, according to the present embodiment, similarly to the case of transmitting the error correction code BS of the above-described embodiment, without providing bits for transmitting the frame synchronization signal FS and the CRC code in one frame, only the main data is transmitted. The frame synchronization signal FS and the short frame structure without loss of main data at all
CRC code can be transmitted. Therefore, application to a transparent transmission path as it is becomes possible. In addition, this eliminates the need to provide a circuit such as a buffer memory for speed conversion and a new clock generator in the transmission device, thereby simplifying the configuration of the device and further reducing jitter associated with the speed conversion operation. Since the occurrence can be eliminated, the transmission quality can be kept high.

The present invention is not limited to the above embodiments. For example, a parity bit or other management information may be applied as information to be superimposed on the main data. In addition, the configuration of the transmission device and the reception device, the frame configuration of the transmission data, the bit position on which the error correction code or the error detection information is superimposed, and the like can be variously modified without departing from the gist of the present invention.

[Effects of the Invention] As described in detail above, the present invention uses a code error violation information of the digital data of the previous frame as main data at a predetermined bit position in the digital data for each frame on the transmission side. Is generated and transmitted in a superimposed manner.
The receiving side reproduces the code error detection information by detecting the presence or absence of a coding rule violation at the predetermined bit position in the received digital data for each frame, and receives the received digital data based on the code error detection information. Is performed.

Still another aspect of the present invention is that the transmission side superimposes an error correction code of digital data of a previous frame on a predetermined bit position in transmission digital data for each frame by generating a code rule violation in main data and transmits the data. On the receiving side, the error correction code is reproduced by detecting the presence or absence of a coding rule violation at the predetermined bit position in the received digital data for each frame, and based on the error correction code, an error of the received digital data is detected. The correction operation is performed.

Therefore, according to the present invention, it is possible to provide a data transmission method that can be sufficiently applied to a transmission line having transparency without causing the transmission device to become complicated and large and the transmission quality to be reduced.

[Brief description of the drawings]

FIGS. 1 to 4 are diagrams for explaining a data transmission system in one embodiment of the present invention. FIGS. 1 and 2 show a frame structure of transmission data, and FIG. FIG. 4 is a circuit block diagram showing a main part configuration of a receiving apparatus, and FIGS. 5 to 7 are diagrams for explaining a data transmission system in another embodiment of the present invention. FIG. 5 is a diagram showing a frame configuration of transmission data, FIG. 6 is a circuit block diagram showing a main configuration of a transmission device, and FIG. 7 is a circuit block diagram showing a main configuration of a reception device. 11 BCH calculation unit, 12 frame generation circuit, 13 multiplexing unit, 14 CMI coding circuit, 21 CMI decoding circuit, 22
... Synchronous signal detection circuit, 23 ... Frame generation circuit, 24 ...
Separation unit, 25 Error correction operation circuit, 31, 41 CRC operation unit, 42 Comparison circuit, CRV Code violation, FS Frame synchronization signal, BS (K1 to K13) Error correction Sign, ES (C
1 to C5) ... CRC code.

Claims (2)

(57) [Claims] In a data transmission system for transmitting digital data having a frame structure by exchanging digital data for a zero continuous suppression code, a transmitting side places a digital data of a previous frame at a predetermined bit position in the digital data for each frame. The code error detection information is superimposed on the main data by generating a coding rule violation and is transmitted. The receiving side detects the presence or absence of the coding rule violation at the predetermined bit position in the received digital data for each frame. A data transmission method for reproducing the code error detection information and performing a code error detection operation on received digital data based on the code error detection information. 2. In a data transmission system for transmitting digital data having a frame configuration by exchanging digital data for a zero continuous suppression code, a transmitting side places a digital data of a previous frame at a predetermined bit position in the digital data for each frame. The error correction code is superimposed on the main data by generating a coding rule violation, and is transmitted.The receiving side detects the presence or absence of a coding rule violation at the predetermined bit position in the received digital data for each frame. A data transmission method for reproducing the error correction code and performing an error correction operation on received digital data based on the error correction code.