JP3454527B2 - Data length protection device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data length protection device, and more particularly to a data length protection device in a data transmission device for transferring data having a predetermined fixed data length.

[0002]

2. Description of the Related Art Conventionally, in a data transmission device for transferring data having a predetermined fixed data length,
Even when an abnormality occurs in the data length, the protection against the abnormality in the data length is not performed, and therefore, the data is transferred as it is like the normal data without being recognized as the abnormal data.

For example, in a time division multiplexing apparatus for separating transfer data having a fixed data length sent through a high speed digital line, converting the transfer speed to a low speed and transmitting the data to a terminal such as a personal computer, the data transfer is performed. When converting the speed from high speed to low speed, the transfer data sent at high speed is written in the memory for clock transfer, but the data length of the transfer data is not abnormal. Instead, it is written in the memory for clock transfer.

FIG. 9 is a block diagram showing the configuration of a portion for writing transfer data in a clock transfer memory in a conventional data transmission device. Further, FIG. 10 shows a timing chart in a normal operation of writing transfer data in the conventional clock transfer memory.

In FIG. 9, reference numeral 91 is a clock transfer memory which temporarily stores transfer data DATA and serves as a buffer for speed conversion. Reference numeral 92 is a write address generation unit that sets an address of the clock transfer memory 91 for writing the transfer data DATA. 93
Is a write enable generation unit that generates a signal indicating the timing of writing the transfer data.

The data enable DENB is a signal for indicating whether or not the transfer data DATA is valid. The data head DSTART is a signal for indicating the head of the transfer data DATA. Data synchronization clock WC
LOCK is a reference signal for synchronizing write control of transfer data DATA. 94 is WCLOCK
Transfer data D in units of 16 bits (1 word) synchronized with
It is a data shift unit for generating ATA.

As shown in the time chart of FIG. 10, D
A data string starting from the transfer data DATA input at the rising edge of START is written in a predetermined storage area of the clock transfer memory 91. The address for writing the data string is generated by the write address generation unit 92. Here, the head data of the data string is written at the head address of the storage area of the clock transfer memory 91 generated at the rising timing of DSTART, and the data is read from the clock transfer memory 91 as described above. Are sequentially read from the first address in a predetermined storage area.

The predetermined storage area is an area in which one transfer data having a fixed data length can be written, and addresses of the fixed data length are allocated. In general, writing and reading speeds are different, and writing and reading are sequentially and asynchronously performed. Therefore, a plurality of fixed-length storage areas are prepared so that a plurality of transfer data can be stored. Usually, the plurality of storage areas are continuous areas and continuous addresses are assigned.

[0009]

However, conventionally, the transfer data DA is based on DSTART indicating the beginning of the data.
Since the head data of TA is only written to the position of the head address of the storage area of the clock transfer memory 91, an error occurs in DSTART or the data synchronization clock WCLOCK for synchronizing the data writing. However, it is not detected as an abnormal data length and D
There is a problem in that data shorter than the regular fixed data length is written or data longer than the regular fixed data length is written depending on the timing of the rise of START.

In addition, even though the data having the abnormal data length is written in the clock transfer memory 91, in the processing on the data reading side, the data is always read from the head address of one data storage area. Abnormal data is also read and transferred as it is. In this way, since abnormal data is processed in the same manner as normal data, the data processing efficiency is reduced and the reliability of data transfer is also reduced.

The present invention has been made in consideration of the above circumstances, and when an abnormality occurs in the signal indicating the beginning of the transfer data or the data synchronization clock, the data having an abnormal data length is discarded. By so doing, it is possible to transfer only the data recognized as the normal data length, and to provide a data length protection device that can shorten the data processing time and improve the reliability of the transferred data. .

[0012]

According to a first aspect of the invention, in advance
Indicates the beginning of transfer data with a fixed fixed data length
Input the data write control signal to check the number of data.
Data synchronization clock that becomes the reference for the write process.
The number of data corresponding to the fixed data length is
The data write control signal is input at the same time
By checking whether or not the data of the transfer data
Data length recognition unit that recognizes whether the data length is normal,
A data storage unit for storing transfer data and the data length confirmation
Transfer data to the data storage section based on the recognition result of the knowledge section
A head address generator that generates a head address to write,
Address to write data based on the generated start address
Address that generates the write timing for
Data generation control unit and writing of data to be written in the data storage unit
A data input control unit that controls timing.
The present invention provides a device for protecting the length of the tape. FIG. 1 shows a block diagram of the configuration of the present invention. As shown in the figure, the present invention uses a data write control signal 6 indicating the beginning of transfer data 8 having a predetermined fixed data length and a data synchronization clock 7 as a reference for write processing to transfer data 8 A data length recognition unit 1 for recognizing whether or not the data length is normal, a data storage unit 5 for storing the transfer data 8, and a head address generation unit for generating a head address for writing the transfer data 8 in the data storage unit 5. 2. A data length protection device including a write address generation control unit 3 for generating an address for writing data and a write timing for data, and a data input control unit 4 for controlling a write timing for writing data in the data storage unit 5. Is provided.
Further, the data length recognition unit corresponds to a fixed data length.
Input the data write control signal before counting the number of data.
It was confirmed that the data length of the transfer data was abnormal because
If it is recognized that the above-mentioned head address generation unit is
Start address of transfer data written in the data storage section
You may make it generate | occur | produce the same head address as. The above
The data length recognition unit determines the number of data corresponding to the fixed data length.
The data write control signal was input after counting
If the data length of the transferred data is
If the head address generation unit is
The same destination as the start address of the transfer data written in the memory
The head address may be generated. Data length
Transferred by the recognition unit due to an abnormality in the data synchronization clock
The number of data cannot be counted correctly and the data length is
When it is recognized as abnormal, the start address generation unit
However, the transfer data written in the
To generate the same start address as the start address of the data
You may. Furthermore, the data length recognition unit
After inputting the control signal,
And a counter that counts the number of transfer data
The number of data output from the counter matches the fixed data length
Decoding that outputs a predetermined match signal when
The match signal output from the decode and the data write control
If the control signal and the
A recognition signal indicating that there is is output to the head address generation unit.
It may be provided with an output unit that applies force.

The data length recognizing section 1 counts the data length in order to recognize that the data length of the transfer data 8 is equal to or shorter than a predetermined fixed data length. A counter and a decoder for recognizing the end of the data and determining whether the counted data length is equal to or shorter than the fixed data length are provided.

Further, in order to recognize that the data length of the transfer data 8 is longer than a predetermined fixed data length, the data length recognition unit 1 has a counter for counting the data length and an end of the data. Decoding is provided to determine whether the recognized and counted data length is longer than the fixed data length.

[0015]

According to the present invention, the data length recognizing section can
The data length of the sent data becomes the predetermined data length
Judge whether they are equal and recognize that the data length is abnormal
If this happens, discard this abnormal data
Therefore, only the data recognized as the normal data length is transferred.
Can be sent, data processing time is shortened, and transferred data is reliable
Can be improved.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on the embodiments shown in the drawings. The present invention is not limited to the embodiments. FIG. 2 is a block diagram showing the configuration of the data length protection device according to the embodiment of the present invention. In the figure, reference numeral 21 is a clock transfer memory that temporarily stores transfer data DATA and serves as a buffer for performing speed conversion and the like. Reference numeral 22 is a write address generation unit for setting the address of the clock transfer memory 21 for writing the transfer data DATA.

Reference numeral 23 is a write enable generator for generating a signal indicating the timing of writing the transfer data. Reference numeral 24 is a data shift unit for generating transfer data DATA in units of 16 dots (1 word) synchronized with the data synchronization clock WCLOCK.

Reference numeral 25 is a head address generator for generating a head address for writing the transfer data DATA in the clock transfer memory 21. Reference numeral 26 identifies the start of the transfer data by DSTART indicating the start position of the transfer data and the data synchronization clock WCLOCK for synchronizing the data writing process, and counts the number of data to determine the data length of the transfer data in advance. It is a data length recognition unit that determines whether the data length is equal to the fixed data length.

First, the outline of the operation of this data length protection device in the embodiment will be described with reference to FIG. When DSTART indicating the beginning of the input transfer data DATA is input to the data length recognition unit 26, the data length recognition unit 26 starts counting the data length. In synchronization with this, the transfer data DATA is passed through the data shift unit 24 to the write enable generation unit 23 at the address of the clock transfer memory 21 set by the write address generation unit 22.
It is written at the timing generated in.

When the counted data length is equal to a predetermined fixed data length, the data length recognition unit 2
The head address generating unit 25
Generates the start address of the area where the next transfer data is to be written. Here, the area in which the next transfer data is to be written is an area different from the area in which the current transfer data equal to the fixed data length is written. Write address generator 2
2 uses the head address output from the head address generation unit 25 to generate a write address for the next transfer data and supplies it to the clock transfer memory 21.

When the data length counted by the data length recognizing unit 26 is not equal to the fixed data length determined in advance, the data length recognizing unit 26 does not output a signal for setting the next start address, and the start address Generator 25
Generates the same start address as the one in which the previous data was written, as the start address for writing the next transfer data. That is, the next transfer data is overwritten in the same area of the clock transfer memory as the previous data.

Next, the operation of the data length recognizing section 26 and the head address generating section 25 will be described using a time chart and the like. FIG. 4 is a block diagram of the data length recognition unit 26 and the head address generation unit 25 in the embodiment of the present invention. In FIG. 4, the counter 1 (31) is a 5-bit counter, which counts the number of WCLOCK clocks, that is, the data length (the number of bits) of data synchronized with the clock, and the write operation when the data length is normal or short. It is used to control the. Here, the count number is 0
It shall start from 0H.

The decode 1 (32) recognizes the end of the data, and outputs the output ('H' level) when the count number output from the counter 1 (31) is equal to a predetermined fixed data length. This is the decoding section to be issued.

The counter 2 (33) is a 5-bit counter, which counts the number of WCLOCK clocks, that is, the data length (number of bits) of data synchronized with the clock, and is used for controlling the write operation when the data length is long. To be done.

The decode 2 (34) recognizes that the data length of the transfer data is longer than a predetermined fixed data length, and the count number output from the counter 2 (33) is the fixed data length + 1. It is a decoding unit that outputs (L level) when it becomes.

Reference numeral 35 is an AND gate, which has a decode 1
(32), decode 2 (34) and data head DST
It recognizes whether or not the data length is normal by the input of ART. When the data length is normal and equal to the fixed data length, the'H 'level is sent for a certain period of time.

The counter 3 (36) is a 2-bit counter, and when the data length is normal, that is, "H" is input to the input ENB.
It counts up when the level is input. The encode 1 (37) multiplies the output of the counter 3 (36) by 27, and the output of the encode 1 (37) indicates the start address of the clock transfer memory 21 in which the transfer data is to be written. Decode 3 (38) returns when the output of counter 3 (36) equals 02H.
The "H" level is output, the counter 3 (36) is reset, and the output value of the counter 3 (36) is returned to 00H.

In the embodiment shown here, as shown in FIG.
The fixed data length of one transfer data is 27 words,
Write areas 1, 2 and 3 for only three pieces of transfer data are secured in the clock transfer memory 21, and are sequentially circulated and transferred to each write area of 27 words starting with 00H, 1BH, 36H. Data shall be written.

WCLOCK is a data synchronization clock, and is a signal that serves as a reference for writing the transfer data and a reference for counting the counter. One word of data is written in one clock cycle. DSTART
Indicates the beginning of the transfer data, and since the data length of the transfer data is 27 words, it is normally generated every 27 clocks.

A normal case where the data length of the received transfer data is equal to a preset fixed length will be described. FIG. 5 shows a time chart of the operation when the data length is normal in this embodiment. As shown in the figure, the transfer data is input and the counter 1 (31) and the counter 2 (33) start counting by the DSTART signal.

When one word of data is written every clock and 27 words of transfer data are written,
That is, when the count number output from the counter 1 (31) reaches the final count value 1AH, the decode 1 (3
2) outputs'H 'level. Therefore, the output of the AND gate (35) indicates the “H” level, and the counter 3 (3
6) counts up by +1. As a result, the start address indicated by the output of the encode 1 (37) is 27 (= 1
BH) is added, the head address of the next write area of the clock transfer memory 21 is designated, and the next data is written in this write area.

Next, an operation will be described when an abnormality occurs in DSTART which is a signal indicating the head of the data length of transfer data and the data length is recognized as short. FIG. 6 shows a time chart when the data length is recognized as short. As shown in the figure, at the 18H (= 24) th word of the data A whose head is indicated by DSTART (A), the next DSTA
It is assumed that the RT (B) 'H' level is input. At this time, the data A is written in the clock transfer memory 21 for 18H words.

In the figure, both the counter 1 (31) and the counter 2 (33) are reset because the'H 'level of DSTART is input, but the counter 1 (31)
Since the count number output from does not indicate the final value (= 1 AH), there is no'H 'level in the output of the decode 1 (32).

Therefore, "H" is output to the output of the AND gate (35).
There is no level, and the counter 3 (36) does not count up. That is, the data B whose head is indicated by DSTART (b) is sequentially written from the head of the same writing area where the data A was written. Therefore, the next data B is overwritten on the data A, so that the abnormal data A in which only 18H words are written is discarded.

Next, the operation when an abnormality occurs in DSTART and a long data length is recognized will be described. FIG. 7 shows a time chart when a long data length is recognized.
As shown in the figure, there is no'H 'level of DSTART that should be at the position of the final data count number (= 1 AH) of the data C whose head is indicated by DSTART (C), and the counter 1 (31) DSTA when showing 1CH
Assume that RT (d) has reached the'H 'level.

At this time, since the count number output from the counter 2 (33) is 1 BH, the decode 2
(34) outputs the'L 'level. Since the count number starts from 00H, the count number 1BH is 1CH.
This means that (fixed data length + 1) pieces of data have been written. Therefore, there is no'H 'level in the output of the AND gate (35), and the counter 3 (36) does not count up. That is, the data D whose head is indicated by DSTART (d) is sequentially written from the head of the same writing area where the data C was written. Therefore, when the data D is overwritten on the data C, the abnormal data C having an increased data length is discarded.

Next, the operation when an abnormality occurs in the data synchronization clock WCLOCK will be described. In Figure 8, WCL
The time chart when abnormality occurs in OCK and one clock is missing is shown. As shown in the figure, DSTA
17H of data E whose head is indicated by RT (e) (=
23) Clock WCLO at position (I) next to word
It is assumed that one CK is missing.

At this time, the counter 1 (31) and the counter 2 (33) are not counted up by one word,
DST indicating the beginning of the next data after the 27th clock
When the “H” level of ART (f) is input, the count value of the counter 1 (31) still shows 19H (= 25).

Therefore, when DSTART (to) indicates the'H 'level, there is no'H' level in the output of the decode 1 (32). Therefore, "H" is applied to the AND gate (35).
There is no level, and the counter 3 (36) does not count up. That is, the data F whose head is indicated by DSTART (to) is sequentially written from the head of the writing area in which the data E was written. Therefore, by overwriting the data F on the data E, the abnormal data E in which only 19H words have been written are discarded.

[0040]

According to the present invention, the data length recognition section determines whether or not the data length of the transfer data is equal to a predetermined data length, and if the data length is recognized as abnormal, Since this abnormal data is discarded, only the data recognized as having a normal data length can be transferred, and the data processing time can be shortened and the reliability of the transferred data can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of the present invention.

FIG. 2 is a block diagram showing a configuration of an apparatus according to an embodiment of the present invention.

FIG. 3 is a configuration diagram of a clock transfer memory according to the embodiment.

FIG. 4 is a detailed block diagram of a data length recognition unit and a head address generation unit in the embodiment.

FIG. 5 is a time chart showing an operation at a normal time in the embodiment.

FIG. 6 is a time chart when the data length is recognized to be short in the embodiment.

FIG. 7 is a time chart when a long data length is recognized in the embodiment.

FIG. 8 is a time chart when an abnormality occurs in the data synchronization clock in the embodiment.

FIG. 9 is a block diagram showing a configuration of a conventional example.

FIG. 10 is a time chart showing a normal operation in the conventional example.

[Explanation of symbols]

21 Clock transfer memory 22 Write Address Generator 23 Write Enable Generation Unit 24 Data shift section 25 Start address generator 26 Data length recognition section

Claims (5)

(57) [Claims] Input of 1. A data write control signal indicating the beginning of the transfer data having the data length of a fixed defined previously
The force, starts counting the number of data, fixed data based on the data synchronous clock as a reference for the writing process
Data at the same time when the number of data corresponding to the length is counted
Check if the write control signal is input
Accordingly, recognizing the data length recognition unit whether the data length of the transfer data is normal, a data storage unit for storing the transfer data, the transfer data based on the recognition result of the data length recognition unit data A head address generation unit that generates a head address to be written to the storage unit, a write address generation control unit that generates an address to write data and a write timing of data based on the generated head address, and a data storage unit . A data length protection device comprising a data input control unit for controlling a write timing of data to be embedded. 2. The data length recognition unit uses a fixed data length.
Data writing control before counting the corresponding number of data
Since the signal was input, the data length of the transfer data was abnormal.
When recognizing that there, the head address generation unit, the data of claim 1, wherein the benzalkonium generates the same top address and the start address of the written in the data storage unit to the abnormality occurring transmitted data Long protection device. 3. The data length recognition unit uses a fixed data length.
Data writing control after counting the corresponding number of data
Since the signal was input, the data length of the transfer data was abnormal.
When recognizing that there, the head address generation unit, the data of claim 1, wherein the benzalkonium generates the same top address and the start address of the written in the data storage unit to the abnormality occurring transmitted data Long protection device. 4. The data length recognition unit is configured to synchronize the data.
Correct the number of transferred data due to clock error.
If you cannot count and recognize that the data length is abnormal,
If the head address generation unit, the data length of Claim 1, wherein the benzalkonium generates the same top address and the start address of the written in the data storage unit to the abnormality occurring transfer data protection system. 5. The data length recognition unit is a data writing system.
After inputting the control signal, the data sync clock is used as a reference.
A counter that counts the number of transmitted data, The number of data output from the counter matches the fixed data length
Decoding that outputs a predetermined match signal when Matching signal output from the decoding and the data writing
If the control signal and the
A recognition signal indicating that the head address is always generated
An output unit for outputting to
Data length protector.