JP3161795B2 - Phase controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase controller, and more particularly to a phase controller for serially transmitting a plurality of time-division multiplexed digital signals.

[0002] In recent years, the amount of transmission information has been dramatically increased with the increase in various data transmission devices such as the number of communication lines and facsimile machines. Under such circumstances, as a method of increasing the amount of transmission information without deteriorating the quality of the data to be transmitted, measures such as using an optical cable for a communication line, increasing the communication frequency, and time division multiplexing have been taken. I have.

[0003] Among these measures, in time division multiplexing,
The following data processing is performed in the transmitting device and the receiving device. The transmitting device converts a plurality of digitalized data into a serial signal by time division multiplexing and transmits the serial signal. Further, the receiving device recognizes individual signals included in the received serial signal (hereinafter, referred to as “received signal”) and restores the data to a plurality of original digital signals. At the time of this restoration, the communication speed of the received signal and the processing speed of the receiving device generally differ. Therefore, the receiving device needs to convert the phase of the received signal in order to output the received signal at a predetermined timing that is easy to handle.

A device for converting the phase of the received signal is a phase control device, and two phase conversion methods are conventionally known. One is a method of converting the phase of a received signal through a delay circuit to a predetermined timing, and the other is a method of writing the received signal to a memory and reading the written received signal at a predetermined timing. .

However, in a phase control device that converts a phase through a memory, the timing at which a received signal is written to the memory may coincide with the timing at which the written received signal is read from the memory. Specifically, this is a state in which the received signal is written to the memory and the written received signal is read at the same time. Therefore,
Since the data is read before the internal state of the memory is determined, the read reception signal (hereinafter, referred to as “output signal”) is indeterminate, and a read data error has occurred.

[0006]

2. Description of the Related Art Conventionally, when the timing of writing a received signal to a memory coincides with the timing of reading an output signal from a memory, the writing of the received signal is delayed until a safe timing.

FIG. 4 is a schematic block diagram of a conventional phase control device. Referring to FIG. 1, a conventional phase control device includes a signal receiving unit 10, a write synchronization signal generation circuit 11, a synchronization signal switching circuit 12, a digital memory 21, a write address signal counter 22, a read address signal counter 23, and a synchronization signal coincidence detection. It comprises a circuit 31.

The signal receiving section 10 receives a communication signal S10 transmitted through a transmission medium such as a communication cable, detects a synchronization pattern such as a leading pulse of the communication signal S10, and outputs a reception signal D1 and a frame synchronization signal S11. I do.
The write synchronizing signal generating circuit 11 receives the frame synchronizing signal S11 and outputs two write synchronizing signals S12a and S12b which are shifted from each other by a half cycle. Note that the length of one cycle of the two write synchronization signals S12a and S12b is the same as the length of the frame synchronization signal S11. Synchronous signal switching circuit 1
2 is a switch signal S14, and two write synchronization signals S1
One of 2a and S12b is output as actual write synchronization signal S13.

The write address signal counter 22 starts counting by the actual write synchronization signal S13 and outputs a write address signal AD1. The write address of the digital memory 21 is sequentially selected by the write address signal AD1, and the received signal D1 is written to the digital memory 21 bit by bit. On the other hand, the read address signal counter 23 starts counting by the read synchronizing signal S20 and outputs the read address signal AD2. The read address of the digital memory 21 is sequentially selected by the read address signal AD2, and the output signal D2 is read from the digital memory 21 bit by bit. Digital memory 21 temporarily stores reception signal D1 in synchronization with write address signal AD1, and outputs output signal D2 in synchronization with read address signal AD2.

The synchronization signal coincidence detection circuit 31 outputs a switching signal S14 when the actual write synchronization signal S13 matches the read synchronization signal S20. For example, when the switching signal S14 is at a low level, the synchronization signal switching circuit 12 selects the write synchronization signal S12a, and when the switching signal S14 is at a high level, selects the write synchronization signal S12b to perform actual writing. It is output as a synchronization signal S13.

With this configuration, when the timing of writing the received signal D1 to the digital memory 21 and the timing of reading the output signal D2 from the digital memory 21 match, the synchronization signal match detection circuit 31 detects this match. I do. That is, the synchronization signal coincidence detection circuit 31
Detects an overlap between the actual write synchronization signal S13 and the read synchronization signal S20, and outputs a switching signal S14. By this switching signal S14, two write synchronization signals S12a and S1 are generated.
2b, a write synchronization signal having a cycle different from that of the read synchronization signal S20 is selected and output as a new actual write synchronization signal S13. Therefore, the start of counting of the write address signal counter 22 and the start of counting of the read address signal counter 23 are shifted, so that the output signal D2 can be correctly read without the addresses of the write address signal AD1 and the read address signal AD2 overlapping. .

FIG. 5 is a time chart of signals by a conventional phase control device. Note that the same signals as in FIG. 4 are given the same signal names. In the figure, a read synchronization signal S20, a read address signal AD2, and an output signal D
2, the signals and data contents of the reception signal D1, the frame synchronization signal S11, the write synchronization signals S12a and S12b, the actual write synchronization signal S13, the switching signal S14, and the write address signal AD1 are shown.

In the figure, at time t11, the pulse of the actual write synchronization signal S13 and the pulse of the read synchronization signal S20 overlap. For this reason, the synchronization signal coincidence detection circuit 31 detects the coincidence of the signals, and switches the switching signal S14 which was initially at the low level to the high level as shown by the arrow X11. The change in the switching signal S14 causes the synchronization signal switching circuit 12 to switch the write synchronization signal S12a selected so far to the write synchronization signal S12b, so that the actual write synchronization signal S13 is written as indicated by the arrow X12. Synchronization signal S1
2b. At time t12, the write address signal counter 22 is turned on by the actual write synchronization signal S13.
Is reset, and the address value of the write address signal AD1 is initialized from “6” to “1”.

Thus, the overlap between the actual write synchronizing signal S13 and the read synchronizing signal S20, that is, the timing at which the reception signal D1 is written to the digital memory 21, and the output signal D
2 can be prevented from being coincident with the timing for reading out from the digital memory 21.

However, the communication signal S10 is susceptible to noise and the like, and with this, the received signal D1 also has a fluctuation of several bits generally called "timing jitter". For this reason, the timing at which the reception signal D1 is written to the digital memory 21 and the timing at which the output signal D2 is read from the digital memory 21 may coincide after a considerable time has elapsed.

FIG. 6 is a time chart when a fluctuation occurs in the received signal. Note that the same signals as those in FIG. 5 are denoted by the same signal names, and description thereof is omitted. In the figure,
The pulse of the read synchronizing signal S20 rises at time t21 and falls at time t22. The actual write synchronization signal S
The pulse 13 rises at time t22 and falls at time t23. For this reason, the synchronization signal coincidence detection circuit 31
No overlap between the pulse of the read synchronization signal S20 and the pulse of the actual write synchronization signal S13 is detected.

However, if the communication signal S10 fluctuates as time elapses, the received signal D1, the actual write synchronization signal S13, and the like also fluctuate accordingly. Finally, at time t24, the read synchronization signal S
There is a case where the pulse of 20 and the pulse of the actual write synchronization signal S13 overlap. At time t25, the write address signal counter 22 is reset by the actual write synchronization signal S13, and the address value of the write address signal AD1 is initialized from "6" to "1". In the vicinity of this time t24,
At the same time as writing the reception signal D1 to the digital memory 21, the output signal D2 is read from the digital memory 21.

[0018]

Therefore, it cannot be determined whether there is a margin in the timing interval between the read synchronizing signal S20 and the actual write synchronizing signal S13, so that a read data error occurs near the time t24. There was a problem.

Further, the read synchronizing signal S20 at time t24
The pulse of the actual write synchronization signal S13 overlaps the pulse of the actual write synchronization signal S13, and the synchronization signal coincidence detection circuit 31 changes the signal level of the switching signal S14 to generate a pulse of the actual write synchronization signal S13 at time t25. Therefore, time t2
The received signal D1 written to the digital memory 21 from 4 to time t25 is overwritten from time t25 because the address value of the write address signal AD1 is initialized, and data is lost. there were.

The present invention has been made in view of the above points, and provides a sufficient phase difference between a write synchronizing signal and a read synchronizing signal at the start of reception to prevent occurrence of a read data error due to fluctuation of the received signal. An object of the present invention is to provide a phase control device for preventing such a situation.

[0021]

FIG. 1 is a diagram showing the principle of a phase control apparatus according to the present invention which achieves the above object. In the figure,
The phase control device includes a synchronization signal switching circuit 12, a coincidence signal switching circuit 13, a storage unit 20, a synchronization signal coincidence detection circuit 31, a write enable signal coincidence detection circuit 32, and a write enable signal generation circuit 33.

The storage means 20 temporarily stores the reception signal D1. The synchronization signal switching circuit 12 uses the switching signal S15 to switch between the two write synchronization signals S having a half cycle shift from each other.
One of 12a and S12b is output as actual write synchronization signal S13. Sync signal coincidence detection circuit 31
Detects a match between the actual write synchronization signal S13 and the read synchronization signal S20, and outputs a synchronization match signal S16. The write enable signal generation circuit 33 outputs a write enable signal S21 having a predetermined cycle shift from the read synchronization signal S20. The write permission match detection circuit 32 detects a match between the actual write synchronization signal S13 and the write permission signal S21, and outputs a write permission match signal S17.
Is output. The coincidence signal switching circuit 13 receives the reception state signal S1.
8, the write permission match detection signal S17 is selected at the start of the reception, and the synchronization match signal S
16 and outputs a switching signal S15.

[0023]

At the start of reception, the write permission match detection circuit 32 detects a match between the actual write synchronization signal S13 and the write permission signal S21, and outputs a write permission match signal S17.

At times other than the start of reception, the synchronization signal coincidence detection circuit 31 detects coincidence between the actual write synchronization signal S13 and the read synchronization signal S20, and outputs a synchronization coincidence signal S16. While monitoring the signal state signal S18, the coincidence signal switching circuit 13 selects the write permission coincidence detection signal S17 at the start of reception, and selects the synchronization coincidence signal S16 except at the start of reception, and outputs the switching signal S15. . By the switching signal S15, the synchronization signal switching circuit 12 causes the write synchronization signal S12a,
One of S12b is set to the actual write synchronization signal S13.
Output as

At the start of reception, one of the write synchronization signals S12a and S12b having a predetermined deviation from the read synchronization signal S20 is output as the actual write synchronization signal S13, so that the read synchronization signal S20 and the actual write Provide a sufficient phase difference with the synchronization signal S13.

[0026]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing an embodiment of the phase control device of the present invention. In the figure, a phase control device is a signal receiving unit 1
0, write synchronization signal generation circuit 11, synchronization signal switching circuit 1
2. Consisting of a coincidence signal switching circuit 13, storage means 20, a synchronization signal coincidence detection circuit 31, a write enable signal coincidence detection circuit 32, and a write enable signal generation circuit 33. The storage means 20 includes a digital memory 21, a write address signal counter 22, and a read address signal counter 23.

The signal receiving unit 10 receives a communication signal S10 transmitted through a transmission medium such as a communication cable, detects a synchronization pattern such as a leading pulse of the communication signal S10, and outputs a reception signal D1 and a frame synchronization signal S11. I do.
The write synchronizing signal generating circuit 11 receives the frame synchronizing signal S11 and outputs two write synchronizing signals S12a and S12b which are shifted from each other by a half cycle. Note that the length of one cycle of the two write synchronization signals S12a and S12b is the same as the length of the frame synchronization signal S11.

The synchronization signal switching circuit 12 outputs one of the two write synchronization signals S12a and S12b as an actual write synchronization signal S13 in response to the switching signal S15. The coincidence signal switching circuit 13 monitors the signal state signal S18, and at the start of reception, the write permission coincidence detection signal S17
Is selected, and the synchronization coincidence signal S16 is selected except at the start of reception, and is output as the switching signal S15.

The synchronization signal coincidence detection circuit 31 outputs a synchronization coincidence signal S16 when the actual write synchronization signal S13 matches the read synchronization signal S20. Write enable signal match detection circuit 32
Detects a match between the actual write synchronization signal S13 and the write enable signal S21 and outputs a write enable match signal S17. The write enable signal generation circuit 33 is 1/1/2 of the read synchronization signal S20.
A write enable signal S21 having a four-cycle shift is output. The write enable signal S21 is, for example, a read synchronizing signal S20 and an actual write synchronizing signal S1 when the signal level is high.
3 indicates that it is a safe area where there is room in the timing interval, and the state where the signal level is low indicates that the timing area between the read synchronization signal S20 and the actual write synchronization signal S13 is a prohibited area where there is no room in the timing interval. Signal.

In the storage means 20, the write address signal counter 22 starts counting by the actual write synchronization signal S13 and outputs a write address signal AD1 which is an address for writing the reception signal D1 to the digital memory 21. The write address of the digital memory 21 is sequentially selected by the write address signal AD1, and the received signal D1 is written to the digital memory 21 bit by bit. On the other hand, the read address signal counter 23 starts counting by the read synchronizing signal S20 and outputs the output signal D2.
Is output to the digital memory 21 as a read address signal AD2. The read address of the digital memory 21 is sequentially selected by the read address signal AD2, and the output signal D2 is read from the digital memory 21 bit by bit. The digital memory 21 is a buffer memory composed of a 12-bit parallel memory, temporarily stores the reception signal D1 in synchronization with the write address signal AD1, and stores the read address signal AD
2 to output an output signal D2.

At the start of reception, the signal receiving section 10 outputs a high-level reception state signal S18, and outputs the reception signal D18.
1 becomes abnormal, or when the transmission device having the phase control device is stopped, the low-level reception state signal S1 is output.
8 is output. The coincidence signal switching circuit 13 selects the coincidence detection signal S17 when the signal level is low, and selects and outputs the synchronization coincidence signal S16 when the signal level is high. Furthermore, the synchronization signal switching circuit 12 selects the write synchronization signal S12a when the switching signal S15 is at a low level, and selects the write synchronization signal S12b when the switching signal S15 is at a high level, for example. It is output as a synchronization signal S13.

Next, the operation of the phase control device of the present invention will be described. At the start of reception, that is, at the start of use of the transmission device having the phase control device, the synchronization signal switching circuit 12 outputs the write synchronization signal S12a as the actual write synchronization signal S13. The coincidence signal switching circuit 13 receives the reception state signal S
While monitoring, the write permission match detection signal S17 is output as the switching signal S15. Then, the write permission match detection circuit 32 checks whether or not the actual write synchronization signal S13 output from the synchronization signal switching circuit 12 is in the safe area. Specifically, when the actual write synchronization signal S13 is output, it is checked whether the signal level of the write enable signal S21 is at a high level.

If the signal level of the write enable signal S21 is not at the high level when the actual write synchronization signal S13 is output, the write enable match detecting circuit 32 detects the low level write enable match. The signal S17 is output. The coincidence signal switching circuit 13 outputs the write permission coincidence detection signal S17 as a switching signal S15. Low level switching signal S
15 receives the write synchronization signal S.
12b is output as the actual write synchronization signal S13.

Next, when the actual write synchronization signal S13 is output and the signal level of the write enable signal S21 is at a high level, the write enable match detection circuit 32 outputs a high level write enable match. The detection signal S17 is output. The coincidence signal switching circuit 13 outputs the synchronization coincidence signal S16 based on the write permission coincidence detection signal S17 that changes from low level to high level.
Is output as the switching signal S15.

Thus, the actual write synchronization signal S13 output from the synchronization signal switching circuit 12 is always output in the safe area. Therefore, even when the received signal D1 fluctuates, it is possible to reliably prevent the occurrence of a read data error due to the fluctuation of the received signal D1 within the range of 1/4 period before and after the read synchronizing signal S20.

FIG. 3 is a time chart of signals by the phase control device of the present invention. The same signals as in FIG. 2 are given the same signal names. In the figure, from the top, a reception state signal S18, a read synchronization signal S20, a read address signal AD2, an output signal D2, a reception signal D1, a frame synchronization signal S11, write synchronization signals S12a and S12b, a write enable signal S21, and switching. Signal S15, actual write synchronization signal S1
3. Write address signal AD1 and match signal switching circuit 13
Signals and data contents such as a selection signal of the synchronization coincidence signal S16 or the write permission coincidence detection signal S17 in FIG.

Next, the operation of the phase control device of the present invention will be described based on a time chart. First, at time t1,
The signal receiving section 10 outputs a high-level reception state signal S18 indicating the start of reception. Then, the synchronization signal switching circuit 12
Outputs the write synchronization signal S12a as the actual write synchronization signal S13.

Here, the pulse of the read synchronizing signal S20 rises at time t2 and falls at time t3. The pulse of the actual write synchronization signal S13 rises at time t3.
Therefore, the synchronization signal coincidence detection circuit 31 does not detect the overlap between the pulse of the read synchronization signal S20 and the pulse of the actual write synchronization signal S13.

However, at time t3, when the pulse of the actual write synchronization signal S13 rises, the write enable signal S21
Is a low level. Therefore, the write permission match detection circuit 32 determines that there is no margin in the timing interval between the actual write synchronization signal S13 and the read synchronization signal S20, and the write permission match detection signal S17 which was initially at a high level.
Is switched to low level and output. The coincidence signal switching circuit 13 that has received the write permission coincidence detection signal S17 outputs it as a switching signal S15 as shown by an arrow X1.

In response to the change of the switching signal S15, the synchronization signal switching circuit 12 sets the time t4 as indicated by the arrow X2.
Outputs the write synchronization signal S12b as the actual write synchronization signal S13. At this time, the write address signal counter 22 is reset by the actual write synchronization signal S13, and the address value of the write address signal AD1 is initialized from "6" to "1".

When the next pulse of the actual write synchronization signal S13 rises, the signal level of the write enable signal S21 is at the high level. Therefore, the write permission match detection circuit 32 determines that the actual write synchronization signal S13 has a margin for the timing interval with the read synchronization signal S20, and raises the signal level of the write permission match detection signal S17 from low to high. Switch to level and output. Upon receiving the write permission match detection signal S17, the match signal switching circuit 13 changes the synchronization match signal S16 to the switch signal S16 as shown by the arrow X3.
15 is output. At this time, the synchronization coincidence signal S16 output as the switching signal S15 is at a low level. Therefore, the synchronization signal switching circuit 12 outputs the read synchronization signal S2
The write synchronization signal S12b having a sufficient phase difference from 0 is output as it is as the actual write synchronization signal S13.

Thereafter, the signal level of the selection signal in the coincidence signal switching circuit 13 is changed until the reception state signal S18 becomes low level, that is, until the reception signal D1 becomes abnormal, or the transmission device having the phase control device It is maintained until it stops.

Thus, at the start of reception, the actual write synchronization signal S
13 and the read synchronization signal S20, a sufficient phase difference is provided between the write timing of the reception signal D1 and the output signal D2.
Can be prevented from being coincident with the read timing. That is, the start of counting between the write address signal counter 22 and the read address signal counter 23 is shifted, so that the write address signal AD1 and the read address signal AD2
And the output signal D2 can be correctly read out without overlapping the addresses.

The received signal D1 is stored in the digital memory 2
Since there is a margin between the timing of writing to 1 and the timing of reading the output signal D2 from the digital memory 21, data loss can be reliably prevented even when the received signal D1 fluctuates.

In the above description, the digital memory 21 for inputting / outputting signals according to the write address signal AD1 and the read address signal AD2 is applied to the storage means 20, but according to the actual write synchronization signal S13 and the read synchronization signal S20. Other memories that can input and output signals may be applied.

Although a buffer memory composed of a 12-bit parallel memory is applied to the digital memory 21, other memories such as a 256-bit matrix memory may be applied.

[0047]

As described above, according to the present invention, the coincidence signal switching circuit selects the write enable coincidence signal at the start of reception, and selects the synchronization coincidence signal at other than the start of reception to output the switching signal. Since the synchronization signal switching circuit is configured to output, as the actual write synchronization signal, a write synchronization signal of the two write synchronization signals, which has a margin in the timing between the actual write synchronization signal and the read synchronization signal. A sufficient phase difference can be provided between the actual write synchronizing signal and the read synchronizing signal from the start, and the occurrence of a read data error due to the fluctuation of the received signal can be prevented.

Further, since there is a margin between the timing of writing the received signal to the memory and the timing of reading the output signal from the memory, even if the communication signal and the received signal fluctuate, it is possible to reliably prevent data loss. .

[Brief description of the drawings]

FIG. 1 is a principle diagram of a phase control device of the present invention.

FIG. 2 is a diagram showing an embodiment of the phase control device of the present invention.

FIG. 3 is a time chart of signals by the phase control device of the present invention.

FIG. 4 is a schematic block diagram of a conventional phase control device.

FIG. 5 is a time chart of signals by a conventional phase control device.

FIG. 6 is a time chart when a fluctuation occurs in a received signal.

[Explanation of symbols]

 Reference Signs List 12 synchronization signal switching circuit 13 coincidence signal switching circuit 20 storage means 31 synchronization signal coincidence detection circuit 32 write enable signal coincidence detection circuit 33 write enable signal generation circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 7/00 H04J 3/06

Claims (3)

(57) [Claims] 1. A phase control device for writing a received signal to a storage means in accordance with a write synchronization signal and reading an output signal from the storage means in accordance with a read synchronization signal. A synchronization signal switching circuit that outputs any one of the synchronization signals as an actual write synchronization signal, and detects a match between the actual write synchronization signal and the read synchronization signal;
A synchronizing signal coincidence detecting circuit for outputting a synchronizing signal; a write enable signal generating circuit for outputting a write enable signal having a predetermined cycle deviation from the read synchronizing signal; A write permission match detection circuit that detects a match with the enable signal and outputs a write permission match signal; and selects the write permission match detection signal at the start of reception, and outputs the synchronization match signal except at the start of reception. A coincidence signal switching circuit for selecting and outputting the switching signal; and storage means for writing a reception signal in synchronization with the actual write synchronization signal and reading an output signal in synchronization with the read synchronization signal. Characteristic phase control device. 2. The storage unit includes: a write address signal counter that outputs a write address signal according to the actual write synchronization signal; a read address signal counter that outputs a read address signal according to the read synchronization signal; Writing a reception signal in synchronization with the write address signal;
2. The phase control device according to claim 1, further comprising: a digital memory that reads an output signal in synchronization with the read address signal. 3. The phase control device according to claim 1, wherein the write enable signal generating circuit is configured to output the write enable signal shifted by １ ／ period from the read synchronization signal. .