JPH03255742A - Transmission repeater - Google Patents

Abstract

PURPOSE:To eliminate transmission error by writing the data to be transmitted from a transmission side into a memory with the aid of synchronization of a transmission side clock, reading the data of the memory in parallel with the write operation with the aid of synchronization of a reception side clock, and sending out the data to the reception side. CONSTITUTION:Between a transmission side equipment 1 and a reception side equipment 2 to execute synchronous data transmission, a memory 5 is interposed so that the write operation and read operation of the data can be respectively independently executed, and the data SD to be sent out from the transmission side is written into the memory 5 and made tentatively resident there with the aid of synchronization of a transmission side clock ST. On the other hand, the data SD tentatively stagnated in the memory 5 is read out in parallel with the write operation while synchronizing a reception side clock RT and sent out to the reception side as reception side data RD. Therefore, the disturbance of synchronization of the transmission timing and reception timing of the data is relaxed by providing the time for making the data in transmission resident in the memory 5.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a transmission relay device used for synchronous data transmission.

Conventional technology synchronous data transmission, for example, as shown in FIG. This is performed by synchronizing the reception operation of the data RD in the side device 2 with the clocks ST and RT, respectively, and by providing a certain synchronization relationship between the transmitting side clock ST and the receiving side clock RT. Data transmission is performed 7 real times, one pit at a time, in synchronization with the clock. If the tarokk ST and RD on the transmitting side and the receiving side can maintain a perfect synchronization relationship, the transmitting side data SD and the receiving side data RD will completely match.

Problems to be Solved by the Invention However, with this configuration, there is a problem in that transmission errors such as data dropouts may occur.

The above problem arises for the following reasons.

That is, the transmitting side clock ST and the receiving side clock RT
are controlled to have a certain synchronization relationship in order to perform synchronous data transmission, but due to fluctuations in line conditions, transient phase fluctuations, so-called so-called phase fluctuations, may occur in the transmitting side clock ST or receiving side clock RT. Jitter may occur.

The inventors have found that this jitter causes the above problem.

For example, as shown in FIG. 4, when jitter occurs in the transmitter clock ST or the receiver clock RT, the data transmission timing or reception timing is locally disturbed, resulting in double received data (D3) or Data (D4) that is not processed is generated.

The present invention has been made in view of the above-mentioned problems, and is a transmission relay that enables transmission without causing errors such as data dropout even if jitter occurs in the clock used to perform synchronous data transmission. The purpose is to provide equipment.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a system in which data writing and reading operations are performed independently between a transmitting side device and a receiving side device that perform synchronous data transmission. The data sent from the transmitting side is written to the memory and temporarily resides therein under the synchronization of the transmitting side's clock, and the data temporarily resides in the memory in parallel with the writing operation. The data is read out in synchronization with the receiving side clock and sent to the receiving side.

According to the present invention, with the above-described configuration, synchronization disturbances between the data transmission timing and the reception timing are buffered by expansion and contraction of the residence time of the data being transmitted in the memory, so that it is possible to perform synchronous data transmission. Even if jitter occurs in the taro clock, it is possible to perform transmission without causing errors such as data dropouts.

Example Embodiments of the present invention will be described below based on the drawings.

FIG. 1 shows a schematic configuration of a transmission relay device according to an embodiment of the present invention, in which 1 indicates data SD and clock ST.
2 is a receiving device that receives data RD in synchronization with clock RT; 3 is a line switching device that connects transmitting device 1 and receiving device 2; 4 is a transmitting device This is a transmission relay device interposed between the device 1 and the receiving device 20.

Here, the transmission relay device 4 includes a memory 5, a write address counter 6, a read address counter 7, an inverter 8 as an address conversion circuit, and the like.

The memory 5 used has a small capacity of only 8 bits. This 8-bit memory 5 is a dual-port memory in which data writing and reading operations are performed independently, and is located between a transmitting device 1 and a receiving device 2 that perform synchronous data transmission. being mediated. Data SD, which is also sent from the sending device 1, is input to the write input Din of the memory 5. Further, the data RD output from the readout output Dout of this memory 5 is sent to the receiving side device 2.

The write address counter 6 is constituted by a cyclic three-pin counter that returns to the original state after counting and amplifying. This write address counter 6 is a clock S on the sending side.
By counting T, the write address (A2.AI.

AO) is generated.

Like the write address counter 6, the read address counter 7 is constituted by a cyclic 3-bit counter that returns to the original value after counting up.

This read address counter 7 is connected to the clock RT on the receiving side.
By counting , the read address (A2.AI, AO) of the memory 5 is generated.

The inverter 8 as an address conversion circuit creates an offset of 4 addresses between the read address and the write address of the memory 5 by logically inverting the read address (the most significant pinot of A2, AI, AO) A2. to have. The write address that has been completely designated by the write address counter 6 is designated as the read address after a delay of four clock cycles.

The operation of the transmission relay device configured as described above will be described below.

FIG. 2 shows the operational concept of the transmission relay device shown in FIG. 1.

In FIGS. 1 and 2, data SD (..., D5. D6. D7° D8.
D9) is written into the memory 5 one bit at a time in synchronization with the sending clock ST.

The memory 5 stores the latest 8 bits of data (D2. D3°D4.
D5. D6. D7. D8. D9) will always stay there.

On the other hand, in parallel with the above-mentioned write operation, the data written to the memory 5 and temporarily stored is stored in synchronization with the receiving side clock RT from the address that is four addresses back from the address being written. Read out sequentially. In other words, 4
Data written a clock cycle ago is read out sequentially. The read data RD (..., Dl,...
D2. D3. D4. D5) are sequentially sent to the receiving device 2.

As described above, the operation of writing the data sent from the sending device 1 to the memory 5 and the operation of reading the data written to the memory 5 and sending it to the receiving device 2 are performed independently. Data is transmitted from the sending side to the receiving side while the data is being transmitted.

As a result, even if jitter occurs in the transmitting side clock ST or the receiving side clock RT and the synchronization relationship between the data transmission timing and the reception timing is locally disturbed, this disturbance will be caused by the residence time of the data being transmitted in the memory 5. becomes buffered by expanding and contracting.

Therefore, even if jitter occurs in the clocks ST and RT for performing synchronous data transmission, it is possible to perform transmission without causing errors such as data omission.

In the embodiment described above, the offset between the write address and the read address is set to four addresses, but this can be increased or decreased depending on the degree of jitter. If the amount of jitter is expected to be small, the offset can be made smaller. On the other hand, if the amount of jitter is expected to be large, it can be dealt with by increasing the offset.

Effects of the Invention As is clear from the above description, the present invention provides a memory in which data writing and reading operations are performed independently between a sending device and a receiving device that perform synchronous data transmission. The data sent from the sending side is written into the memory and temporarily stored therein under the synchronization of the sending side clock, while the data temporarily stored in the memory is written in parallel with the write operation. 1 by reading it out in synchronization with the receiving side clock and sending it to the receiving side.
Synchronization disturbances between the data transmission timing and reception timing are buffered by the expansion and contraction of the residence time of data during transmission in memory, so even if jitter occurs in the clock used to perform synchronous data transmission, data loss will occur. This has the advantage of being able to perform transmission without causing errors such as.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of a transmission relay device according to an embodiment of the present invention, FIG. 2 is a diagram showing the operational concept of the device, and FIG. 3 is a schematic configuration diagram of a system in which synchronous data transmission is performed. FIG. 4 is a time chart showing problems in synchronous data transmission. 1... Sending side device, 2... Receiving side device, 3... Line switching device, 4. Transmission relay device, 5... Memory 6.
...Write address counter, 7...Read address counter, 8...Inverter, SD...Sending side data,
ST: transmitting side clock, RD: receiving side data,
RT: Receiving side clock.

Claims (1)

[Claims] A memory in which data write and read operations are performed independently, and data sent from the sending side is written to the memory in synchronization with the sending side clock, and the data temporarily stored is transferred to the receiving side clock. A transmission relay device comprising circuit means for reading the data under synchronization and transmitting it to the receiving side.