JPS5915582B2 - Digital phase synchronization method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital phase synchronization system, and more particularly, to synchronization of bit phase and frame phase in terminal equipment in a digital synchronization network that operates with a unified clock, that is, a clock of the same frequency. It is something.

An example of the configuration of a conventional digital phase synchronization method is shown in FIG.

In this method, bit phase synchronization and frame phase synchronization are performed using dedicated circuits, respectively. That is, in FIG. 1, ES is an elastic store, TIM is a timing extraction circuit, EWA is an elastic store write address circuit 15, ERA is an elastic store read address circuit, PHC is a phase control circuit, FM is a frame memory, FSYNC is a frame synchronization circuit, FWA is a frame memory write address circuit, Tll is a data signal input terminal, T,2 is a data signal output terminal, 20T13 is a frame memory read address signal input terminal, and T14 is a local bit clock input terminal. , First, the timing extraction circuit TIM extracts the timing clock from the input data, and sends the clock to the write address circuit EWA.
Elastics 25 Determine the write address of the door ES. Input data is sequentially written into the elastic store ES according to this address. On the other hand, data is sequentially read out from the local bit clock according to the read address generated by the read address circuit ERA. The 30-phase control circuit PHC monitors the phases of the write address signal and the read address signal, and controls the write address signal so that overflow or underflow of the elastic store ES does not occur depending on the phase relationship. The data signal whose bit phase has been synchronized with the station bit clock through the above process is then transferred to the frame synchronization circuit F.
Frame synchronization is performed with SYNC. When this frame is synchronized, data is sequentially written from the local bit clock to the frame memory FM in accordance with the write address generated by the frame memory write address circuit FWA.

Thereafter, frame phase synchronization is achieved by sequentially reading data in accordance with a frame memory read address signal based on a frame signal within the station. Note that a random access memory (RAM) having a capacity for one frame is normally used as the frame memory FM. Second
The figure also shows a conventionally used digital phase synchronization method, which does not perform bit phase synchronization and frame phase synchronization with dedicated circuit configurations, as in the method shown in FIG. , this method requires a frame memory capacity of two frames.
That is, in FIG. 2, TIM is a timing extraction circuit;
FSYNC is a frame synchronization circuit, FWA is a frame memory write address circuit, FM is a frame memory, PHC
is a phase control circuit, T2l is a data signal input terminal, T22
is a data signal output terminal, and T23 is a frame memory read address signal input terminal. In this method, first, a timing clock is extracted from input data by a timing extraction circuit TIM, and the input data is extracted by a frame synchronization circuit FSYNC. Frame synchronization is established, and when frame synchronization is established, the frame memory write address circuit FWA
A write address is determined, and input data is written to the frame memory FM in accordance with the write address. On the other hand, data is sequentially read out using a frame memory read address signal based on the station frame signal. This phase control circuit PH
C controls writing to the frame memory FM based on the phase relationship between the write address signal and the read address signal of the frame memory FM. Therefore, the frame memory FM is composed of two memories each having a capacity for one frame, and when one is writing, the other is reading, thereby achieving phase synchronization. As described above, in the conventional method shown in FIG. 1 for establishing bit phase synchronization and frame phase synchronization, the control related circuits EWA, ERA, PHC of the elastic store ES
A control-related circuit FWA for the frame memory FM is required in terms of the system configuration, and the system shown in FIG. 2 has drawbacks such as the capacity of the frame memory FM for two frames. When a random access memory is used as the frame memory FM in the systems shown in FIGS. 1 and 2, one of the drawbacks of this system is that it is difficult to find a fault in the random access memory. The present invention is characterized in that, in a digital phase synchronization method, the functions of the elastic store ES and frame memory FM as described above are replaced with FlFO memory, thereby solving the drawbacks of the conventional method.

Embodiments of the present invention will be described below with reference to the drawings. 3 and 4 relate to a first embodiment of the present invention, in which a FIFO memory is used as a serial input/output buffer. Incidentally, the FIFO memory is a well-known one, but since it is a structural element of the present invention, an outline of its operation will be described below. In other words, FIFO memory is functionally a type of multi-stage serially connected register, and when the memory status is write enabled, input data is stored in the memory bit by bit using the write clock, but the input data is input first in the storage order. The stored data is written to the cell closest to the output, that is, the final cell, and thereafter stored sequentially from the final cell toward the input section. Furthermore, if even one bit is stored, a read-enabled status is output, and the data is read out bit by bit from the output section of the memory using the read clock. Immediately after one bit is read out, the contents of the cells in each stage are shifted by one bit in the output direction.

Here, if there is no frequency deviation between the write clock and the read clock, the memory will not always overflow or underflow, but if the frequency of the write clock is higher than the read clock, the memory will flow from the output side to the input side. The cells are filling up. In this state, when the frequency of the read clock becomes higher than the write clock, the memory cells become empty from the input side to the output side. As explained above, the FIFO memory is a memory characterized by being able to perform writing and reading independently, and is available as a commercial product. In FIG. 3, TIM is a timing extraction circuit, FSYNC is a frame synchronization circuit,
FIFO is FIFOl Memo 18 RCNT is a read control circuit, FF is a flip-flop circuit, G is an inhibit gate circuit, T3l is a data signal input terminal, T32 is a data signal output terminal, T33 is a station clock input terminal, T34 is a station frame signal input 42 in FIG. 4 is a received data signal, 433 is a write enable signal output from the frame synchronization circuit FSYNC, 43 is a write clock, 44 is a read enable signal, and 45 is a station signal indicating the frame position of the internal signal. The frame signal, 466 is the station clock, 46 is the read clock, 47 is the read data, and the numbers 1, 2, etc. attached to the received data signal 42 represent each bit of the received data signal, and the read data 47 Each number 1, 2...
・corresponds to In addition, the numbers shown in Figure 3 (42,
43...) correspond to each signal in FIG. Hereinafter, for the convenience of explaining the operation, it is assumed here that all contents of the FIFO memory have been reset (all internal memory cells are in a clear state).

It is also assumed that the flip-flop circuit FF is in the set state. First, the received data signal 42 input from the data signal input terminal T3 is sent to the timing extraction circuit TIM.
After the timing is extracted by the frame synchronization circuit FS using this extraction clock (synonymous with the write clock 43).
Frame synchronization is performed on YNC.

That is, the beginning position (1) of the frame of the received data signal 42
) is determined. Frame same. When synchronization is performed, a write enable signal 4 is sent from the frame synchronization circuit FSYNC.
33 is sent to the FIFO memory and read control circuit RCNT.

In FIFO memory. Upon receiving this, cancel the set,
The received data signals 42 are sequentially written into the FlFO memory in a bit-serial manner using a write clock 43 used in the timing extraction circuit TIM. That is, the data are written into the FIFO memory in the order of numbers 1, 2, . . . shown in FIG. 442. On the other hand, when the read control circuit RCNT receives the write enable signal 433, it sends the read enable signal 44 to the reset terminal R of the flip-flop circuit FF after a certain time t to release the forced set state of the flip-flop circuit.

However, in this state. Still flip-flop circuit FF
Since no signal is input to the set terminal S, the output Q of is held in the reset state. By the way, the above-mentioned time t
is the time required to ensure that more than a certain number of bits are written in advance to the FIFO memory in order to prevent underflow when reading from the FIFO memory.
This has the effect of absorbing the second transmission path delay fluctuation.

All operations up to this point are performed asynchronously with the station clock.

That is, they all operate using the reception timing clock. next,
The process of reading the received data stored in the above-mentioned FIFO memory will be described.

As mentioned above, the flip-flop circuit FF has received the read enable signal 44 and is in the set release state, but in this state, a frame signal is sent from the station equipment (not shown) at regular intervals via the station frame signal input terminal T34. When the incoming station frame signal 45 is received at the set terminal S, that is, when the first station frame signal 45 after release is received, the flip-flop circuit FF is set and the output Q becomes set. When the output terminal Q of the flip-flop circuit FF enters the set state, the inhibited state of the inhibit gate circuit G is released, and the station clock 466 is switched to the FIF as the read clock 46.
Sent to O memory. This readout clock 46 causes F
Data is read out bit-by-bit serially from the IFO memory one after another.

FIG. 4 47 shows this state, and read data 47 is read out in the order of numbers 1, 2, . . . . However, since data 1 immediately appears at the output terminal T32 when it is written into the FIFO memory, it should be noted that in FIG. 47, the length of data 1 is shown to be longer than the data 2 and subsequent data. This readout process is all performed using the station's frame signal 45 and the station's read clock 46, so that the received data signal 42 is simultaneously synchronized to the station's frame phase and bit phase. Also, the received data signal 4
If synchronization occurs in step 2, frame synchronization circuit FS
YNC to FIFO memory and read control circuit RCN
The write enable signal sent to T is no longer sent. As a result, the FIFO memory is reset, the read enable signal 44 from the read control circuit RCNT disappears, and the flip-flop circuit FF is also forced to be fixed in the set state. and bit phase synchronization is performed. Note that the memory capacity required to prevent overflow and underflow of the FIFO memory from occurring is "capacity for one frame + capacity necessary to absorb transmission line delay."

The capacity required to absorb transmission line delay is an amount determined depending on the characteristics of a transmission medium (cable, etc.) through which data is transmitted. In the case of the circuit configuration explained above, the reliability of the memory part in particular is a big problem, but
Since FIFO memory uses IFO memory, the input data passes through all internal memory cells serially and is output, so by inserting a monitoring signal into the input data and monitoring it on the output side, it is easy to Memory failures can be discovered. As explained above, in the first embodiment, compared to the conventional digital phase synchronization method, the peripheral control circuit of the memory is greatly simplified, and a great effect can be obtained from the mounting of the components constituting the method. In addition, the memory capacity for two frames is not required (provided that the capacity for absorbing transmission path delay fluctuations is smaller than the capacity for one frame), and the memory can be easily monitored for all bits. This has significant advantages over using access memory. Next, a second embodiment of the present invention will be described. FIG. 5 is a block diagram showing the configuration of the second embodiment, and FIG. 6 is a time chart thereof. In FIG. 5, TIM is a timing extraction circuit, FSYNC is a frame synchronization circuit, CONV is a serial/parallel conversion circuit, WPG is a write clock generation circuit, FIFO is an n-word x m-bit FLFO memory, RCNT is a read control circuit, and FF is a flip-flop circuit, G is an inhibition gate circuit, T and l are data signal input terminals, T52 is a data signal output terminal, T
53 is a station clock input terminal, and T54 is a station frame signal input terminal. Further, in FIG. 6, 61 is a received frame signal, 62 is a received data signal, 633 is a write enable signal, and 6
3 is a write clock, 64 is a read enable signal, 65 is a station frame signal, 666 is a station clock, 66 is a read clock, and 67 is read data. In addition, the received data 62
The numerals 1, 2, . . . attached to the read data 67 indicate the numbers of time slots (hereinafter referred to as time slots) in which m consecutive bits are one unit, and the same applies to the numbers attached to the read data 67. Further, the symbols 1, 2, . . . attached to the write clock 63 and the read clock 66 mean clock numbers corresponding to the above-mentioned time slot numbers.
The operation will be explained below. The received data signal 62 input from the data signal input terminal T5l is subjected to timing extraction by the timing extraction circuit TIM, and then is extracted by the frame synchronization circuit F.
Frame synchronization is performed with SYNC.

That is, the position of the frame signal of the received data signal 62 is determined. FIG. 6 61 shows the time position of this received frame signal 62. When frame synchronization is established, the write clock generation circuit WP is output from the frame synchronization circuit FSYNC.
A write enable signal 633 is sent to G and the read control circuit PCNT. Based on this, the write clock generation circuit WPG generates a write clock 63 once every m bits. The received data signal 62 is converted into a parallel signal in units of m bits by a serial/parallel conversion circuit CONV, and m bits are simultaneously written into the memory FIFO by a write clock 63. This write clock 63 is a write clock generating circuit WPG.
is generated from the received timing clock. In this way, in m bit units, one by one as shown in FIG.
, 2, etc., but when time t has elapsed since the first write, a read enable signal 64 is sent from the read control circuit RCNT to the reset terminal R of the flip-flop circuit FF. Sent. This time t is a time set in advance to absorb transmission path delay fluctuations. All operations up to this point are asynchronous with the station's clock, but next. The process of synchronizing with the station's clock will be described. First, when the above-mentioned read enable signal 64 is sent out, thereafter, based on the station frame signal 65 that appears first, data is transferred from the memory FIFO to the parallel m bits as shown in FIG.
, 67, the data is read out one after another in the order of 1, 2, . By the above operations, the received data is synchronized with the frame phase and bit phase of the station. If synchronization occurs in the received data signal 62, the memory FIFO is set once again, and then the bit phase and frame phase are synchronized again through the series of operations from frame synchronization described above. Let's do it. Note that the memory capacity (n words, Xm bits) required for the memory FIFO is the capacity necessary to absorb transmission line delay fluctuations for one frame. In this embodiment, since the received data signal 62 is processed in parallel, the memory FIFO read and write clocks are one compared to the first embodiment, allowing more time for memory FIFO read and write processing.

During this margin time, a memory monitoring signal independent from the received data signal 62 can be input in parallel to the memory FIFO in units of m bits, and the memory monitoring signal is included in the transmitted signal as in the first embodiment. Since there is no need to insert a The [phase] clocks shown in FIGS. 63 and 66 are the above-mentioned supervisory signal writing and reading clocks, and the parallel bit supervisory signals are input to and output from the memory FIFO by this clock. The present invention configures a digital phase synchronization method using FIFO memory, and performs bit phase synchronization and frame phase synchronization at the same time, so it is more economical than conventional methods in terms of the required parts for the configuration of the digital phase synchronization method. It has the advantage that the memory monitoring function, which was a problem with the conventional method, can be easily added because it uses FIFO memory, so it can be used for the input section of terminal equipment in a digital network that operates on a unified clock. can do.

Claims (1)

[Claims] 1. A circuit that extracts a timing clock from a digital signal received via a transmission path, a circuit that synchronizes the frame of the received signal, a FIFO memory that stores the received signal, and generates a read permission timing signal for the FIFO memory. A frame phase synchronization circuit, which is composed of a read control circuit that controls the readout, a flip-flop circuit that is controlled by the read permission timing signal and the station frame signal, and an inhibition gate that prohibits the passage of the station clock, transfers the received data signal to the FIFO memory. , the reference timing for starting writing is aligned with the phase of the received frame, and sequential writing is performed using a timing clock extracted from the received data signal, while the reference timing for starting reading is aligned with the internal frame phase, and reading is sequentially performed from the FIFO memory using the local clock. A digital phase synchronization method characterized in that the FIFO memory and the flip-flop circuit are reset when frame synchronization is lost.