IE42267B1 - A device for synchoronizing a binary data train with anothher such train - Google Patents

Abstract

1503412 Frame synchronizing COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS CIT ALCATEL 4 Feb 1976 [5 Feb 1975] 4429/76 Heading H4M To synchronize the framing of a pulse train at 6 {from transmission channel 5} with that of a synchronous or plesiochronous train at 2 {from channel 1}, the former train being read into series to parallel shift register 9, at the incoming bit rate R supplied at point 7, the register 9 storing q {q>1} bits, the bits being parallel read, q bits at a time, at the rate R/q into first-in-first-out memory 8, the train being correspondingly handled in parallel to series register 11, to be read out via shift register 17 at a clock rate equal to that of the train at 2, the bits in register 17 and the bit at 16 are compared, as a word, in unit 18, with a predetermined frame locking word so that, when the latter word is detected, read-out of the storage means is inhibited until the beginning of the next frame of the train at 2, at which time read-out is re-established with the trains in frame synchonism, the train read out coming from the serial output of register 17 and passing via gate 20, enabled when the frame locking word has been detected in two successive frames, as well as a particular bit on line 22 half a frame after the first detected frame locking word and when the beginning of frame signal on line 4 relating to the train at 2 is detected. Gate 20 remains open unless there are three successive failures to detect a frame locking word at the expected epoch. The storage means can store one frame of data. Pulse trains so synchronized may be checked for identity, or bits from one train may be distributed from one train into the other. Data read into the first-in-first-out store is internally transferred at a high data rate to form an ordered stack in the locations closest to the output.

Description

The invention relates to a device for synchronizing one binary data train with another, the two trains having quasisynchronous bit frequencies and being subdivided by locking words into frames having identical lengths. Such a device is often called a frame synchronizing device and it is applicable more particularly to PCM digital transmission (pulse code modulation).

In a PCM transmission, a binary data train is divided into frames having a certain length and in which certain 10 positions are marked by a particular combination of binary data (bits). This combination of bits is called the locking word and its bit positions are not available for transmitting useful data.

With a view to processing the data contained in a succes15 sion of frames, an attempt is often made to synchronize one train in relation to another, for example when it is required to check the identity of the two trains, or when it is required to distribute certain parts of one train to corresponding positions in another train. This frame synchronization has, until now, been effected by means of a memory in which the bits of a train have been written in successive cells. The bits are extracted from that memory by means of a control device which sends out the addresses of the cells to be read as a function of the time difference between the two beginnings of frames in the two trains.

Preferred embodiments of the present invention require a control device that is more simple; this is particularly l ‘ appreciated when it is necessary to take into consideration, when decoding the frame locking word, errors in transmission and the standardized requirements concerning loss and recovery of locking.

According to the present invention there is provided a device for frame synchronizing a first series binary data train with a second series binary data train, both trains having practically identical bit rates and being subdivided by predetermined frame locking words into frames of identical lengths, the device comprising: a series/parallel transformation circuit connected to cut the said first train into sections q bits long (where q is an integer greater than unity); a first in, first out (FIFO) memory having q bits per cell connected to receive the said sections at a rate of 1/q times the instantaneous bit rate of the said first data train; a parallel/series transformation circuit connected to receive the said sections from the FIFO memory at a rate of 1/q times the instantaneous bit rate of the said second data train and to deliver a series data train at the instantaneous bit rate of the said second data train; frame locking word detection means responsive to the output of the FIFO memory and a logic control circuit responsive to the frame locking word detection means and to the said second data train to interrupt data output from the FIFO memory and the flow of data thereafter from the instant a frame locking word from the said first train is satisfactorily detected until a frame locking word is also detected in said second data train, the said first train then being clocked out of the device in frame synchronism with the said second train.

The essential particularity of a memory of the SILO or I FIFO (First-in — First out) type is that its data input control is independent from its output control. Once they are inserted in the memory, the bits are conveyed at an internal rate which is independent from both the input and the output rates. The internal rate is greater tlHn the data insertion rate. The first bit which enters such a memory therefore passes therethrough very rapidly and is memorized at the location nearest to the output, the following bits being stacked behind. As soon as the first bit is extracted by an outside reading order for that memory, the stack of the remaining bits shifts by one place and the second bit then occupies the first location.

Preferably, the locking word detector is fed by a shift register whose capacity corresponds to the size of the locking word and which receives the series train leaving the said parallel/series transformation circuit.

The invention will be described hereinbelow in greater detail with reference to a figure which shows diagrammatically a preferred embodiment of the invention.

With reference to that figure, a transmission channel for a first binary train A has been symbolically shown by a box 1, whose output 2 delivers the said train. This channel also delivers a clock pulse train on an output 3 at the rate at which the bits pass through the channel. A binary signal, which shows the beginning of a frame in the train A is available on an output 4.

Another train B, which is delivered to a terminal 6 by another channel 5, is to be frame synchronised to the train A. Another terminal 7 of the channel 5 delivers clock pulses at the rate of that channel 5.

If no data is to be lost once synchronisation has been achieved, it is essential for the long term average of the two clock pulse rates to be identical, although their phase relationship, as well as the time difference between the two beginnings of frames are random and a certain amount of short term jitter between the two rates can be tolerated.

An essential element of the device is constituted by a memory 8 of the FIFO type having in each cell four bits in parallel. The terminal 6 of the channel 5 feeds the memory 8 via a four-bit series/parallel transformation circuit 9, which is constituted by a shift register 9. The shifting is effected at the rate of the train B and the writing of the data into the memory 8 is controlled at a rate which is derived from the original rate by means of a binary divideby-four divider lo.

The capacity of the FIFO memory is a function of the maximum difference which can be tolerated between the two trains. In general, that maximum difference is one complete frame.

Another transformation circuit 11 is provided at the output of the FIFO memory 8 and receives four bits in parallel from the memory 8 when a control input 12 receives a pulse.

The parallel/series transformation circuit 11 is again constituted by a shift register whose shift rate is four times greater than the reading rate of the memory 8. For that purpose, another divide-by-four divider 13 is provided between the control input 12 of the memory and a shift control input 14. As will be seen hereinbelow, the input 14 receives pulses at the rate of the train A, except when a frame locking word has been discovered and when, at the same time, the two trains are considered as non-synchronized.

This conditioned pulse train is generated in a logic control unit 15, which will be explained hereinbelow.

The bits leaving through a terminal 16 of the parallel/ series transformation circuit 11 are applied subsequently to a shift register 17, whose shift speed is identical to the rate of the train A. That shift register comprises six bistable elements, whose outputs are connected to the inputs of a frame locking word decoder 18. The decoder 18 is also connected to the terminal 16 to receive a seventh bit in addition to the six bits it receives from the shift register 17.

In the example chosen, the frame locking word comprises seven bits having a well-determined configuration. When such a word enters the register 17 (with the seventh bit being maintained at its input 16 by the converter 11), the 4226? decoder observes a coincidence with the predetermined configuration and delivers a binary signal indicating the presence of such a word via an output 19, The output 19 is connected to an input of the logic control unit 15.

Two other inputs of the logic unit 15 are connected to the outputs 3 and 4 respectively of the box 1.

; The logic control unit controls, in the last instance, a gate 20 which is situated between the output of the register 17 and an output 21 of the device. The train B in synchronism with the train A is available on the output 21 as will be seen after the following explanation of the operation of the device.

The train B is cut up by the divider 10 andthe circuit 9 into groups of four bits. The cutting up is effected in a manner unrelated to the beginning of a frame. The groups are stored one after another in the memory 8, At the time of the search for locking, the logic control unit 15 supplies the terminal 14 with a regular train of pulses at the frequency of the train A. Consequently, the groups which have been written in the memory 8 leave successively via the circuit 11 and pass through the register 17. The gate 20 is blocked during the search for locking.

At each shift instant, the decoder 18 checks the combination of the bits and it sends out a signal to the control logic unit 15 on the discovery of a locking word. The logic control unit 15 then checks the presence of standard -ized criteria for effecting the locking. The locking will be considered as effected when the following criteria have been observed successively. 422 6 7 The presence of the locking word on the line 19, for the first time; The presence of a particular bit on the line 22, half a frame later.; The presence of the locking word on the line 19, for the second time, .half a frame later still.

The logic control unit 15 comprises, for the checking of these criteria, counters and logic gates (not shown) and sends out an output permission signal to the gate 20 when these criteria are fulfilled and when the channel A indicates the beginning of a frame via its output 4 to the logic control unit 15. The train B therefore leaves through the terminal 21, beginning by the frame locking word in synchronism with a frame locking word on the terminal 2 of the channel A. The gate 20 remains open until a loss of locking is discovered in the logic control unit. According to further standardized criteria, the frame locking is considered as lost if the device detects three consecutive erroneous locking words.

The change of the loss of frame locking state causes the closing of the gate 20 and a further search for looking. It should be observed that the terminal 14 at the input of the parallel/series transformation circuit 11 receives a pulse train regularly at the rate of the train A, except in the interval between the discovery of a second locking word in the train B according to the standardized criteria and the beginning of the next frame in the train A. During that interval, the reading of the memory 8, the parallel/series transformation and the shifting of the register 17 are - 8 42267 blocked.

The device according to the invention is not limited I to the example described hereinabove. The device can also be adapted to requirements and standards (criteria) other than those mentioned hereinabove. The invention may be applied to PCM digital terminals having thirty telephone channels. They enable the transfer of certain parts of a PCM frame into a synchronous frame of another train. The device according to the invention could even be considered for use when the frames are nominally synchronous, that is, when they come from different clocks, having identical nominal average frequency but being able to vary within the specified limits. In view of the fact that a whole frame is stored in the memory, such limits can be fairly wide without there being any danger of loss of data.

Claims (3)

1. A device for frame synchronising a first series binary data train with a second series binary data train, both trains having practically identical bit rates and being subdivided by predetermined frame locking words into frames of identical lengths, the device comprising; a series/parallel transformation circuit connected to cut the said first train into sections bits long (where q is an integer greater than unity); a first in, first out (FIFO) memory having q bits per cell connected to receive the said sections at a rate of 1/g times the instantaneous bit rate of the said first data train; a parallel/series transformation circuit connected to receive the said sections from the FIFO memory at a rate of 1/q times the instantaneous bit rate of the said second data train and to deliver a series data train at the instantaneous bit rate of the said second data train; frame locking word detection means responsive to the output of the FIFO memory and a logic control circuit responsive to the frame locking word detection means and to the said second data train to interrupt data output from the FIFO memory and the flow of data thereafter from the instant a frame locking word from the said first train is satisfactorily detected until a frame locking word is also detected in said second data train, the said first train then being clocked out of the device in frame synchronism with the said second train.

2. A device as claimed in Claim 1, wherein the frame locking word detection means is fed by a shift register whose capacity corresponds to the size of the locking word 10 4226 7 and which receives the series train leaving said parallel/ series transformation circuit.

3. A device for synchronizing one binary data series train with another such train substantially as herein 5 described with reference to the accompanying drawing.