JPS59126352A - Data highway device - Google Patents

Abstract

PURPOSE:To prevent duplication or missing of data from being produced even when the transmission delay time of a loop is equal to integral multiple times of frame length by providing additionally a circuit comparing write and read timings of an elastic memory and a circuit delaying the writing data to a loop delay compensating circuit. CONSTITUTION:It is supposed that a detecting circuit 14 detects entering of a read clock CLK2 of a transmission frame into the significant level range of a clock CLK3. Then, the detecting circuit 14 inverts the state of a write input switching circuit 15. As a result, a delay circuit 13 is controlled so as to be inserted or removed. Thus, a write timing CLK1 to the elastic memory 10 at each frame of receiving data is delayed or quikened by a fixed delay time of the delay circuit 13. After the transmission delay time of a loop is controlled once, when the fluctuating width of the loop transmission delay time does not exceeds the width of the fixed delay time in this way, the device operates stably without competition between the transmission and reception timings again.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data network device that transmits data using time slots on a transmission path connected in a loop.

Conventionally, in this type of data transmission system, in order to ensure continuity of frames on the transmission path, the loop synchronization control station that controls loop synchronization corrects the transmission delay time that occurs on the transmission path and each terminal station, and corrects the fluctuations. need to be absorbed.

Therefore, in the loop synchronous control station, received data is written into the elastic memory once for each frame, and the received data, which has been written to the appropriate size, is read out from the elastic memory at the transmission timing and then sent to the transmission path. However, if the transmission delay time of the loop is equal to an integral multiple of the frame length of the transmission path, the write timing and read timing of the elastic memory will be equal, and furthermore, due to fluctuations in the transmission delay time, the write timing and read timing will be moved back and forth. Therefore, there is a drawback that frame duplication and deletion occur.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data highway device that eliminates the above-mentioned conventional drawbacks and eliminates frame duplication and loss due to variations in transmission delay time even when the loop transmission delay time is equal to an integral multiple of the frame length. It's about doing.

According to the present invention, in a data network device that connects a plurality of stations through a loop-shaped transmission path to transmit data, a circuit temporarily stores received data in a loop synchronization control station that controls loop synchronization.

There is obtained a data transfer device characterized by comprising a circuit that compares write timing and read timing of the storage circuit, and a circuit that delays the received data based on the comparison result.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a system configuration diagram of the datano-iway device. Here, 1 is a loop synchronous control station, 2 to 4 are terminal stations, 5 is a loop-shaped transmission path, and 6 to 9 are terminal devices.

FIG. 2 is a block diagram showing the configuration of a loop delay correction circuit of a conventional loop synchronous control station. In FIG. 2, data received from the transmission line 5 is written into the elastic memory 10 frame by frame at the timing when the timing circuit 12 reproduces the data.

The data is read from the elastic memory 10 and output at the transmission timing generated by the timing circuit 11.

3 and 4 are diagrams showing the operation of the conventional loop delay correction circuit shown in FIG. 2. In FIG. 3, a is the transmission delay time of the loop 5, and the received data is written to the elastic memory 10 at the timing of CLK 1 for each frame. Next, CLK 2 synchronized with the transmission timing
It is read out from the elastic 10 at the timing of .

If the loop transmission delay time is approximately equal to an integral multiple of the frame length, as shown in FIG. 4b, the write timing CLK 1 and the read timing CLK 2 are close to each other. Now, if the transmission delay time becomes slightly larger than the frame length, the read frame will be delayed by one frame, and the number of frames on the transmission path will decrease by one. Thereafter, the transmission delay time becomes slightly smaller than the frame length, and the read frame is one frame earlier, so the number of frames on the transmission path increases by one. In this way, when the transmission delay time fluctuates, the number of frames increases or decreases, resulting in data duplication.

Deficiency occurs.

FIG. 5 shows an embodiment of the loop delay correction circuit according to the present invention. The difference from the conventional loop delay correction circuit is that the loop delay correction circuit shown in FIG. 2 includes a detection circuit 14 that compares write timing and read timing, and a delay circuit 13 that delays received data. This is because a switching circuit 15 is added.

As shown in FIG. 6, in the detection circuit 14, when the clock CLK 3 is in the significant level range near the write timing CLK 1 of the received data frame,
Assume that it is detected that the transmission frame read clock CLK2 is input. then.

The detection circuit 14 inverts the state of the write input switching circuit 15. As a result, delay circuit 13 is inserted.

or controlled to be deleted. Due to this,
The writing timing CLK 1 of each frame of received data to the elastic memory 10 is delayed or advanced by the fixed delay time of the delay circuit 13. In this way, (5) Once the transmission delay time of the loop is controlled, unless the variation width of the loop transmission delay time exceeds the width of the fixed delay time.

The transmission timing and reception timing operate stably without conflicting again. Note that if the fixed delay time width to be inserted is set to half the frame length, the permissible variation width of the delay time is maximized.

As explained above, in a loop synchronous control station of a data highway system that connects multiple stations using a loop-shaped transmission path and transmits data, the loop delay correction circuit that corrects loop delay is configured to adjust the elastic memory write timing. By adding a circuit that compares the read timing and a circuit that delays the write data to the shelastic memory based on the comparison result, even when the loop transmission delay time is equal to an integral multiple of the frame length, No duplication or loss of data occurs. or.

The frame length was changed when the transmission delay time of the loop was an integral multiple of the frame length.Although it is possible to insert a fixed delay, the present invention can deal with any transmission delay, so (6) The number will be reduced.

[Brief explanation of the drawing]

FIG. 1 is a system configuration diagram of a general data highway device, FIG. 2 is a block diagram of a conventional loop delay correction circuit, and FIGS. 3 and 4 are diagrams showing the operation of a conventional loop delay correction circuit. FIG. 5 is a block diagram showing an embodiment of the loop delay correction circuit according to the present invention, and FIG. 6 is a diagram showing the operation of the loop delay correction circuit according to the present invention. 1...Loop synchronous control station, 2-4...Terminal station, 5...
・Ru...De-shaped transmission line, 6-9...Terminal device, 10.
... Elastic memory circuit, 11... Read timing generation circuit, 12... Write timing generation circuit, 13... Delay circuit, 14... Write and read timing comparison circuit, 15... Switching circuit. (7) Figure 3 Figure 5

Claims (1)

[Claims] (1) In a data network/way system that connects a plurality of stations via a loop-shaped transmission line to transmit data. A loop synchronization control station that controls loop synchronization includes a circuit that temporarily stores received data, a circuit that compares write timing and read timing of the storage circuit, and a circuit that delays the received data based on the comparison result. A datano-iway device characterized by the following features: