JPS6143852A - Communication system of loop type time division multiplex dataway - Google Patents

Abstract

PURPOSE:To decrease a circuit scale and the cost and to relieve a load to a hardware by reading a data at a prescribed address with a transmission data address signal, transmitting the data read from a data memory with a transmission timing signal and transmitting a reception data with a delay. CONSTITUTION:The transmission data address signal E forms an address An+k storing the k-th word of a reception signal when the output D of a transmission frame counter is Ak. The transmission data address signal E is subjected to time division processing by a 3-state buffer 51, the result is inputted to the data memory 10 to read the transmission data of a designated address. The transmission data read from the data memory 10 is loaded in parallel in a parallel/serial converting shift register 60, where the result is shifted by using a transmission bit clock and the parallel/serial conversion shift register output is obtained. Then the result is subjected to code modulation by a line driver 61 and a transmission data is outputted to a transmission line by using the transmission timing signal from a clock generator 40.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a communication system for a loop-based time division multiplex data way, and in particular to a method for reducing transmission delay of a loop by a data memory for switching control used in time division multiplex communication. The present invention relates to this type of communication system that uses compensation.

[Technical Background of the Invention] The configuration of a conventional loop type time division multiplex data way is shown in FIG. In FIG. 4, communication controllers No. 1 to No. n are connected in a loop through a transmission path 1, and data is transmitted and received. The transmission signal sent out from the communication controller N091 is received after going around the loop and sent out again, so the transmission delay of data going around the loop is always the length of the sent data, that is, the data frame. Must be an integer multiple. However, it is difficult to match the transmission path length to the data transmission delay so that it becomes an integer number of data frames, and it also changes depending on external conditions. Therefore, it is known to provide a loop delay compensation circuit at one location on the loop to control the round trip delay of the loop so that it is always an integral multiple of the data frame.

Generally, as shown in FIG. 5, loop delay compensation is performed by a delay controller 5 consisting of a re-counter or the like, with a delay element 4 such as a memory or a shift register interposed between the receiver 2 and the transmitter 3. controlled. The delay controller 5 is a circuit that receives a signal from the receiver 2 and also receives a transmission timing signal from the signal line 6 together with the transmitter 3. Reproduction is performed, and the receiver 2 sends out a reception timing signal such as a reception data clock and a reception data frame signal to the delay controller 5, and also sends an input data signal to the delay element 4. The delay controller 5 uses the reception timing signal and the transmission timing signal on the signal line 6 to send to the delay element 4 a delay time signal for making the round trip delay of the loop an integral multiple of the data frame. The delay element 4 sends an output data signal to the transmitter 3 in response to a signal from a delay controller 5, and the transmitter 3 outputs a transmission signal to a transmission line in response to a transmission timing signal on a signal line 6.

[Problems with the Background Art] However, the loop delay compensation described above requires independent hardware such as data memory, and in order to operate adaptively to changes caused by arbitrary loop lengths and external conditions, delay elements and delay controls are required. However, there are disadvantages in that the circuit scale of the device increases, and the cost and hardware burden increase.

[Object of the Invention] The present invention has been made in view of the above-mentioned conventional difficulties, and it is possible to reduce the loop transmission delay in a loop type time division multiplex data way by using a switching control data memory commonly used in time division multiplex communication. 5. It is an object of the present invention to provide a loop type time division multiplex data way communication system that reduces the circuit scale and reduces the cost and burden on hardware.

[Summary of the Invention] FIG. 1 shows loop delay compensation in a loop time division multiplex dataway communication system to achieve the above object. Of these, data memory 10. The address bus 11 and the data bus 12 utilize existing memories and buses used for exchange control in time division multiplex communications. In FIG. 1, the receiver 13
Gara.

The reception timing signal is sent to the reception timing control circuit 14, and the reception data is sent to the data memory 10 via the data bus 12. Further, the reception timing control circuit 14 sends a reception data address signal to the data memory 1o via the address bus 11.

On the other hand, a transmission timing address signal is sent from the transmission timing control circuit 15 to the transmission exchange control circuit 16, and a transmission data address signal is sent from the transmission exchange control circuit 16 to the data memory 10 via the address bus 11. Further, transmission data is sent from the data memory 10 to the transmitter 17 via the data bus 12, and a transmission signal is output from the transmitter 17 in response to a transmission timing signal from the transmission timing control circuit 15.

That is, in this method, first, the received signal is transmitted by the receiver 13,
It reproduces the signal clock, identifies and reproduces the received data signal, and reproduces the data frame information, and sends the signal clock and data frame information reception timing signal to the reception timing control circuit 14 as well as to the data memory via the data bus 12. The received data signal is sent to 10. Upon receiving the reception timing signal, the reception timing control circuit 14 sends a reception data address signal to the data memory 1o via the address bus 11 in order to instruct the address at which the reception data signal 8 should be stored in the data memory 1o. The received data signal is stored in the data memory 10.

On the transmission side, the transmission timing control circuit 15 sends a transmission timing address signal to the transmission exchange control circuit 16,
The transmission exchange control circuit 16 sends and designates a transmission data address signal indicating the storage address of data to be transmitted in the data memory 1O to the data memory 1O via the address bus 11, and reads the data at the address. The read data is sent to the transmitter 17 via the data bus 12, and the transmitter 17 outputs it as a transmission signal in response to a transmission timing signal from the transmission timing control circuit 15. , In this way, the received data is transmitted after being delayed by an arbitrary time.

[Embodiments of the Invention] Preferred embodiments of the present invention will be described below with reference to FIGS. 2 and 3.

The loop time division multiplex cheater-way communication system of the present invention is realized by a loop delay compensation circuit as shown in FIG. In FIG. 2, a line receiver 20 is connected to a bit synchronization circuit 21 and a code demodulation circuit 22, and from the code demodulation circuit 22, a frame synchronization circuit 24 and a data latch 25,
It is connected to a 3-state buffer 26. Further, the bit synchronization circuit 21 is connected to a code demodulation circuit 22, a serial/parallel conversion shift register 23, and a frame synchronization circuit 24, thereby forming the receiver 13 in FIG.

The reception timing control circuit 14 in FIG.
A data latch 32.3 state buffer 33 are connected to each other. Further, the bit synchronization circuit 21 and the frame synchronization circuit 24 each receive a received freight counter 30.
connected to.

The transmission timing control circuit 15 in FIG.
2 and a control logic circuit 43. The control logic circuit 43 is connected to various controllers in order to generate and send out signals synchronized with the timing of transmission.

The transmission exchange control circuit 16 shown in FIG. 1 is configured by connecting a control memory 50 and a three-state buffer 51. That is, it is connected from the transmission address conversion circuit 42 to the control memory 50, and is also connected to other internal circuits via the control memory address bus for one time division. Further, the control memory 50 is connected to other internal circuits via a control memory data bus for time division.

The transmitter 17 in FIG. 1 is comprised of a parallel-to-serial conversion shift register 60 and a line driver 61. The clock generator 40 is also connected to the line driver 61 .

The operation of the loop delay compensation circuit configured in this way is explained in the second section.
This will be explained using the time chart shown in FIG. 3 along with the drawings.

A received signal is input to the line receiver 20, and the bit synchronization circuit 21 extracts the bit clock component of the received signal.
A bit synchronous clock is regenerated.

On the other hand, the received signal is demodulated into an information code at a code demodulation port 11822 to obtain a demodulated received signal A as shown in FIG. Here, the th word of the fth frame of the demodulated received signal A is expressed as D(f,k), one word is made up of 8 bits, and symbols O to 7 are attached. The demodulated received signal A is converted to B by the serial/parallel conversion shift register 23.
1 to B8 are converted into serial/parallel shift register outputs. A synchronization word is detected in the frame synchronization circuit 24 from among the signals of the serial/parallel shift register outputs 81 to B8, and a frame synchronization signal is obtained. The reception frame counter 30 is driven by this frame synchronization signal and the reception timing signal of the bit synchronization clock to obtain a counter output representing the timing within the frame of the reception signal. On the other hand, the data latch 25 latches the serial/parallel shift register outputs B1 to B8 one bit at a time, and when the data latch 25 outputs D(f,k)O to 7, the reception frame counter 30 A signal representing the reception timing is output. This output signal is converted by the reception address conversion circuit 31 into an address signal for data memory 1/0 in which the reception data is stored, and then passed through the data latch 32 to the data memory 1.
A received data address signal C is applied to 0. here,
Data latches 25.32 are latches for absorbing timing differences between transmission and reception, and cause a delay of within 1 bit cycle (not shown), and 3-state buffers 26.33
is for time-division use of the data bus 12 and address bus 11. In Fig. 3.

The received data is stored with the An address as the first address, and the kjith word is stored in An+, and at time t2, the received data D(f, k) is stored in the A n + kth word of the data memory IO. Next, to explain the case where the data stored in the data memory 10 is retrieved and transmitted after a certain period of time, first, the output clock of the clock generator 40 is used to start the transmission frame counter 4.
1 is driven, and outputs Ak as the transmission frame counter output, which is the timing to transmit the th word in the frame. This output Ak generates a control signal for each part in the control logic circuit 43, and the control signal is output in synchronization with the transmission timing of the transmitter 17. In addition, the output Ak is sent to the control memory 5 by the transmission address conversion circuit 42.
It is converted into an address for storing the transmission exchange control data of 0,
This reads out the transmission data address signal E of the control memory 50.The control memory 50 realizes the exchange process by selecting an arbitrary address in the data memory 10 for the transmission data according to the stored data, but the reception data is not changed as it is. In the case of transmission, the transmission data address signal E becomes the address A n + k where the first word of the received signal is stored when the output of the transmission frame counter is Ak. This transmission data address signal E is time-divisionally processed by the 3-state buffer 51 and input to the data memory 10, and the transmission data at the specified address is read out.The transmission data read out from the data memory 10 is processed at time tq. It is loaded in parallel into a parallel-to-serial conversion shift register 60, where it is shifted by the transmission pit clock to obtain a parallel-to-serial conversion shift register output F. Then, the data is code-modulated by the line driver 61, and transmitted data is output to the transmission path in response to a transmission timing signal from the clock generator 40.

That is, the time 'ro from time t1 to time t4 in FIG.
represents the delay from the 0 signal of D(f,k) in the demodulated received signal A to the parallel-to-serial conversion shift register output F, and most of the delay is caused by the data memory IO. Further, the time from time 14 to t6 is defined as T1, and the frame period T2 (=T.

+T, ), so the parallel-to-serial conversion shift register output F
The time T3 required for the signal to pass through the line driver 61, go around the transmission loop including other communication controllers, and return as the demodulated received signal A via the line receiver 20 and the code demodulation circuit 22 is an integer of the frame period T2. times (1) to time T
1 is added. That is, for one hour T3, Ts = T2 X I + T1. Therefore, the round trip delay T4 of the entire transmission loop is the time T from the code demodulation circuit output (demodulated received signal A) to the parallel/serial conversion shift register output F.

and the delay time T3 from the parallel/serial conversion shift register output F to the code demodulation circuit output. Therefore, T4 = To + T3 = To + T2 I +T'+. Here, T2:TO+TI.

T< =T2 +T2 I =T2 (I + 1
), and it can be seen that the loop delay compensation function is realized.

In the above embodiment, the exchange control function is shown in which the reception data address signal C is fixed and the transmission exchange control circuit 16 is used to select the transmission data from the data memory 10 by the transmission data address signal E, but other methods may also be used. Similar effects can also be obtained by, for example, fixing the transmission data address signal E and selecting the reception data address signal C.

[Effects of the Invention] According to the present invention, as is clear from the above embodiments,
The loop transmission delay in a loop type time division multiplex data way can be reduced by using an exchange control data memory commonly used in time division multiplex communications to store received data and read out transmitted data. ,
Cost and burden on hardware can be reduced.

For example, one communication controller in the data way can be installed in the master controller, and the other communication controllers can be installed in the slave controller, and all exchanges including the transmission timing can be performed using the received data address signal (C). If processing control is performed, the parent controller and slave controllers can have similar circuit configurations, making it easy to share most of the hardware.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing loop delay compensation in the loop time division multiplex dataway communication system of the present invention, and FIG. 2 is a block diagram showing a preferred embodiment of the loop delay compensation circuit in the communication system of the present invention. Figure 3 is the second
A time chart showing the timing of signals in each part of the circuit diagram in the figure, Fig. 4 is a configuration diagram showing a general loop type time division multiplexing data way, and Fig. 5 shows a conventional loop delay in the data way in Fig. 4. FIG. 3 is a block diagram showing compensation. IO......Data memory 13...Receiver 14...Reception timing control circuit 15
...... Transmission timing control circuit 16 ...
...... Transmission exchange control circuit F ...... Transmitter

Claims (1)

[Claims] Received data is stored in an exchange control data memory used for an interface with a multiplexed transmission path in digital time division multiplex communication by specifying an address using a received data address signal, and among the data stored in the data memory, A loop time division multiplex data way communication system characterized by reading data at a predetermined address using a transmission data address signal, transmitting the data read from the data memory using a transmission timing signal, and delaying transmission of the received data. .