JP3001311B2 - Data communication processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication processing circuit, and more particularly to a data communication processing circuit of a serial data communication line for transmitting and receiving data on a plurality of lines.

[0002]

2. Description of the Related Art A conventional data communication processing circuit of this type includes:
As shown in FIG. 3, a plurality of data communication processing circuits 3A and 3B respectively corresponding to a plurality of data communication lines and an external data bus 2 for transferring data between the data communication processing circuits 3A and 3B are provided. It had been.

One data communication processing circuit 3A includes a reception control circuit 31 for processing serial reception data and performing serial-to-parallel conversion, a reception buffer 32 for temporarily storing parallel reception data from the reception control circuit 31, A data bus control circuit 33 for controlling the input / output of data to / from the bus 2; a transmission buffer 34 for temporarily storing the input parallel transmission data; and a serial transmission data for converting the parallel transmission data from the transmission buffer 34 from parallel to serial. Transmission control circuit 35 for outputting to the terminal TT
It was configured with.

Next, the operation of the conventional data communication processing circuit will be described.

[0005] First, the receiving operation will be described. The reception data DR, which is the serial data input from the reception terminal TR, is input to the reception control circuit 31. Reception control circuit 3
1 performs reception processing of the reception data DR in synchronization with the reception clock CKR, performs serial / parallel conversion, and performs
The bit parallel reception data PR is output and stored in the reception buffer 32. The parallel reception data PR stored in the reception buffer 32 is output to the internal data bus 36 by the reception data read signal RR. The data bus control circuit 33 transfers the 8-bit received data output to the internal data bus 36 from the data input / output terminal TD to the external data bus 2.
Output to

Next, the transmission operation will be described. The transmission data input from the external data bus 2 is stored in the transmission data buffer 34. The transmission data PT stored in the transmission data buffer 34 is input to the transmission control circuit 35 by a transmission data read signal RT. Transmission control circuit 35
Is parallel-to-serial converted from the parallel transmission data PT in synchronization with the transmission clock CKT, and output from the transmission terminal TT as serial transmission data DT.

The above operation is for one data communication line. For a plurality of communication lines, a plurality of data communication processing circuits 3A, 3B... It was to do.

[0008]

The conventional data communication processing circuit described above requires a transmission control circuit for parallel / serial conversion and a reception control circuit for serial / parallel conversion for each data communication line. When performing data communication on a line, there is a disadvantage that a plurality of corresponding communication processing circuits are required.

[0009]

A data communication processing circuit according to the present invention is a receiving synchronization circuit for synchronizing first and second received data and outputting corresponding first and second synchronized serial received data. A reception data combining circuit that combines the first and second synchronous serial reception data to generate combined reception data, and serially / parallel-converts the combined reception data and divides the combined reception data into first and second parallel reception data A reception control circuit, first and second reception data buffers respectively storing the first and second parallel reception data, and first and second transmissions respectively storing the first and second parallel transmission data A data buffer and the first and second parallel transmission data output from the first and second transmission data buffers in a parallel serial mode; A transmission control circuit for converting the combined transmission data into first and second serial transmission data, and a transmission data dividing circuit for dividing the combined transmission data into first and second serial transmission data. And a transmission synchronization circuit that synchronizes and outputs first and second transmission data.

[0010]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the data communication processing circuit of the present invention.

The data communication processing circuit 1 of the present embodiment has a configuration shown in FIG.
As shown in (1), a reception synchronization circuit 11 that synchronizes data received from a plurality of lines and outputs synchronous serial reception data, and a reception circuit that combines a plurality of synchronization serial reception data to generate a single combined reception data Data synthesis circuit 1
2, a reception control circuit 13 for converting the combined reception data into a parallel signal and dividing it into a plurality of parallel reception data, reception data buffers 14 to 16 for respectively storing the parallel reception data, an external data bus 2 and an internal data bus 24. A data bus control circuit 17 for controlling input / output of received data and transmission data; transmission data buffers 18 to 20 for respectively storing a plurality of parallel transmission data; A transmission control unit 21 for generating combined transmission data as data, and a transmission data dividing circuit 2 for dividing the combined transmission data to generate a plurality of serial transmission data
2 and a transmission synchronization circuit 23 for synchronizing a plurality of transmission data.

Next, the operation of this embodiment will be described.
In this embodiment, the number of lines will be described as three.

FIG. 2 is a time chart of the circuit of this embodiment shown in FIG.

First, the receiving operation will be described. The reception data, which is the serial data input from the reception terminals TR1 to TR3 of the three lines, respectively,
At 1, synchronization is achieved by the reception clock CKR.
The synchronous serial reception data DR1 to DR3 synchronized by the reception synchronization circuit 11 are input to the reception data synthesis circuit 12, and generate the single reception data DRS which is a single serial data by the data control clocks CKD1 to CKD3. .

The combined reception data DRS is transmitted to the reception control circuit 13
, Where the following reception data processing is performed by the transmission / reception control clock CKS. That is, the combined reception data D is generated by the data control clocks CKD1 to CKD3.
The RS is serial-parallel converted and divided into three 8-bit parallel received data PR1 to PR3. The parallel reception data PR1 to PR1 output from the reception control circuit 13
PR3 is stored in the reception data buffers 14 to 16, respectively. Since the above-described reception data processing is performed on the combined reception data DRS including data for three lines, the transmission / reception control clock CKS is equal to the reception clock CK.
The frequency is three times or more of R.

Next, the parallel reception data PR1 to PR3 stored in the reception data buffers 14 to 16 are sequentially transmitted from the reception data selected by the reception data output control signal CR via the internal data bus 24 to the data bus control circuit. 17 is output. The data bus control circuit 17 outputs the 8-bit parallel received data PR1 to PR3 output to the internal data bus 24 from the data input / output terminal TD to the external data bus 2.

Next, the transmission operation will be described. The parallel transmission data for the three lines input from the external data bus 2 via the data input / output terminal TD is output to the internal data bus 24 by the data bus control circuit 17, and the transmission selected by the transmission data input control signal CT The data is stored in one of the data buffers 18 to 20. The parallel transmission data PT1 to PT3 stored in the transmission data buffers 18 to 20, respectively, are input to the transmission control circuit 21.

The transmission control circuit 21 converts the parallel transmission data PT1 to PT3 into data control clocks CKD1 to CKD.
3 for parallel-to-serial conversion, and further synthesizes a single serial data DTS. Transmission control circuit 21 further performs transmission data processing using transmission / reception control clock CKS. The combined transmission data DTS is input to the transmission data division circuit 22, where the data control clock CKD
1 to CKD3, three serial transmission data DT
1 to DT3 are generated. The transmission data DT1 to DT3 are synchronized with the transmission clock CKT by the transmission synchronization circuit 23, and output from the transmission terminals TT1 to TT3 as serial transmission data for three lines, respectively.

The embodiments of the present invention have been described above. However, the present invention is not limited to the above embodiments, and various modifications can be made. For example, a selector for switching between synthesized serial data input from outside and synthesized reception data between the reception data synthesis circuit and the reception control circuit, and an external transmission of synthesis transmission data between the transmission control circuit and the transmission data division circuit. By providing a selector for switching between output to the transmission data division circuit and output to the transmission data division circuit, connection to other systems and expansion of data communication lines can be facilitated without departing from the gist of the present invention. Of course, you can.

[0021]

As described above, the data communication processing circuit according to the present invention comprises a reception data synthesizing circuit for generating synthetic reception data, and a reception control for serially / parallel converting the synthesis reception data and dividing it into a plurality of parallel reception data. A circuit, a plurality of corresponding reception data buffers, a plurality of transmission data buffers respectively storing a plurality of parallel transmission data, and a parallel-to-serial conversion of the plurality of parallel transmission data output from the transmission data buffer to generate composite transmission data And a transmission data dividing circuit that divides the combined transmission data into a plurality of serial transmission data, whereby one data communication processing circuit can process data communication of a plurality of data communication lines. is there.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a data communication processing circuit of the present invention.

FIG. 2 is a time chart illustrating an example of an operation in the data communication processing circuit according to the embodiment.

FIG. 3 is a block diagram illustrating an example of a conventional data communication processing circuit.

[Explanation of symbols]

 1, 3A, 3B data communication processing circuit 2 external data bus 11 reception synchronization circuit 12 reception data synthesis circuit 13, 31 reception control circuit 14-16, 32 reception data buffer 17, 33 data bus control circuit 18-20, 34 transmission data Buffer 21, 35 Transmission control circuit 22 Transmission data division circuit 23 Transmission synchronization circuit 24, 36 Internal data bus

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 29/04 H03M 9/00 H04J 3/02

Claims (1)

(57) [Claims] 1. A receiving synchronization circuit for synchronizing respective first and second received data and outputting corresponding first and second synchronized serial received data, and said first and second synchronized serial received data A reception data synthesis circuit that generates synthesized reception data by synthesizing the received data, a reception control circuit that serially / parallel converts the synthesized reception data and divides the data into first and second parallel reception data, First and second reception data buffers for storing parallel reception data, first and second transmission data buffers for storing first and second parallel transmission data, respectively, and the first and second transmission data Transmission control for parallel-to-serial conversion of the first and second parallel transmission data output from the buffer to generate composite transmission data A transmission data dividing circuit for dividing the combined transmission data into first and second serial transmission data; and synchronizing the first and second serial transmission data with the first and second transmission data, respectively. A data communication processing circuit comprising: a transmission synchronization circuit that outputs a signal.