JPH0810857B2 - AIS sending circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention uses a PCM multiplexed signal generated by multiplexing a plurality of low-order PCM signals and synchronously multiplexing a plurality of high-order PCM signals as a transmission path signal. The present invention relates to a PCM communication system, and particularly to an AIS (alarm information signal, a signal that prevents an alarm from spreading to the next repeater) used in the PCM communication system.

[Conventional technology]

Conventionally, in the PCM communication system, a PCM relay device having an AIS transmission circuit that transmits the AIS signal when the transmission path reception signal is in an asynchronous state has been used.

This AIS transmission circuit, as shown in FIG.
Corresponding to the number of high-order PCM signal systems, AIS generating circuits 22 to 29 are provided. These AIS generating circuits 22 to 29 receive the low-order PCM clock a, and based on these low-order PCM signals, AIS are generated respectively.
The low-order PCM signals x1 to x8 are output as signals. That is, the output lines from the AIS generating circuits 22 to 29 are in the bus form as shown by the thick arrows in FIG.
2 outputs a plurality of signals in parallel according to the clock a. Here, these multiple signals are converted to low-order PCM signals x
I'm calling it 1. These low-order PCM signals x1 to x8 are input to the multiplexing circuits 6 to 13, respectively. On the other hand, high-order PCM clock b
Are input to the clock frequency dividing circuits 14 to 21, respectively, and the frequency-divided clock c is output from each of the clock frequency dividing circuits 14 to 21 and given to the multiplexing circuits 6 to 13. As described above, each of the low-order PCM signals x1 to x8 is composed of a plurality of signals, and the multiplexing circuits 6 to 13 multiplex the plurality of signals based on the divided clock c to output the high-order PCM signals p to w. .

Thus, in the conventional AIS transmission circuit, the AIS signal for the low-order PCM signal is generated for each high-order PCM signal, and these low-order PCs are generated.
The AIS signal for M signal is multiplexed and the AIS signal output is output as a high-order PCM signal.

[Problems to be Solved by the Invention]

By the way, in the case of the above-mentioned PCM repeater equipped with the AIS signal insertion function, that is, in the case of the AIS transmission circuit, since the AIS generation circuit is provided for each high-order PCM signal, the PCM in which a plurality of high-order PCM signals are synchronously multiplexed. In the case of multiple signals, multiple AIS generation circuits, clock divider circuits, and multiplex circuits are required, resulting in not only a large circuit scale but also complexity.
There is also a problem that the number of connections between the elements that make up the circuit increases and the current consumption increases.

[Means for solving the problem]

The AIS sending circuit according to the present invention uses a PCM pulse train constituting a frame as one system, and a repeater device using a PCM multiplex signal in which a plurality of high order PCM signals are multiplexed as a transmission path signal. Used for high-order PCM signals
AIS generation circuit for generating IS signal at low PCM signal level, and switching circuit for inputting two systems of AIS signals from the AIS generation circuit and switching to AIS signal for high order PCM signal of each system, for high order PCM signal A clock division circuit that generates a clock to multiplex low-order PCM signals from a clock, and a multiplex that multiplexes low-order PCM signal level AIS signals to high-order PCM signals for each system using the clock from the clock division circuit And a circuit.

EXAMPLES Next, the present invention will be described with reference to examples.

FIG. 1 is a block diagram of an embodiment of an AIS transmission circuit according to the present invention.

Referring to FIG. 1, the low-order PCM clock signal a is input to the AIS generation circuit 1, and the ALS generation circuit 1 outputs the low-order PCM signals d to k as the AIS signals for the high-order PCM signals of each system. As shown in FIG. 1, the output lines through which the low-order PCM signals d and e are transmitted are in the bus format as indicated by the bold arrows, and therefore the low-order PCM signals d and e are composed of a plurality of signals. become. On the other hand, the output line to which the low-order PCM signals f to k are sent is a single output line as indicated by the thin arrow, and here, the low-order PCM signals f to k are composed of one signal. On the other hand, the clock divider circuits 14 to 17 have high levels.
The PCM clock signal b is input and the clock divider circuits 14 to 1
A plurality of frequency-divided signals c are output from 7. The low-order PCM signal d is input to the switching circuit 2 as the first-order high-order PCM signal, and the low-order PCM signal e for the second-order high-order PCM signal is further input.
And low-order PCM signals f and g, which are identification signals of high-order PCM signals
Is input, the switching circuit 2 operates on the low-level PC as described later.
Switching M signals d to g, that is, selectively inputting,
The low-order PCM signal 1 is output for the second-order high-order PCM signal. Similarly, the low-order PCM signal e for the high-order PCM signal of the second system is input to the first series of the switching circuit 3 and the 2nd line of the switching circuit 3 is input.
Low-order P as the identification signal of the high-order PCM signal of the 4th line in the sequence
The CM signals h and i are input and the low-order PCM signal m is output for the high-order PCM signal of the fourth system.

The low-order PCM signal (e) of the first series of the switching circuit 3 is input to the switching circuit 4, and the low-order PCM signals f and j are input to the second series of the switching circuit 4 as identification signals of the high-order PCM signal of the sixth system. Input the low-order PCM signal n for the 6th system high-order PCM signal
Is output. High-order PC of the second line in the first line of the switching circuit 5
Input the low-order PCM signal e for M signal, and input the low-order PCM signals f and k to the second series of the switching circuit 5 as the identification signals of the high-order PCM signal of the 8th system, for the high-order PCM signal of the 8th system. To output the low-order PCM signal o.

The output lines from the switching circuits 2 to 5 are in the bus form as indicated by the thick arrows in FIG.
The signals l to o are composed of a plurality of signals, and the multiplexing circuit 6,
The low-order PCM signals d and l to o are input to 10, 11, 12, and 13, and the multiplex circuits 6, 10, 11, 12, and 13 receive the low-order PCM signal d and the low-order PCM according to the divided clock c, respectively. The signals l to o are multiplexed to generate high-order PCM signals p, q, s, u of the 1, 2, 4, 6 and 8th systems.
And w. The low-order PCM signals e, h,
And i are input, the high-order PCM signal is used as the third-order high-order PCM signal
The signal r is output. The low-order PCM signals e, h, and j are input to the multiplexing circuit 8 and the high-order PCM signal t is output as the high-order PCM signal of the fifth system.

The low-order PCM signals e, f, and k are input to the multiplexing circuit 9, and the high-order PCM signal v is output as the high-order PCM signal of the seventh system.

As described above, when the high-order PCM signals p, q, r, s, t, u, v, and w are generated, as shown in FIG.
2 to 29, low-order PCM signal x from each AIS generation circuit 22 to 29
It is not necessary to generate 1 to x8. That is, in FIG. 1, low-order PCM signals d and e composed of a plurality of signals and different low-order PCM signals f to k are generated from the AIS generating circuit 1 based on the low-order PCM clock a, and the switching circuit 2 Lower PCM
Upon receiving the signals d and e and the low-order PCM signals f and g, one of the low-order PCM signals d and e and the low-order PCM signals f and g is selected in a predetermined order to generate the low-order PCM signal l. . Then, the multiplexing circuit 10 multiplexes the low-order PCM signal to generate the high-order PCM signal q (that is, the low-order PCM signal x2 in FIG. 2 corresponds to the low-order PCM signal 1 in FIG. 1). The switching circuits 3 to 5 also select the input signal in a predetermined order.

Similarly, as can be easily understood from FIGS. 1 and 2, the low-order PCM signal d corresponds to the low-order PCM signal x1, and the low-order PCM signal d
The signal e and the low-order PCM signals h and i correspond to the low-order PCM signal x3, the low-order PCM signal m corresponds to the low-order PCM signal x4, and the low-order PCM
The signal e and the low-order PCM signals h and j correspond to the low-order PCM signal x5, the low-order PCM signal n corresponds to the low-order PCM signal x6, and the low-order PCM
The signal e and the low-order PCM signals h and k correspond to the low-order PCM signal x7, and the low-order PCM signal o corresponds to the low-order PCM signal x8.

In this way, the switching circuit controls the switching of the low-order PCM signal to generate the low-order PCM signal for generating the high-order PCM signal, so the configuration of the AIS sending circuit does not use multiple AIS generating circuits. Can be simplified.

Switching circuit 2, multiplexing circuits 6 and 10 and clock frequency dividing circuit 14
Is composed of one circuit element.

Switching circuit 3, multiplexing circuits 7 and 11, and clock frequency dividing circuit 15
It consists of one circuit element.

Switching circuit 4, multiplexing circuits 8 and 12, and clock frequency dividing circuit 16
One circuit element is composed of.

Switching circuit 5, multiplexing circuits 9 and 13 and clock frequency dividing circuit 17
One element is composed of.

〔The invention's effect〕

As described above, in the present invention, it is not necessary to provide the AIS generation circuit for the high-order PCM signal, and the AIS generation circuit may generate the minimum necessary low-order PCM signal, that is, the AIS signal. Since most of the generator circuits for use in the system are shared, as a result, there is an effect that the circuit scale of the AIS transmission circuit can be reduced. In addition, AI
It is possible to reduce the number of elements that make up the S sending circuit, which greatly reduces the number of connections between elements, making it possible to realize an AIS sending circuit with a smaller mounting area than before and consume less current. There is an effect that can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an AIS transmission circuit according to the present invention, and FIG. 2 is a block diagram showing a conventional AIS transmission circuit. a: Low PCM clock, b: High PCM clock, c: Divided clock, d: Low PCM signal, e: Low PCM signal, f: Low PCM signal, g: Low PCM signal, h: Low PCM signal, i: Low level PCM signal, j: Low level PCM signal, k: Low level PCM signal, l: Low level PCM signal, m: Low level PCM signal, n: Low level PCM signal, o: Low level PCM signal, p: High level PCM signal, q: High level PCM signal Signal, r: high-order PCM signal, s: high-order PCM signal, t: high-order PCM signal, u: high-order PCM signal, v: high-order PCM signal, w: high-order PCM signal, x1: low-order PCM signal, x2: low-order PCM signal, x3: Low-order PCM signal, x4: Low-order PCM signal, x
5: Low level PCM signal, x6: Low level PCM signal, x7: Low level PCM signal, x8: Low level PCM signal, 1: AIS generation circuit, 2: Switching circuit, 3: Switching circuit, 4: Switching circuit, 5: Switching circuit, 6: Multiple circuit, 7: Multiple circuit, 8: Multiple circuit, 9: Multiple circuit, 10: Multiple circuit, 11: Multiple circuit, 12: Multiple circuit,
13: Multiplexer, 14: Clock divider, 15: Clock divider, 16: Clock divider, 17: Clock divider, 18: Clock divider, 19: Clock divider, 20: Clock Frequency divider, 21: Clock divider, 22: AIS generator, 23: AIS generator, 24: AIS generator, 25: AIS generator, 26: AIS generator, 2
7: AIS generation circuit, 28: AIS generation circuit, 29: AIS generation circuit.

Claims (1)

[Claims] 1. A repeater using a PCM pulse train as a transmission line signal, wherein a frame is composed of a PCM pulse train, and a plurality of high-order PCM signals in which a plurality of low-order PCM signals are multiplexed are synchronously multiplexed as a transmission path signal. And AIS generating means for generating first and second low-order PCM signals for two systems of AIS signals in accordance with a low-order PCM signal clock and generating a plurality of high-order PCM signal identification signals. The first and second low-order PCM signals are received, and one system of the third signal is received according to the identification signal.
Switching means for outputting a low-order PCM signal of the
Second switching means for receiving the fourth low-order PCM signal of one system according to the identification signal, and the high-order P
Clock dividing means for converting a CM signal clock into the low-order PCM signal clock, and a first high-order PCM based on the low-order PCM signal clock for receiving the first low-order PCM signal
First generating means for generating a signal, and the second low-order PCM
Second generation means for receiving a part of the signal and the identification signal and generating a second high-order PCM signal according to the low-order PCM signal clock; and for receiving the third low-order PCM signal for the low-order PCM signal Third generation means for generating a third high-order PCM signal based on a clock, and fourth high-order PCM based on the low-order PCM signal clock for receiving the fourth low-order PCM signal
An AIS transmission circuit, comprising: a fourth generation means for generating a signal.