JP2504028B2 - Relay device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a repeater of a PCM communication system that uses a PCM multiplexed signal generated by synchronously multiplexing a plurality of low-order PCM signals as a transmission path signal.

〔Overview〕

INDUSTRIAL APPLICABILITY According to the present invention, when a PCM multiple signal is received in an asynchronous state, in a relay means for generating a signal reproduced in a synchronous state, both the upper and lower signals of the low order signal forming the multiplexed signal are reproduced in a synchronous state. As a result, the terminal device can monitor the synchronization state of both the upper and lower signals of the low-order signal.

[Conventional technology]

In a conventional PCM repeater having a means for inserting an AIS signal when a received signal of this kind is in an asynchronous state, as shown in FIG. 2, a synchronously multiplexed high-order PCM signal is separated into two low-order PCM signals, One of the lower PCM signals a is output as it is as a transmission signal c, the other upper PCM signal j is frame-synchronized by the synchronizing signal 6, and in the synchronized state, the selector circuit 7 selects the upper PCM signal j. In the asynchronous state, the AIS signal g synchronized with the internal oscillator clock e was selected by the selector circuit 7 and output as the transmission signal 1.

[Problems to be solved by the invention]

A PCM repeater having such conventional AIS signal insertion means separates a high-order PCM signal into two low-order PCM signals, one low-order PCM signal has an AIS insertion means, and the other low-order PCM signal remains unchanged. Since it is designed to output in the state of
When transmitting a PCM signal to a PCM terminal device via a multi-stage PCM relay device, only one system monitors the asynchronous state at each relay device, and the PCM terminal device transmits the high-order PCM signal. Although it has a means for monitoring the synchronized state by separating it into two low-order PCM signals, it has a drawback that the means for identifying two low-order PCM signals in the asynchronous state operates only one system.

The present invention eliminates such drawbacks, and an object of the present invention is to provide a relay device capable of monitoring the synchronization state of both upper and lower signals of a low-order signal.

[Means for solving problems]

The present invention arrives at a PCM multiplexed signal generated by multiplexing a plurality of low-order PCM signals each constituting one frame, and a terminal for inputting an upper signal and a lower signal of the low-order PCM signal, respectively. In a relay device having an internal oscillator that generates an internal clock equivalent to the reference clock of the PCM multiplexed signal, a first synchronizing means for testing the synchronization of the lower signal and a second synchronizing means for testing the synchronization of the upper signal. When,
A clock selecting means for selecting either an internal clock or a clock regenerated from a higher-order signal based on the verification result of the second synchronizing means, and a clock corresponding to the above-mentioned signal in synchronization with the clock selected by the clock selecting means. First insertion signal generating means for generating one insertion signal; second insertion signal generating means for generating a second insertion signal corresponding to a lower signal in synchronization with the clock selected by the clock selecting means; First selecting means for selecting either the lower signal or the second insertion signal based on the test result of the synchronizing means, and selecting either the upper signal or the first inserting signal based on the test result of the second synchronizing means. And a second selecting means for

[Action]

When the upper signal is in the synchronous state, this upper signal is sent as it is. When the upper signal is in an asynchronous state, an insertion signal corresponding to the upper signal is transmitted in synchronization with the clock generated by the internal oscillator.

When the lower-order signal is in the synchronous state, this lower-order signal is transmitted as it is. When the lower signal is in the asynchronous state, if the upper signal is in the synchronous state, it is synchronized with the clock of the upper signal, an insertion signal corresponding to the lower signal is sent out, and if the above signal is in the asynchronous state, the internal oscillator In synchronism with the clock generated by, the insertion signal corresponding to the lower signal is transmitted.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of this embodiment.

The apparatus of this embodiment selects a clock selector circuit 3 for selecting one of the reception clock signal d and the internal oscillator clock e, an AIS signal generation circuit 4 for generating an AIS signal g in place of the upper PCM signal, and a lower AIS signal i. An AIS signal selector circuit 5 for outputting, a synchronizing circuit 1 for inputting the lower PCM signal a,
A selector circuit 2 that outputs a transmission signal c related to the lower PCM signal a; a synchronization circuit 6 that inputs the upper PCM signal j;
And a selector circuit 7 that outputs a transmission signal 1 related to the upper PCM signal j.

Next, the operation of the apparatus of this embodiment will be described with reference to FIG.

Input the high-order PCM signal, separate it into the low-order PCM signal, and
One of the M signals, the upper PCM signal j, is input to the synchronizing circuit 6 for frame synchronization, and at the same time, a part of the overhead bit data is taken out as separation data. In the asynchronous state, the switching signal k is sent to the clock selector circuit 3, and the clock is switched from the received clock signal d input in synchronization with the upper PCM signal to the internal oscillator clock e. In the AIS signal generation circuit 4, the fixed main signal synchronized with the clock f for the AIS signal from the clock selector circuit 3, the fixed partial overhead bit and the low-order service data which is a part of the overhead bit are transferred to the upper PC.
It is generated as the AIS signal g for the M signal. In the AIS signal selector circuit 5, the upper PCM input from the AIS signal generation circuit 4
The fixed insertion signal h is input to convert the AIS signal g for the signal to the AIS signal i for the lower PCM signal, and the A for the upper PCM signal is input.
Converts the upper and lower PCM signal identification signals in the fixed partial overhead bits in the IS signal to lower PCM signal identification signals,
The low-order service data, which is a part of the overhead bits, is converted into a fixed signal and output as the AIS signal i for the lower PCM signal. In the selector circuit 7, the high-order PCM signal j and the AIS signal g for the PCM signal from the AIS signal generation circuit 4 are input,
Based on the switching signal k from the synchronizing circuit 6, the upper PCM signal j is selected when the PCM signal is in the synchronous state and AIS is selected in the asynchronous state.
The signal g is selected and output as the upper PCM signal 1.

Further, since the higher-order signal constitutes one frame and the lower-order signal also constitutes another frame, the synchronizing circuit 1 has a different frame synchronization from the synchronizing circuit 6. When the synchronous circuit 1 detects that the lower PCM signal is asynchronous, it outputs the switching signal b. In the selector circuit 2, the low-order PCM signal a of the low-order PCM signals and the low-order PCM signal from the AIS signal selector circuit 5
When the AIS signal i for PCM signal is input and the switching signal b from the synchronization signal 1 is input, the lower PCM signal a is synchronized with the higher P
The lower PCM signal a is selected regardless of whether the CM signal is synchronous or asynchronous, and the lower PCM signal a is in the asynchronous state and the upper PCM.
In the synchronous state of the signal j, the clock from the received clock signal d input in synchronization with the upper PCM signal j is selected by the clock selector circuit 3, and the lower PCM synchronized with this clock is selected.
AIS signal i for signal is selected, and lower PCM signal a and upper
When both PCM signals j are in the asynchronous state, the internal oscillator clock is selected by the clock selector circuit 3, and the lower-order PC in which the AIS signal i for the lower-order PCM signal synchronized with this clock is selected.
It is output as the M signal c.

〔The invention's effect〕

INDUSTRIAL APPLICABILITY As described above, the present invention makes it possible for a relay device to insert an AIS signal into each of two low-order PCM signals at different timings.
This has the effect of monitoring the operating status of PCM signals. Further, even if the relay device is in the asynchronous state in the terminal device, there is an effect that it is possible to discriminate between the high-order PCM signal and the low-order PCM signal of the low-order PCM signals of the two systems.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of the embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of a conventional example. 1, 6 ... Synchronous circuit, 2, 7 ... Selector circuit, 3 ...
Clock selector circuit, 4 ... AIS signal generation circuit, 5 ...
... AIS signal selector circuit, a ... Lower-order PCM signal, b, k ...
... switching signal, c, 1 ... transmission signal, d ... reception clock signal, e ... internal oscillator clock, f ... AIS signal clock, g, i ... AIS signal, h ... fixed insertion signal, j
...... Higher PCM signal.

Claims (1)

(57) [Claims] 1. A terminal for receiving a PCM multiplexed signal generated by multiplexing a plurality of low-order PCM signals, each of which constitutes one frame, and for inputting a high-order signal and a low-order signal of the low-order PCM signal, respectively. And a repeater equipped with an internal oscillator that generates an internal clock equivalent to the reference clock of this PCM multiplexed signal, the first synchronization means for verifying the synchronization of the lower signal and the second synchronization for verifying the synchronization of the upper signal. Means, clock selecting means for selecting either the internal clock or the clock reproduced from the higher-order signal based on the verification result of the second synchronizing means, and synchronizing with the clock selected by the clock selecting means,
First insertion signal generating means for generating a first insertion signal corresponding to the above signal, and synchronized with the clock selected by the clock selecting means,
Second insertion signal generating means for generating a second insertion signal corresponding to the lower signal, and first selecting means for selecting one of the lower signal or the second insertion signal based on the test result of the first synchronizing means, And a second selecting means for selecting either the higher-order signal or the first insertion signal based on the verification result of the second synchronizing means.