JP2590923B2 - Multiplexed PCM signal repeater - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a PCM communication system in which a PCM multiplex signal generated by synchronously multiplexing a plurality of low-order PCM signals is used as a transmission line signal.
In particular, the present invention relates to a multiplexed PCM signal relay device provided with an AIS signal generation circuit.

[Conventional technology]

Conventionally, in a PCM repeater having a function of inserting an AIS (alarm information signal) signal (a signal for preventing an alarm from spreading to the next repeater) when this type of transmission path reception signal is in an asynchronous state, As shown in the figure, a high-order PCM signal y multiplexed synchronously is divided into a plurality of low-order PCM signals by a separation circuit 14.
The signals are separated into signals a, b, c, and d.
Select d, and in the asynchronous state, the AIS signal generator 6,
The switching circuits 10, 11, 12, and 13 select and output the AIS signal generated for each low-order PCM signal in 7, 8, and 9.

In addition, as shown in FIG.
The lower PCM signals a, b, c, and d obtained by separating the signal y into a plurality of pieces are monitored by a plurality of synchronization circuits 15, 15, 15, and 15, respectively. In the state, the DATA generation circuits 1, 1, provided for each lower PCM signal
The AIS signal was selected and output from 1,1.

[Problems to be solved by the invention]

By the way, the PCM with the conventional AIS signal insertion function described above
As shown in Fig. 3, the repeater separates the high-order PCM signal into a plurality of low-order PCM signals, outputs each low-order PCM signal in a synchronous state, and outputs an AIS signal when asynchronous, but outputs an AIS signal for each low-order PCM signal. Since the signal generator circuits 6, 7, 8, 9 are used, if the high-order PCM signal is a synchronous multiplexed signal of a plurality of low-order PCM signals, the AIS signal generator circuit is required to be multiple times larger, and the circuit scale is large. In addition, there is a disadvantage that the structure becomes complicated and current consumption increases.

In addition, in the conventional PCM repeater having the AIS signal insertion function described above, as shown in FIG. 4, a synchronous circuit is provided for each of a plurality of lower PCM signals to monitor the synchronous state. In order to generate an AIS signal, there is an AIS signal generation circuit having a DATA generation circuit for each lower PCM signal, so that the circuit scale is very large and complicated, and the current consumption increases.

In view of the above drawbacks, the technical problem of the present invention is to provide a multiplexed PCM signal that does not require an AIS signal generation circuit for each low-order PCM signal even when the high-order PCM signal is a synchronous multiplexed signal of a plurality of low-order PCM signals. It is to provide a relay device.

Another technical problem of the present invention is that a plurality of lower PCMs are provided.
An object of the present invention is to provide a multiplexed PCM signal repeater that does not require a synchronization circuit for each signal.

[Means for solving the problem]

According to the present invention, in a multiplexed PCM signal relay apparatus in which a high-order PCM multiplexed signal obtained by synchronously multiplexing a plurality of low-order PCM signals each including one frame of a PCM pulse train forming a frame and a transmission path signal is used, A separating circuit 14 for separating the PCM multiplex signal y into low-order PCM signals a, b, c, d;
A synchronous circuit 15 for detecting synchronous / asynchronous of the CM signals a, b, c, d;
A data generation circuit 1 for generating one asynchronous scrambled data, a frame generation circuit 2 for adding a frame signal i and an identification signal k, l, m of one low-order PCM signal; Identification signal adding circuits 3, 4, and 5 for replacing the identification signals n, o, and p of the output signals with identification signals of other low-order PCM signals; scrambling data of the DATA generation circuit 1, the frame generation circuit 2 and the identification signal Additional circuit
AIS signal generating circuits 6, 7, which generate the main signal AIS signals q, r, s, t for the low-order PCM signal at the time of asynchronous from the output signals of 3, 4, 5
8, 9 and the switching signals e, f, g, h from the synchronous circuit 15, the low-order PCM signals a, b, c, d and the low-order PCM signals from the AIS signal generation circuits 6, 7, 8, 9 respectively. Switching circuits 10, 11, 12, and 13 for switching between the signal main signal AIS signals q, r, s, and t, and low-order signals from the switching circuits 10, 11, 12, and 13
A multiplexed PCM signal relay device comprising: a multiplexing circuit 16 that multiplexes the PCM signals a, b, c, and d or the AIS signal for each lower-order PCM signal.

Further, according to the present invention, the upper PCM multiplexed signal y input to the repeater which uses the upper PCM multiplexed signal obtained by synchronously multiplexing a plurality of lower PCM signals constituting one frame of the PCM pulse train constituting the frame as the transmission path signal is input. Are the lower PCM signals a, b, c, d
, A selecting circuit 17 for selecting one of a plurality of lower PCM signals a, b, c, and d, a synchronizing circuit 15, and a DATA generating circuit 1 for generating one asynchronous scramble data. ,
A frame generation circuit 2 for adding a frame signal and an identification signal of one lower PCM signal, and an identification signal addition for replacing identification signals k, l, and m of output signals from the frame generation circuit 2 with identification signals of other lower PCM signals Circuits 3, 4, 5 and the DATA generation circuit 1
AIS signal generation circuit 6, which generates AIS signals q, r, s, t for lower-order PCM signals at the time of asynchronous from the scramble data of the above and the output signals of the frame generation circuit 2 and the identification signal addition circuits 3, 4, 5 7, 8, 9, each lower PCM signal a, b, c, d and AIS signal q, r,
switching circuits 10, 11, 12, 13 for switching between s and t, and the switching circuits 10, 1
1, 12, 13 and the lower PCM signals a, b, c, d or the lower PCM AIS signals q, r from the control circuit 18 and the switching circuits 10, 11, 12, 13 for controlling the selection circuit 17, respectively. , s, t are multiplexed.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the multiplexed PCM signal relay device of the present invention. High-order PCM multiplex reception signal y, high-order PCM
CLK y ′ is input to the separation circuit 14, and the four low-order PCM signals a, b,
Separate into c and d and synchronize with each other by the synchronization circuit 15
Outputs the switching signals SEL1e, SEL 2f, SEL 3g, and SEL 4h during asynchronous operation.

In the DATA generation circuit 1, the scramble data DATA at the time of AIS
i, the frame generation circuit 2 generates a frame signal j including one low-order PCM signal identification signal k, l, m, and the identification signal addition circuits 3, 4, and 5 separate the identification signal from the frame signal j from each other. Of the low order PCM signal identification signals k, l, m
Output as frame signals n, o, p for PCM signal.

In the AIS signal generation circuits 6, 7, 8, and 9, the frame signals n, o, p of the identification signal addition circuits 3, 4, and 5 are input to the input from the DATA generation circuit 1, respectively.
And outputs the main signal AIT signals q, r, s, and t as the asynchronous AIS signal for each low-order PCM signal.

In the switching circuits 10, 11, 12, and 13, the low-order PCM signals a, b, c, and d and the main signal AIS signals q, r, s, and t are inputted, and the switching signals SEL e, f, g, and l are input.
Accordingly, the low-order PCM signals a, b, c, d are selected during synchronization, and the main signal AIS signals q, r, s, t are selected during asynchronous operation, and are output as transmission signals u, v, w, x.

In the multiplexing circuit 16, the transmission signals u, v, w, x and the high-order PCMCLKy '
And outputs it as a high-order PCM multiplex transmission signal z.

Next, another embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram of one embodiment of the present invention.
The upper PCM multiplex reception signal y is input to a separation circuit 14 and separated into a plurality (four in FIG. 2) of lower PCM signals a, b, c, and d, and one lower signal is selected in a time division manner by a selection circuit 17. The switching signal e, f, g, h is output from the control circuit 18 after determining whether the lower signal selected by one synchronization circuit 15 is synchronous or asynchronous.

On the other hand, the DATA generation circuit 1 generates an AISDATA signal i at the time of AIS, the frame generation circuit 2 generates a frame signal j including a lower PCM signal identification signal, and the identification signal addition circuits 3, 4, and 5 respectively generate the frame signal j. , The identification signal is replaced with another identification signal k, l, m for another lower PCM signal, and is output as a frame signal n, o, p for another lower PCM signal.

The AIS signal generators 6, 7, 8, and 9 add the identification signals k, l, and m for the lower PCM signals of the identification signal addition circuits 3, 4, and 5 to the input from the DATA generation circuit 1 respectively, and AIS when asynchronous for signaling
A main signal AIS signal q, r, s, t is output as a signal.

The switching circuits 10, 11, 12, and 13 receive the lower PCM signals 1a, b, c, d and the main signal AIS signals q, r, s, t, and synchronize with the switching signals e, f, g, h. At times, the lower PCM signals a, b, c, d are selected, and when asynchronous, the main signal AIS signals q, r, s, t are selected, and the transmission signals u, v, w, x
Output as

The multiplexing circuit 16 synchronizes and multiplexes a plurality of lower signals and outputs them as an upper PCM multiplex transmission signal z.

〔The invention's effect〕

As described above, the present invention uses a plurality of lower PCM signals as upper PCM signals by sharing most of one low-order PCM signal AIS signal generation circuit with another low-order PCM signal AIS signal generation circuit. It is possible to generate different AIS signals and output them as a plurality of lower PCM signals that become upper PCM signals at the time of non-synchronization. This has the effect of reducing the circuit scale and the current consumption.

As described above, according to the present invention, synchronization monitoring of a plurality of lower PCM signals is performed in a time-division manner and detected by one synchronization circuit, and most of the AIS signal generation circuit for one lower PCM signal is replaced by another synchronization circuit. By sharing the AIS signal generation circuit for lower PCM signals, it is possible to generate different AIS signals for each of a plurality of lower PCM signals and output them as lower PCM signals that become upper PCM signals when asynchronous. The effect is that the scale and current consumption can be significantly reduced.

[Brief description of the drawings]

1 and 2 are block diagrams showing an embodiment of a multiplexed PCM signal relay device of the present invention, and FIGS. 3 and 4 are block diagrams showing a conventional example of a conventional relay device. a ... Low PCM signal 1, b ... Low PCM signal 2, c ... Low PCM
Signal 3, d …… Low PCM signal 4, e …… SEL 1, f …… SEL 2, g…
… SEL 3, h… SEL 4, i… AISDATA signal, j… Frame signal, k… Identification signal 2, l… Identification signal 3, m… Identification signal 4,
n ... frame signal 2, o ... frame signal 3, p ... frame signal 4, q ... main signal AIS signal 1, r ... main signal AIS signal 2, s
… Main signal AIS signal 3, t… Main signal AIS signal 4, u… Transmit signal 1, v… Transmit signal 2, w… Transmit signal 3, x… Transmit signal 4, y
…… High-order PCM multiplex reception signal, y …… High-order PCMCLK, z …… High-order P
CM multiplex transmission signal, 1 DATA generation circuit, 2 Frame generation circuit, 3 Identification signal addition circuit 2, 4 Identification signal addition circuit
3,5 ... Identification signal addition circuit 4,6 ... AIS signal generation circuit 1,7 ...
… AIS signal generation circuit 2,8 …… AIS signal generation circuit 3,9 …… AIS
Signal generation circuits 4,10 ... Switching circuits 1,11 ... Switching circuits 2,12 ...
… Switching circuits 3,13 …… Switching circuits 4,14 …… Separation circuit, 15 ……
Synchronous circuit, 16: Multiplex circuit, 17: Select circuit, 18: Control circuit.

Claims (2)

(57) [Claims] 1. A multiplexing PCM signal repeater using a high-order PCM multiplex signal obtained by synchronously multiplexing a plurality of low-order PCM signals as a transmission line signal, a separation circuit for separating an input high-order PCM multiplex signal into a low-order PCM signal. , A synchronization circuit that detects the synchronization / asynchronization of each separated low-order PCM signal, a DATA generation circuit that creates one scrambled data when asynchronous, and a frame generation that adds a frame signal and an identification signal of one low-order PCM signal A circuit, an identification signal adding circuit for replacing an identification signal of an output signal from the frame generation circuit with an identification signal of another low-order PCM signal, and scrambled data of the DATA generation circuit, the frame generation circuit and the identification signal addition circuit. An AIS signal generation circuit for generating an AIS signal for a low-order PCM signal at the time of asynchronous from an output signal; and a switching signal from the synchronization circuit for each low-order PCM signal and an AIS signal generation circuit. Each low-level PC
A multiplexing PCM, comprising: a switching circuit for switching between an AIS signal for an M signal; and a multiplexing circuit for multiplexing each low-order PCM signal from the switching circuit or the AIS signal for each low-order PCM signal.
Signal relay device. 2. A relay apparatus in which a plurality of lower-order PCM signals are synchronously multiplexed and a higher-order PCM multiplexed signal is used as a transmission path signal.
A separation circuit that separates the input upper PCM multiplex signal into lower PCM signals, a selection circuit that selects one of the separated lower PCM signals, and synchronization / asynchronization of the selected lower PCM signal , A data generation circuit that generates one asynchronous scrambled data, a frame generation circuit that adds a frame signal and an identification signal of one lower PCM signal, and a signal that is output from the frame generation circuit. An identification signal adding circuit for replacing an identification signal with an identification signal of another low-order PCM signal; and an AIS for a lower PCM signal during asynchronous operation based on scrambled data from the DATA generation circuit and output signals from the frame generation circuit and the identification signal addition circuit.
An AIS circuit for generating a signal, a switching circuit for switching between each lower PCM signal and the AIS signal, a control circuit for controlling the switching circuit and the selection circuit, and an AIS for each lower PCM signal or each lower PCM signal from the switching circuit. A multiplexed PCM signal relay device, comprising: a circuit for multiplexing signals.