JPH0134490B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a synchronization system that facilitates synchronization for demultiplexing m×n multiplexed digital signals on the receiving side.

Conventional technology and problems Mxn=N multiplexing is performed using a digital multiplex converter,
On the receiving side, it is common to synchronize with a higher order group before demultiplexing. However, when performing high-speed transmission, it is often difficult to synchronize high-order groups due to constraints such as delays in circuit elements. For this purpose, m multiplexed digital signals, that is, higher-order groups are
It is conceivable to synchronize the demultiplexed digital signals. In that case, it is necessary to add a header for n-multiplexing and demultiplexing, and a simple synchronization circuit for higher-order groups is also required.

Fig. 1 is an explanatory diagram of N multiplexing, Fig. 2 is a block diagram of the main parts of the multiplexer on the transmitting side, and Fig. 3 is a block diagram of the main parts of the demultiplexer on the receiving side. This shows that. That is, as shown in FIG. 1, the digital signals of channels #1 to #9 are multiplexed at every cycle of 1/fe, and a frame pattern F is added. The time slot corresponding to each channel of this N multiplex digital signal is 1/
fh (fh=fe×M, and M=N+F). In the configuration shown in FIG. 2 that performs such multiplexing, the output signal of the oscillator OSC1 of frequency fh is counted by the counter CTR1, and the count output is supplied to the multiplexer MUX1 as a clock signal for N multiplexing. and N to the frame pattern generator FPG1.
A device that supplies a clock signal for each multiplexing, supplies a frame pattern F from a frame pattern generator FPG1 to a multiplexer MUX1, adds a frame pattern F to every N multiplexed digital signals of each channel, and sends it out. It is.

On the receiving side, as shown in Fig. 3, the synchronization circuit FSY1 detects the frame pattern F, performs frame synchronization, controls the counter CTR2, and supplies a clock signal for demultiplexing to the demultiplexer DMUX1. Then, the multiplex digital signal synchronized by the synchronization circuit FSY1 is sent to the demultiplexer DMUX.
1 and separates it into digital signals of each channel #1 to #9.

In such a multiplexing system, synchronization is achieved in high-order groups, and in the case of high-speed transmission, it becomes difficult to achieve synchronization due to delays in circuit elements, etc., as described above. Therefore, it is applied to relatively low-speed transmission.

FIG. 4 is an explanatory diagram of conventional m×n=N multiplexing,
Figure 5 is a block diagram of the main parts of the multiplexing device on the transmitting side.
FIG. 6 is a block diagram of the main part of the demultiplexing device on the receiving side, in the case where m=3 and n=3. As shown in Figure 4, channels #1~
The digital signals #3, #4 to #6, and #7 to #9 are multiplexed every 1/fe period and the same frame pattern F is added to each of them, resulting in multiplexed digital signals m1, m2, m3 for every 3 channels. is multiplexed and a header H is added to make an m×n multiplex digital signal. One time slot of the m multiplex digital signal is 1/fm, and one time slot of the m×n multiplex digital signal is 1/fh'. becomes.

In the multiplexing device shown in FIG. 5 that performs such multiplexing, the output signal of the oscillator OSC2 with the frequency fh' is counted by the counter CTR2, and the output signal of the frequency fm
The count output signal is counted by counter CTR3, and the count output signal is sent to the multiplexer.
It is supplied as a clock signal for multiplexing MUXa, MUXb, and MUXc, and also supplies a clock signal for generating frame pattern F from counter CTR3 to frame pattern generator FPG2. As a result, the same frame pattern F is added to the digital signals multiplexed by the multiplexers MUXa, MUXb, MUXc, resulting in multiple digital signals m1, m2, m3 as shown in FIG. Also, the counter CTR2 supplies a multiplexing clock signal to the multiplexer MUX2, and the header generator HDG
A clock signal for generating header H is supplied to the header. As a result, as shown in FIG. 4, an m.times.n multiplexed digital signal to which a header H is added at every predetermined period is sent out from the multiplexer MUX2.

On the receiving side, as shown in Figure 6, the header H of the m×n multiplex digital signal is detected by the header detection unit HDT, and the received m×n multiplex digital signal is multiplexed together with the detection signal of this header H. Add to separation section DMUX2. Demultiplexer DMUX2
Then, based on the header detection signal, the multiplex digital signals m1, m2, m3 are separated in the order and added to the frame synchronization circuits FSYa, FSYb, FSYc, respectively.
The frame pattern F is detected and synchronized in FSYc, the counters CTRa, CTRb, and CTRc are controlled, and the demultiplexers DMUXa, DMUXb,
Supply the clock signal for demultiplexing to DMUXc,
The signals are separated into digital signals of channels #1 to #9, respectively.

In this m×n multiplexed digital signal, the oscillation frequency fh' of the oscillator OSC2 becomes higher by at least the addition of the header H compared to the multiplexing case shown in FIG. In order to identify the order of a set of multiplexed digital signals, a synchronization circuit such as a header detection unit HDT that detects the header H and achieves synchronization is required. This synchronous circuit is
Since it is intended to synchronize high-order groups, it must be constructed using high-speed circuit elements.

Purpose of the Invention The present invention enables multiplexing of m×n multiplexed digital signals without adding a header, and enables demultiplexing on the receiving side by synchronizing with lower-order groups. The purpose is to

Structure of the Invention The present invention transmits m×n multiplexed digital signals of a high-order group from a transmitting side, and receives m×n multiplexed digital signals of a low-order group which are demultiplexed by n on a receiving side that receives the m×n multiplexed digital signals of a high-order group. In a synchronization system that multiplexes and demultiplexes m digital signals, the transmitting side includes a multiplexing means for multiplexing m digital signals into m-multiplexed digital signals of a lower order group, and n multiplexed digital signals multiplexed by this multiplexing means. a multiplexing means for adding different frame patterns to each of the m multiplexed digital signals of the low-order group and multiplexing them as they are to obtain an m×n multiplexed digital signal of the high-order group; A separating means for receiving ×n multiplexed digital signals and separating them into n low-order groups of m-multiplexed digital signals, and a separating means for demultiplexing m low-order groups of m-multiplexed digital signals demultiplexed by the separating means. The demultiplexing means identifies the frame pattern added to the m-multiplexed digital signal of the low-order group and synchronizes the m-multiplexed digital signal. No header is added. Examples will be described in detail below.

Embodiment of the Invention FIG. 7 is an explanatory diagram of multiplexing according to an embodiment of the invention, and is for the case where m=3 and n=3 (N=9). The addition of frame patterns as m-multiplexed digital signals is similar to the conventional example shown in FIG. 4, but each frame pattern F1, F2, F3 is a different pattern. This frame pattern F1, F
2, F3 are added to generate multiple digital signals m1, m
2, m3, and the receiving side receives a multiplex digital signal m
1, m2, m3 as frame patterns F1, F2,
It can be identified by F3. and m
Although it multiplexes n multiple digital signals, it does not add a header H. Therefore,
If the period of one time slot of the m×n multiplex digital signal is 1/fh'', then fh''<fh'. That is,
Compared to the conventional m×n multiplex digital signal,
If the transmission speed is the same, the amount of information to be transmitted can be increased.

FIG. 8 is a block diagram of the main parts of a multiplexer on the transmitting side according to an embodiment of the present invention, in which an oscillator with a frequency fh''
The output signal of OSC3 is counted by counter CTR4, the count output signal of frequency fm' is counted by counter CTR5, and the multiplexing unit
It supplies clock signals for multiplexing to MUXA, MUXB, and MUXC, and supplies clock signals for generating frame patterns F1, F2, and F3 for each multiplexing to frame pattern generators FPGA, FPGB, and FPGC. , the multiplexed digital signals to which different frame patterns F1, F2, and F3 have been added are added to the multiplexer MUX3, and multiplexed using the multiplexing clock signal from the counter CTR4, resulting in an m×n multiplexed digital signal. Send from section MUX3. That is, as shown in FIG. 7, the m×n multiplex digital signal is composed of m1,
m2, m3, m1, m2, . . .

FIG. 9 is a block diagram of the main parts of a demultiplexing device on the receiving side according to an embodiment of the present invention.
The m×n multiplex digital signal input to the DMUX 3 is converted into n parallel signals by serial-parallel conversion. That is, the 3x3 multiplexed digital signal is converted into three 3x3 multiplexed digital signals. in this case,
The order of the m multiplex digital signals converted into parallel signals is arbitrary; for example, they may be output in the order of m2, m3, m1, and input in parallel to each frame synchronization circuit FSYA, FSYB, FSYC. Ru.

The frame synchronization circuit FSYA detects the frame pattern F1 among the frame patterns F1, F2, and F3 of the input m multiplex digital signals m1, m2, and m3, and performs frame synchronization on the multiplex digital signal m1 to which the frame pattern F1 has been added. and controls the counter CTRA to supply a clock signal for demultiplexing to the demultiplexer DMUXA, and the demultiplexer DMUXA demultiplexes into digital signals of channels #1, #2, and #3 based on the clock signal. . Also frame synchronization circuit
In FSYB, m input multiplex digital signals m
1, m2, m3 frame patterns F1, F2,
For F3, detect frame pattern F2,
Frame synchronization is performed on the multiplexed digital signal m2 to which the frame pattern F2 has been added, and a clock signal for demultiplexing is supplied to the demultiplexer DMUXB by controlling the counter CTRB.
DMUXB separates digital signals into channels #4, #5, and #6 based on the clock signal. Furthermore, the frame synchronization circuit FSYC detects the frame pattern F3 among the frame patterns F1, F2, F3 of the input m-multiplexed digital signals m1, m2, m3, and
Frame synchronization is performed on the multiplexed digital signal m3 to which 3 is added, and a counter CTRC is controlled to supply a clock signal for demultiplexing to the demultiplexer DMUXC, and the demultiplexer DMUXC selects channel #7 based on the clock signal. , #8, and #9 digital signals.

As mentioned above, the demultiplexer DMUX3 that processes the high-order group multiplexed digital signal separates the m×n multiplexed digital signal into n pieces into m multiplexed digital signals by simply serial-parallel conversion. This eliminates the need for frame synchronization in low-order group multiplex digital signals, and synchronization circuits FSYA, FSYB, FSYC perform frame synchronization, and synchronization separation units DMUXA, DMUXB,
The signal is separated into digital signals for each channel using DMUXC.

Effects of the Invention As explained above, the present invention provides multiplexing units MUXA, MUXB,
A multiplexing means such as MUXC, and different frame patterns F1 and F are applied to m multiplex digital signals of n low-order groups multiplexed by this multiplexing means.
2, F3 is frame pattern generator FPGA,
A multiplexing unit such as a multiplexing unit MUX3 is provided which adds data from FPGB, FPGC, etc. and directly multiplexes it into m×n multiplexed digital signals of a high-order group, and also provides a multiplexing unit such as a multiplexing unit MUX3 that adds m×n multiplexed digital signals of a high-order group to the receiving side. a demultiplexing unit DMUX3 or the like which demultiplexes m multiplexed digital signals of n low-order groups; a demultiplexing unit DMUXA which demultiplexes m of the m multiplexed digital signals of low-order groups separated by the demultiplexing means;
Demultiplexing means such as DMUXB and DMUXC are provided,
It identifies the frame patterns F1, F2, F3 added to the m-multiplexed digital signal of the low-order group, and synchronizes the m-multiplexing, and m×n of the high-order group.
Since frame synchronization is not performed for multiplexed digital signals, the demultiplexer DMUX on the receiving side
The separation means such as No. 3 need only have a function of performing serial-to-parallel conversion, which can be economical.

Also, it identifies different frame patterns and synchronizes them, but it identifies the frame pattern added to the m-multiplex digital signal of the low-order group, and since it is slower than the high-order group, the frame pattern The identification means and synchronization means have the advantage of being realized with a relatively simple configuration.

Furthermore, since the header H is not added to the m×n multiplex digital signal of the higher order group, there is an advantage that the amount of transmitted information can be increased.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram of conventional N multiplexing, Figure 2 is a block diagram of the main parts of the multiplexer on the transmitting side for the multiplexing method shown in Figure 1, and Figure 3 is the main parts of the demultiplexer on the receiving side. FIG. 4 is an explanatory diagram of conventional m×n multiplexing, FIG. 5 is a main part block diagram of a multiplexing device on the transmitting side for the multiplexing system shown in FIG. 4, and FIG.
The figure is a block diagram of the main parts of the demultiplexing device on the receiving side, FIG. 7 is an explanatory diagram of multiplexing according to the embodiment of the present invention, and FIG. 9 are block diagrams of main parts of a demultiplexing device on the receiving side according to an embodiment of the present invention. OSC1 to OSC3 are oscillators, CTR1 to CTR5,
CTRa~CTRc, CTRA~CTRC are counters,
MUX1~MUX3, MUXa~MUXc, MUXA
~MUXC is multiplexing unit, FPG1, FPG2, FPGA
~FPGC is the frame pattern generator, HDG is the header generator, FSY1, FSYa ~ FSYc, FSYA ~
FSYC is a frame synchronization circuit, DMUX1 to DMUX
3, DMUXa ~ DMUXc, DMUXA ~ DMUXC
is the demultiplexer.

Claims (1)

[Scope of Claims] 1. A transmitting side sends out a high-order group m×n multiplexed digital signal, and the receiving side receives the high-order group m×n multiplexed digital signal, and the receiving side demultiplexes n low-order group m multiplexed digital signals. In a synchronization method that multiplexes and demultiplexes m digital signals, the transmitting side includes a multiplexing means for multiplexing m digital signals into m-multiplexed digital signals of a low-order group, and n multiplexing means for adding different frame patterns to each of the m multiplexed digital signals of the lower order group and multiplexing them as they are into n multiplexed digital signals to obtain an m×n multiplexed digital signal of the higher order group; a separating means for receiving a multiplexed digital signal and separating it into n low-order groups of m-multiplexed digital signals; and a separating means for demultiplexing m low-order groups of m-multiplexed digital signals demultiplexed by the separating means. and the separating means identifies the frame pattern added to the m multiplexed digital signals of the low order group, and
A synchronization method characterized by synchronizing demultiplexing.