JPS6461135A - Multiplexed pcm signal repeater - Google Patents

Multiplexed pcm signal repeater

Info

Publication number
JPS6461135A
JPS6461135A JP21761487A JP21761487A JPS6461135A JP S6461135 A JPS6461135 A JP S6461135A JP 21761487 A JP21761487 A JP 21761487A JP 21761487 A JP21761487 A JP 21761487A JP S6461135 A JPS6461135 A JP S6461135A
Authority
JP
Japan
Prior art keywords
signals
order
ais
signal
pcm
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP21761487A
Other languages
Japanese (ja)
Other versions
JP2590923B2 (en
Inventor
Masahiko Takahashi
Takao Nakai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP21761487A priority Critical patent/JP2590923B2/en
Publication of JPS6461135A publication Critical patent/JPS6461135A/en
Application granted granted Critical
Publication of JP2590923B2 publication Critical patent/JP2590923B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

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  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To output AIS signals as plural low-order PCM signals to be used as high-order PCM signals at the time of asynchronizing by using most of an AIS signal generating circuits for high-order PCM signal to AIS signal generating circuits for low-order PCM signal in common to generate different AIS signals for plural low-order PCM signals being high-order PCM signals. CONSTITUTION:A high-order PCM multiplex signal (y) and a high-order PCMCLK y' are supplied to demultiplex circuit 14, where the signals are demultiplexed into 4-system of low-order PCM signals (a), (b), (c), (d), they are synchronized with a synchronizing circuit 15 so as to output switching signals SEL1e, SEL2f, SEL3g, SEL4h in synchronizing/asynchronizing state. Switching circuits 10, 11, 12, 13 receive lowporder PCM signals (a), (b), (c), (d) and main signal AIS(alarm information signal) signals (q), (r), (s), (t), use the switching signals SEL (e), (f), (g), (l) to select the low-order PCM signals (a), (b), (c), (d) in the synchronizing state and the main signal AIS signals (q), (r), (s), (t) in the asynchronizing state, and the result is outputted as transmission signals (u), (v), (w), (x).
JP21761487A 1987-08-31 1987-08-31 Multiplexed PCM signal repeater Expired - Lifetime JP2590923B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21761487A JP2590923B2 (en) 1987-08-31 1987-08-31 Multiplexed PCM signal repeater

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21761487A JP2590923B2 (en) 1987-08-31 1987-08-31 Multiplexed PCM signal repeater

Publications (2)

Publication Number Publication Date
JPS6461135A true JPS6461135A (en) 1989-03-08
JP2590923B2 JP2590923B2 (en) 1997-03-19

Family

ID=16707052

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21761487A Expired - Lifetime JP2590923B2 (en) 1987-08-31 1987-08-31 Multiplexed PCM signal repeater

Country Status (1)

Country Link
JP (1) JP2590923B2 (en)

Also Published As

Publication number Publication date
JP2590923B2 (en) 1997-03-19

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