JPS56110398A - Time slot replacement system - Google Patents

Time slot replacement system

Info

Publication number
JPS56110398A
JPS56110398A JP1282180A JP1282180A JPS56110398A JP S56110398 A JPS56110398 A JP S56110398A JP 1282180 A JP1282180 A JP 1282180A JP 1282180 A JP1282180 A JP 1282180A JP S56110398 A JPS56110398 A JP S56110398A
Authority
JP
Japan
Prior art keywords
time slot
output
counter
circuit
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1282180A
Other languages
Japanese (ja)
Other versions
JPS6159597B2 (en
Inventor
Yuji Kubota
Kuniaki Kihara
Takeshi Kakino
Masaki Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1282180A priority Critical patent/JPS56110398A/en
Publication of JPS56110398A publication Critical patent/JPS56110398A/en
Publication of JPS6159597B2 publication Critical patent/JPS6159597B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Abstract

PURPOSE:To realize a miniaturization of a device, by storing the number of output terminal corresponding to each time slot and at the memory position of an address that corresponds to the input terminal of a multiplexing circuit in each region of the time slot conversion memory and thus realizing an isolation of the output of a buffer memory just through a time slot conversion. CONSTITUTION:The frame synchronous circuit 16 has a synchronism with the output of te serial-parallel conversion circuit 3. In addition, the time slot counter 18 that uses the address signal as the input is provided along with the frame counter 17. Then the F bits of the signal applied to the input terminal 1-N is applied to the circuit 16 to secure a frame synchronizm for the multiplexing signal. After this, the counter 17 is set synchronizing with the time slot of the multiplexing signal to transmit an output. When the output of the counter 17 is at the address of the terminal 1-N at the F-bit position, the output is switched by a switch circuit from the counter 18 to be applied to the buffer memory 4.
JP1282180A 1980-02-04 1980-02-04 Time slot replacement system Granted JPS56110398A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1282180A JPS56110398A (en) 1980-02-04 1980-02-04 Time slot replacement system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1282180A JPS56110398A (en) 1980-02-04 1980-02-04 Time slot replacement system

Publications (2)

Publication Number Publication Date
JPS56110398A true JPS56110398A (en) 1981-09-01
JPS6159597B2 JPS6159597B2 (en) 1986-12-17

Family

ID=11816043

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1282180A Granted JPS56110398A (en) 1980-02-04 1980-02-04 Time slot replacement system

Country Status (1)

Country Link
JP (1) JPS56110398A (en)

Also Published As

Publication number Publication date
JPS6159597B2 (en) 1986-12-17

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