JPH01108823A - Intermediate repeater - Google Patents
Intermediate repeaterInfo
- Publication number
- JPH01108823A JPH01108823A JP26605787A JP26605787A JPH01108823A JP H01108823 A JPH01108823 A JP H01108823A JP 26605787 A JP26605787 A JP 26605787A JP 26605787 A JP26605787 A JP 26605787A JP H01108823 A JPH01108823 A JP H01108823A
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- JP
- Japan
- Prior art keywords
- signal
- circuit
- identification
- low
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 238000000605 extraction Methods 0.000 claims abstract description 20
- 238000001514 detection method Methods 0.000 claims abstract description 19
- 239000000284 extract Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 6
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000000926 separation method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000011084 recovery Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ＰＣＭ時分割多重伝送方式の中間中継装置に
利用する。特に、低位のＰＣＭ信号を複数個同期多重し
たＰＣＭ多重信号を伝送路信号とし、受信再生したＰＣ
Ｍ多重信号を直並列変換し元の低位のＰＣＭ信号に分離
し、再び一定の順序に多重し、高位のＰＣＭ信号に変換
する中間中継装置に利用する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to an intermediate relay device of a PCM time division multiplex transmission system. In particular, a PCM multiplexed signal obtained by synchronously multiplexing multiple low-level PCM signals is used as a transmission path signal, and a PC receives and reproduces it.
The M multiplexed signal is serial-parallel converted, separated into original low-order PCM signals, multiplexed again in a fixed order, and used in an intermediate repeater that converts into a high-order PCM signal.
本発明は中間中継装置において、
あらかじめ複数個の低位のＰＣＭ信号の識別信号および
複数個の信号路の選択情報の組み合せに対応した信号切
替回路の切替制御情報を記憶回路に設定しておき、複数
個の信号路のひとつを選択し、選択した信号路の選択情
報、選択した信号路上の低位のＰＣＭ信号の同期状態お
よびその識別信号と記憶回路の内容とに基づいて信号切
替回路および選択回路の制御を行うことにより、低位の
ＰＣＭ信号切替の手順が少なく、同期復帰時間が短くな
るようにしたものである。The present invention provides an intermediate relay device in which switching control information of a signal switching circuit corresponding to a combination of identification signals of a plurality of low-level PCM signals and selection information of a plurality of signal paths is set in advance in a storage circuit. The signal switching circuit and the selection circuit are selected based on the selection information of the selected signal path, the synchronization state of the low-order PCM signal on the selected signal path, its identification signal, and the contents of the storage circuit. By performing control, the number of procedures for switching low-level PCM signals is reduced, and the synchronization recovery time is shortened.
第２図は従来例の中間中継装置のブロック構成図である
。FIG. 2 is a block diagram of a conventional intermediate relay device.
従来、中間中継装置は、第２図に示すように識別信号抽
出回路が信号路のひとつに接続されている構成であった
。すなわち、入力端子ａに入力したＰＣＭ多重信号Ｓ１
は分離回路１で低位のＰＣＭ信号ＤＩ−Ｄ３に分離され
る。この分離された信号は、それぞれ信号切替回路２に
入力される。Conventionally, an intermediate relay device has a configuration in which an identification signal extraction circuit is connected to one of the signal paths as shown in FIG. That is, the PCM multiplex signal S1 input to input terminal a
is separated into a low-order PCM signal DI-D3 by the separation circuit 1. The separated signals are respectively input to the signal switching circuit 2.
信号切替回路２は制御回路１０により制御され入力した
信号の順序を切り替えて信号路０１〜Ｃ３に送出する。The signal switching circuit 2 is controlled by the control circuit 10 to switch the order of input signals and send them to signal paths 01 to C3.
選択回路４は信号路Ｃ＋−Ｃａのうちのひとつを選択し
、信号路上の低位のＰＣＭ信号を入力する。同期検出回
路５は選択回路４の出力信号を入力し同期外れを検出す
る。識別信号抽出回路６は常時信号路Ｃ１に接続され、
信号路Ｃ１上の低位のＰＣＭ信号を入力し識別信号を抽
出する。制御回路１０は同期検出回路５からの検出出力
および識別信号抽出回路６からの識別信号に基づいて信
号切替回路２および選択回路４を制御してあらかじめ定
められた順序で低位のＰＣＭ信号を多重化する。The selection circuit 4 selects one of the signal paths C+-Ca and inputs the low-order PCM signal on the signal path. The synchronization detection circuit 5 inputs the output signal of the selection circuit 4 and detects loss of synchronization. The identification signal extraction circuit 6 is always connected to the signal path C1,
A low-order PCM signal on the signal path C1 is input and an identification signal is extracted. The control circuit 10 controls the signal switching circuit 2 and the selection circuit 4 based on the detection output from the synchronization detection circuit 5 and the identification signal from the identification signal extraction circuit 6 to multiplex the low-order PCM signals in a predetermined order. do.
しかし、このような従来例の中間中継装置では、識別信
号抽出回路６は信号路Ｃ１のみに接続され、常に信号路
ＣＩの信号からのみ識別信号を抽出していた。However, in such a conventional intermediate relay device, the identification signal extraction circuit 6 was connected only to the signal path C1, and always extracted the identification signal only from the signal on the signal path CI.
たとえば、低位のＰＣＭ信号Ｄ１、Ｄ２、Ｄ３が多重化
されて伝送され、分離回路１で分離され、信号路Ｃ１、
Ｃ２、Ｃ３にはそれぞれ低位のＰＣＭ信号信号炉２．
、Ｄ、が出力され、かつ低位のＰＣＭ信号信号炉２期外
れの場合について説明する。制御回路１０の制御により
、選択回路４で低位のＰＣＭ信号Ｄ３、Ｄｌを選択し、
その同期状態を同期検出回路５で監視し、信号路Ｃ２、
Ｃ２の信号が同期状態であれば、信号切替回路２を制御
し、識別信号抽出回路６により識別信号を抽出し、あら
かじめ定められた順序に多重化できるように信号切替回
路２を制御していた。このために、信号路Ｃ＋ に出力
される低位のＰＣＭ信号が同期外れ状態であった場合に
、多重化する場合の同期状態の信号を信号路Ｃ１に出力
するような切替動作、次にあらかじめ定められた信号を
信号路ＣＩに出力する切替動作が必要であり、切替の手
順が多くなり、したがって同期復帰時間が長くなる欠点
があった０
本発明は上記の欠点を解決するもので、低位のＰＣＭ信
号切替の手順が少なく、同期復帰時間が短い中間中継装
置を提供することを目的とする。For example, low-order PCM signals D1, D2, and D3 are multiplexed and transmitted, separated by a separation circuit 1, and signal paths C1 and D3 are multiplexed and transmitted.
C2 and C3 each have a lower PCM signal reactor 2.
, D is output and the low-level PCM signal reactor is out of the second stage. Under the control of the control circuit 10, the selection circuit 4 selects the low-order PCM signals D3 and Dl,
The synchronization state is monitored by the synchronization detection circuit 5, and the signal path C2,
If the signal of C2 is in a synchronous state, the signal switching circuit 2 is controlled so that the identification signal is extracted by the identification signal extraction circuit 6 and multiplexed in a predetermined order. . For this purpose, if the low-level PCM signal output to signal path C+ is out of synchronization, a switching operation is performed to output a synchronized signal for multiplexing to signal path C1, and then a predetermined The present invention solves the above-mentioned drawbacks, and the present invention solves the above-mentioned drawbacks. It is an object of the present invention to provide an intermediate relay device that requires fewer PCM signal switching procedures and has a shorter synchronization recovery time.
本発明は、信号切替回路を含む中間中継装置において、
選択回路は、その出力信号を識別信号抽出回路に与える
手段と、選択した信号路の識別情報を出力する手段とを
含み、複数個の信号路の識別情報およびこの複数個の信
号路上に送出される低位のＰＣＭ信号の識別信号に対応
する上記信号切替回路の切替制御情報を格納する記憶回
路と、同期検出回路の検出出力、識別信号抽出回路の出
力信号および上記出力する手段の出力信号を入力し、上
記記憶回路の内容に基づいて上記信号切替回路および上
記選択回路の制御を行う演算処理回路とを備えたことを
特徴とする。The present invention provides an intermediate relay device including a signal switching circuit,
The selection circuit includes means for supplying its output signal to the identification signal extraction circuit, and means for outputting identification information of the selected signal path, and outputs identification information of the plurality of signal paths and information sent to the plurality of signal paths. a storage circuit for storing switching control information of the signal switching circuit corresponding to the identification signal of the low-order PCM signal; a detection output of the synchronization detection circuit; an output signal of the identification signal extraction circuit; and an output signal of the output means. The present invention is characterized in that it includes an arithmetic processing circuit that controls the signal switching circuit and the selection circuit based on the contents of the storage circuit.
選択回路の与える手段で選択回路の出力信号を識別信号
抽出回路に与える。記憶回路で複数個の信号路の識別情
報およびこの複数個の信号路上に送出される低位のＰＣ
Ｍ、信号の識別信号に対応する信号切替回路の切替制御
情報を格納する。演算処理回路で同期検出回路の検出出
力、識別信号抽出回路の出力信号および選択回路の出力
する手段の出力信号を入力し、記憶回路の内容に基づい
て切替制御信号を信号切替回路に与える。以上の動作に
より低位のＰＣＭ信号切替の手順を少なく、同期復帰時
間を短くできる。The output signal of the selection circuit is applied to the identification signal extraction circuit by means of the selection circuit. A storage circuit stores identification information of a plurality of signal paths and a low-level PC sent to the plurality of signal paths.
M, stores switching control information of the signal switching circuit corresponding to the signal identification signal; The arithmetic processing circuit inputs the detection output of the synchronization detection circuit, the output signal of the identification signal extraction circuit, and the output signal of the means for outputting the selection circuit, and provides a switching control signal to the signal switching circuit based on the contents of the storage circuit. The above operation reduces the number of low-level PCM signal switching procedures and shortens the synchronization recovery time.
本発明の実施例について図面を参照して説明する。第１
図は本発明一実施例中間中継装置のブロック構成図であ
る。第１図において、中間中継装置は、低位のＰＣＭ信
号を複数個同期多重したＰＣＭ多重信号を受信再生した
信号を入力する入力端子ａと、入力端子ａからＰＣＭ多
重信号Ｓｌを入力し直並列変換し元の低位のＰＣＭ信号
に分離する分離回路１と、分離回路１からの複数個の低
位のＰＣＭ信号ＤＩ−Ｄ３をその順序を切り替えて複数
個の信号路０１〜Ｃ８上にそれぞれ送出する信号切替回
路２と、信号路Ｃ，−Ｃ３上の低位のＰＣＭ信号り、〜
Ｄ、を入力してＰＣＭ多重信号Ｓ２を出力する多重回路
３と、多重回路３の出力ＰＣＭ多重信号Ｓ２を入力する
出力端子すと、複数個の信号路０１〜Ｃ３を選択し、選
択した信号路上の低位のＰＣＭ信号を出力する選択回路
４と、選択回路４の出力信号の同期状態を検出する同期
検出回路５と、低位のＰＣＭ信号り、 −Ｄ３から識別
信号を抽出する識別信号抽出回路６とを備える。Embodiments of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram of an intermediate relay device according to an embodiment of the present invention. In FIG. 1, the intermediate relay device has an input terminal a into which a signal obtained by receiving and reproducing a PCM multiplexed signal obtained by synchronously multiplexing a plurality of low-level PCM signals is input, and a PCM multiplexed signal Sl is inputted from the input terminal a and serial-parallel conversion is performed. a separation circuit 1 that separates the original low-order PCM signals into original low-order PCM signals; and a signal that switches the order of a plurality of low-order PCM signals DI-D3 from the separation circuit 1 and sends them onto a plurality of signal paths 01 to C8, respectively. The switching circuit 2 and the low-level PCM signals on the signal paths C and -C3,
A multiplex circuit 3 which inputs D and outputs a PCM multiplex signal S2, and an output terminal which inputs the output PCM multiplex signal S2 of the multiplex circuit 3 selects a plurality of signal paths 01 to C3 and outputs the selected signal. A selection circuit 4 that outputs a low-level PCM signal on the road, a synchronization detection circuit 5 that detects the synchronization state of the output signal of the selection circuit 4, and an identification signal extraction circuit that extracts an identification signal from the low-order PCM signal -D3. 6.
ここで本発明の特徴とすることろは、選択回路４に、そ
の出力信号を上記識別信号抽出回路６に与える手段と、
選択した信号路の識別情報を出力する手段とを含み、中
間中継装置に、複数個の信号路０１〜Ｃ８の識別情報お
よび複数個の信号路０１〜Ｃ３上に送出される低位のＰ
ＣＭ信号信号−１〜Ｄ３別信号に対応する信号切替回路
２の切替制御情報を格納する記憶回路９と、同期検出回
路５の検出出力、識別信号抽出回路６の出力信号および
出力する手段の出力信号を入出力ポート回路７を経由し
て入力し、記憶回路９の内容に基づいて切替制御信号を
入出力ポート回路７を経由して信号切替回路２に与える
演算処理回路８とを備えたことにある。Here, the features of the present invention include means for providing the selection circuit 4 with its output signal to the identification signal extraction circuit 6;
means for outputting the identification information of the selected signal path, and the intermediate relay device includes a means for outputting identification information of the plurality of signal paths 01 to C8 and a low-level P transmitted onto the plurality of signal paths 01 to C3.
A storage circuit 9 that stores switching control information of the signal switching circuit 2 corresponding to the separate signals of CM signal signals -1 to D3, a detection output of the synchronization detection circuit 5, an output signal of the identification signal extraction circuit 6, and an output of the output means. and an arithmetic processing circuit 8 which inputs a signal via the input/output port circuit 7 and provides a switching control signal to the signal switching circuit 2 via the input/output port circuit 7 based on the contents of the storage circuit 9. It is in.
また、演算処理回路８は選択回路４を制御する手段を含
む。Further, the arithmetic processing circuit 8 includes means for controlling the selection circuit 4.
このような構成の中間中継装置の動作について説明する
。第１図において、分離回路１で分離された低位のＰＣ
Ｍ信号Ｄ＋りＤ３は、信号切替回路２で信号路Ｃ３、Ｃ
２、Ｃ３上にそれぞれ出力される。低位のＰＣＭ信号り
、〜Ｄ３は、選択回路４に入力され、人出力ポート回路
７からの制御信号により、ひとつの信号が選択される。The operation of the intermediate relay device having such a configuration will be explained. In Figure 1, a low-level PC separated by isolation circuit 1
The M signal D+D3 is connected to signal paths C3 and C by the signal switching circuit 2.
2 and C3 respectively. The low-order PCM signals ~D3 are input to the selection circuit 4, and one signal is selected by the control signal from the human output port circuit 7.
選択回路４の選択情報は、入出力ポート回路７に入力さ
れて、選択された信号がどの信号路のものであるかを示
すものである。The selection information of the selection circuit 4 is input to the input/output port circuit 7 and indicates which signal path the selected signal belongs to.
この選択回路４の出力信号は同期検出回路５および識別
信号抽出回路６で信号の同期状態および識別信号が抽出
され、人出力ボート回路７に入力される。The synchronization state and identification signal of the output signal of the selection circuit 4 are extracted by a synchronization detection circuit 5 and an identification signal extraction circuit 6, and are inputted to a human output boat circuit 7.
記憶回路９には、選択回路の選択情報（すなわち、どの
信号路ＣＩ−Ｃ３の信号が選択されているか）および識
別信号によって信号切替回路２および選択回路４を制御
する制御情報が記憶されている。The storage circuit 9 stores selection information of the selection circuit (that is, which signal path CI-C3 is selected) and control information for controlling the signal switching circuit 2 and the selection circuit 4 based on the identification signal. .
演算処理回路８は、入出力ポート回路７から入力した情
報と記憶回路９の情報とにより、信号切替回路２または
選択回路４を制御する制御信号を作成し人出力ポート回
路７から出力し、分離回路１の出力信号はあらかじめ定
められた信号路に出力される。The arithmetic processing circuit 8 creates a control signal for controlling the signal switching circuit 2 or the selection circuit 4 based on the information input from the input/output port circuit 7 and the information in the storage circuit 9, outputs it from the human output port circuit 7, and separates the control signal. The output signal of the circuit 1 is output to a predetermined signal path.
いま、従来例の説明で述べた場合と同様に低位のＰＣＭ
信号Ｄ１、Ｄ２、Ｄ３が多重化されており、信号路Ｃ＋
、Ｃ２、Ｃ３にはそれぞれ低位のＰＣＭ信号信号炉２
Ｄ３ 、Ｄ＋が出力されかつ低位のＰＣＭ信号信号炉２
期外れの場合について説明する。選択回路４の出力信号
には信号路Ｃ２の低位のＰＣＭ信号信号炉３力されてい
るとする。同期検出回路５および識別信号抽出回路６に
よって選択回路４の出力信号が同期状態であり、また低
位のＰ ＣＭ信号Ｄ３であることが検出され、この情報
は選択回路４の選択情報とともに人出力ポート回路７を
通して演算処理回路８に認識される。Now, as in the case described in the explanation of the conventional example, the low PCM
Signals D1, D2, D3 are multiplexed and signal path C+
, C2, and C3 each have a lower PCM signal reactor 2.
D3, D+ output and low level PCM signal reactor 2
We will explain the case of out of period. It is assumed that the output signal of the selection circuit 4 is applied to the lower PCM signal signal generator 3 of the signal path C2. The synchronization detection circuit 5 and the identification signal extraction circuit 6 detect that the output signal of the selection circuit 4 is in a synchronous state and is a low-level PCM signal D3, and this information is sent to the human output port along with the selection information of the selection circuit 4. It is recognized by the arithmetic processing circuit 8 through the circuit 7.
これらの情報に基づき、演算処理回路８で記憶回路９に
記憶された情報から信号切替回路２の制御信号が作成さ
れ、入出力ポート回路７から出力される。この制御信号
により、信号切替回路２は信号路ＣｌＳＣ２、Ｃ３上に
出力された低位のＰＣＭ信号Ｄ２、Ｄｌ、ＤＩを低位の
ＰＣＭ信号Ｄ１、Ｄ２ 、Ｄ３の順に一度に切替える。Based on this information, a control signal for the signal switching circuit 2 is created by the arithmetic processing circuit 8 from the information stored in the storage circuit 9, and is output from the input/output port circuit 7. In response to this control signal, the signal switching circuit 2 switches the low-order PCM signals D2, Dl, DI outputted on the signal paths ClSC2, C3 to the low-order PCM signals D1, D2, D3 at once.
このような−度の動作により、分離された低位のＰＣＭ
信号信号−１〜Ｄ３号切替回路２においてあらかじめ決
められた信号路に出力され、多重回路３により多重化さ
れる。Due to such low-level operation, the isolated low-level PCM
The signals are output to a predetermined signal path in the signal-1 to D3 switching circuit 2 and multiplexed by the multiplexing circuit 3.
以上のように本実施例は、従来例のように多くの手順を
踏むことなく一度に信号切替回路２を制御することがで
きる。この切替動作以後、信号切替回路２は固定される
。一方、選択回路４は一定周期で信号路Ｃ１１０２、Ｃ
３を選択し、常に同期外れおよび識別信号を検出し、人
出力ポート回路７を通じて演算処理回路８に認識され、
異常状態が監視される。異常が検出された場合には上述
の動作により速かに、信号の順序がチエ’）りされ、常
に一定の順序で出力し多重化する。As described above, in this embodiment, the signal switching circuit 2 can be controlled at once without going through many procedures unlike the conventional example. After this switching operation, the signal switching circuit 2 is fixed. On the other hand, the selection circuit 4 periodically selects the signal paths C1102 and C1102.
3 is selected, the out-of-synchronization and identification signals are always detected, and are recognized by the arithmetic processing circuit 8 through the human output port circuit 7.
Abnormal conditions are monitored. If an abnormality is detected, the order of the signals is quickly checked by the above-described operation, and the signals are always output in a fixed order and multiplexed.
以上説明したように、本発明は、低位のＰＣＭ信号切替
の手順が少なく、同期復帰時間を短くできる優れた効果
がある。特に従来回路では多重度が増加するにつれて回
路規模が増大したが、入力ボート回路の出力の増加のみ
で、その手順は記憶回路の情報変更で容易にできる効果
がある。As described above, the present invention has the excellent effect of reducing the number of steps for switching low-level PCM signals and shortening the synchronization recovery time. In particular, in conventional circuits, the circuit scale increased as the degree of multiplicity increased, but this procedure can be easily achieved by simply changing the information in the memory circuit, with only an increase in the output of the input boat circuit.
【図面の簡単な説明】
第１図は本発明一実施例中間中継装置のブロック構成図
。
第２図は従来例の中間中継装置のブロック構成図。
１・・・分離回路、２・・・信号切替回路、３・・・多
重回路、４・・・選択回路、５・・・同期検出回路、６
・・・識別信号抽出回路、７・・・入出力ポート回路、
８・・・演算処理回路、９・・・記憶回路、１０・・・
制御回路、ａ・・・入力端子、ｂ・・・出力端子、０１
〜Ｃ３・・・信号路、Ｄ、Ｄ、〜Ｄ３・・・低位のＰＣ
Ｍ信号、Ｓｌ、Ｓ２・・・ＰＣＭ多重信号。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an intermediate relay device according to an embodiment of the present invention. FIG. 2 is a block diagram of a conventional intermediate relay device. DESCRIPTION OF SYMBOLS 1... Separation circuit, 2... Signal switching circuit, 3... Multiplex circuit, 4... Selection circuit, 5... Synchronization detection circuit, 6
...Identification signal extraction circuit, 7...Input/output port circuit,
8... Arithmetic processing circuit, 9... Memory circuit, 10...
Control circuit, a...input terminal, b...output terminal, 01
~C3...Signal path, D, D, ~D3...Low PC
M signal, Sl, S2...PCM multiplex signal.
Claims (1)
て複数個の信号路上にそれぞれ送出する信号切替回路と
、 この複数個の信号路のひとつを選択し、選択した信号路
上の低位のＰＣＭ信号を出力する選択回路と、 この選択回路の出力信号の同期状態を検出する同期検出
回路と、 低位のＰＣＭ信号から識別信号を抽出する識別信号抽出
回路と を備えた中間中継装置において、 上記選択回路は、その出力信号を上記識別信号抽出回路
に与える手段と、選択した信号路の識別情報を出力する
手段とを含み、 上記複数個の信号路の識別情報および上記複数個の信号
路上に送出される低位のＰＣＭ信号の識別信号に対応す
る上記信号切替回路の切替制御情報を格納する記憶回路
と、 上記同期検出回路の検出出力、上記識別信号抽出回路の
出力信号および上記出力する手段の出力信号を入力し上
記記憶回路の内容に基づいて上記信号切替回路および上
記選択回路を制御する演算処理回路とを備えた ことを特徴とする中間中継装置。(1) A signal switching circuit that switches the order of a plurality of low-level PCM signals and sends them onto a plurality of signal paths, and selects one of the plurality of signal paths and selects a low-level PCM signal on the selected signal path. In an intermediate relay device comprising a selection circuit that outputs a signal, a synchronization detection circuit that detects a synchronization state of an output signal of this selection circuit, and an identification signal extraction circuit that extracts an identification signal from a low-level PCM signal, the above selection is performed. The circuit includes means for providing the output signal to the identification signal extraction circuit, and means for outputting identification information of the selected signal path, and outputting the identification information of the plurality of signal paths and the identification information of the plurality of signal paths. a storage circuit for storing switching control information of the signal switching circuit corresponding to the identification signal of the low-order PCM signal to be transmitted; a detection output of the synchronization detection circuit, an output signal of the identification signal extraction circuit, and an output of the outputting means; An intermediate relay device comprising: an arithmetic processing circuit that inputs a signal and controls the signal switching circuit and the selection circuit based on the contents of the storage circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26605787A JPH01108823A (en) | 1987-10-20 | 1987-10-20 | Intermediate repeater |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26605787A JPH01108823A (en) | 1987-10-20 | 1987-10-20 | Intermediate repeater |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01108823A true JPH01108823A (en) | 1989-04-26 |
Family
ID=17425781
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26605787A Pending JPH01108823A (en) | 1987-10-20 | 1987-10-20 | Intermediate repeater |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01108823A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012187109A (en) * | 2012-05-14 | 2012-10-04 | Yanmar Co Ltd | Rice transplanter |
-
1987
- 1987-10-20 JP JP26605787A patent/JPH01108823A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012187109A (en) * | 2012-05-14 | 2012-10-04 | Yanmar Co Ltd | Rice transplanter |
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