JPS63207235A - Frame aligner circuit - Google Patents

Abstract

PURPOSE:To decrease a memory quantity and to minimize a delaying time by separating a pay-load and an overhead, storing them individually, executing the phase matching of a frame only to the over-head and outputting data. CONSTITUTION:The data in the pay load of an input frame are transferred to an output pay-load. As an FIFO memory 15 for a pay-load, only 16 bits are needed. For an FIFO memory 16 for an over-head, the data quantity of the overhead for one frame is needed. Consequently, conventionally, the quantity of the FIFO memory to need 6336 bits can be decreased to 16 bits of the FIFO memory 15 for the pay-load and 192 bits of the FIFO memory 16 for the overhead, namely, to 208 bits in total. The data position in the overhead and pay- load is dislocated, but when the data are inputted to the pay-load after a frame is combined with the node to be transmitted beforehand, the correct data can be received by extracting the pay-load only at the receiving side.

Description

[Detailed description of the invention] [General! ] By separating the payload and overhead for a frame that has a structure divided into a payload and overhead, and then performing phase alignment of the frame only for the overhead.

Reduces the amount of memory required by the frame aligner.

It also shortens the delay time for phase matching.

[Industrial application field]

The present invention relates to a frame aligner circuit that aligns the phase of frames in a ring network or multiplex transmission device in a digital transmission system that transmits frames that are configured to be divided into payload and overhead.

[Conventional technology]

FIG. 5 is an example of a basic frame related to the present invention.

FIG. 6 shows an example of a bit multiplexing circuit, FIG. 7 shows an example of a bit multiplexed signal, FIG. 8 shows an explanation of the functions of a frame aligner, and FIG. 9 shows an example of a conventional frame aligner circuit.

As a multiplexing method for digital transmission paths, a synchronous multiplexing method using bit multiplexing has been proposed. In this multiplexing system, for example, as shown in FIG. 5, a frame structure is adopted in which a low-order group signal is divided into an overhead and a payload. The overhead contains management information such as frame synchronization signals.

The payload contains the information that you actually want to transmit.

In the basic frame shown in FIG. 5, F represents a frame pattern, OH represents an overhead channel, and PL represents a payload. The transmission path speed of this basic frame is 5
0.688Mb/s, information signal speed is 49.152
Mb/s. The part shown in the diagram is B.

It has an 8-bit configuration, with 6.336 bits per frame.

When multiplexing a plurality of low-order group signals, bit multiplexing is performed by a parallel-to-serial conversion circuit 40 as shown in FIG. 6, and the multiplexed signals are thereby multiplexed.

As shown in FIG. 7, blocks in which each bit corresponds to a lower-order group channel are repeated one period.

By the way, when a ring network as shown in FIG. 8 is generally constructed using multiplexed signals, it is necessary to match the electrical lengths of the rings. The reason is as follows.

In the ring network of FIG. 8(a), when a specific frame is sent from node N1, the sent frame returns to node N1 with a delay of the transmission line delay time and processing time at each node.

If the delay time is not an integer multiple of the frame, then
), at the node N1, the phases of the transmitted frame and the received frame become gray. If the received frame were to be sent again, the frame phase would fluctuate each time the frame goes around, making it impossible to achieve frame synchronization at each node, making it virtually impossible to communicate.

Therefore, conventionally, a frame aligner is provided in one of the nodes on the ring to adjust the delay time so that the electrical length of the ring becomes an integral multiple of the frame length, as shown in FIG. 8(b). I have to.

The conventional frame aligner circuit is shown in FIG. 9, for example. In FIG.

First In First
0ut) memory, 51.52 is an AND circuit, 53 is a counter, 54 is a comparison circuit, 55 is a frame detection circuit, 5
6 represents a frame generation circuit, and 57 represents a difference detection circuit.

Input frame data is input using a special clock.

The data is written to the FIFO memory 50. The phase difference between the input signal and the output signal is detected by the difference detection circuit 57 using the frame pulses output by the frame detection circuit 55 and the frame generation circuit 56, and according to the phase difference,
Counter 53. The comparison circuit 54 allows the FIFO memory 5
Controls the amount of data stored in 0. This controls the input frame to match the output frame.

[Problem that the invention seeks to solve]

In the case of a frame aligner circuit as shown in FIG.
In principle, the FO memory 50 requires a memory space for at least one frame. Therefore, in the case of a frame configuration as shown in FIG. 5, one frame has 6,336
It requires 1 bit of memory, and 1 more bit, for example this 50M
When 24 sequences of b/s signals are multiplexed, 6336
x24=152064 bits of memory are required. and.

Since this FIFO memory requires high-speed operation (50 Mb/s), even if parallel processing is performed, the nine-circuit scale poses a problem. That is, according to the conventional method, l
In order to record data for frames (2), use a large-capacity FI
There is a problem that FO memory is required.

Also, the amount of FIFO memory is large.

This means that the transmission delay is large, and in the case of the basic frame shown in FIG. 5, a maximum delay of 125 μs occurs each time the frame passes through one frame aligner.

If we consider the case where there are multiple frame aligners in the entire transmission network, this delay becomes large.

The issue of delay time cannot be ignored either.

The present invention aims to solve the above problems, requires less memory,
It is an object of the present invention to provide a frame aligner circuit with a small delay time.

[Means for solving problems]

FIG. 1 shows an example of the basic configuration of the present invention.

In FIG. 1, 10 is a separation unit that separates the payload and overhead for an input signal, 11 is a storage unit that separately stores the separated payload and overhead, and 1
2 is a frame output unit that performs frame phase matching only for overhead and outputs it; 13 is an overhead detection circuit that detects overhead in a human signal; 14 is a changeover switch; 15 is a payload FIFO memory; 16
17 represents an overhead FIFO memory, 17 represents a frame generation circuit that generates a frame to be output, and 18 represents a selector that selects and outputs a payload or overhead.

The overhead detection circuit 13 sends a switching signal to the changeover switch 14 in response to the overhead in the input signal, guides the input signal to the overhead FIFO memory 16, outputs a write clock W2, and transfers the overhead to the overhead FIFO memory 16. Memo! Write in J l 6. Further, regarding the payload of the input signal, the input signal is guided to the payload FIFO memory 15 via the changeover switch 14, and the payload is written to the payload FIFO memory 15 by the write clock W1. Due to this.

Payload and overhead are separated.

On the output side, according to the frame to be generated under the control of the frame generation circuit 17, a readout [Dock R1 or R2 is sent to the payload FIFO memory 15 or overhead FIFO memory 16, then the data is read out, and the selector 18 to switch between the two and combine them (No. 3 is used as the output signal).

The payload FIFO memory 15 has a capacity that can store data equal to 2fti, which is the length of the overhead.

It has a capacity to store one frame's worth of overhead data.

[Effect]

FIG. 2 is an explanatory diagram of the operation of the frame aligner shown in FIG. 1.

In the frame aligner circuit shown in FIG. 1, data in the payload of an input frame is transferred to the output payload, as shown in FIG. At this time.

Since the position of the input frame's overhead is different from the position of the output frame's overhead, the amount of data needed to shift the position of the overhead, that is, twice the length of the overhead, is required. For example, if the frame configuration is the format shown in FIG. 5 mentioned above, the payload FIFO
As the memory 15, 16 bits are required.

Also, the overhead FIFO memory 16 is as follows.

Since the amount of overhead data for one frame is required, in the case of the frame configuration shown in FIG.

8×24≠192 bits are required.

Therefore, according to the present invention, the amount of FIFO memory that conventionally required 6336 pins can be reduced to 208 bits in total, including 16 bits in the payload FIFO memory 15 and 192 bits in the overhead FIFO memory 16.

Note that when the data passes through the two frame aligner circuits according to the present invention as shown in FIG. 2, the overhead and the data position in the payload are shifted, but it is necessary to assemble the frame in advance at the transmitting node and then put the data in the payload. For example, by extracting only the payload on the receiving side, correct data can be received.

〔Example〕

FIG. 3 shows an example of application of the present invention, and FIG. 4 shows another example of application of the invention.

FIG. 3 shows an example in which two frame aligners according to the present invention are used in a ring network. A frame aligner 20 at node Nl adjusts the electrical length of the ring to an integral multiple of the frame length. Although it is functionally similar to a conventional frame aligner, the amount of memory required is smaller than that of a conventional frame aligner circuit as shown in FIG.

The delay time is also short.

Calculations are made for the basic frame shown in FIG.

The minimum amount of FIFO memory required for the frame aligner is 6336 bits in the conventional case, and 16+192=208 bits in the case of the present invention. Therefore, about 3
It decreases to 1/0. Regarding delay time, 16/63
36, which is shortened to 1/396.

FIG. 4 shows an example of a pond using a frame aligner circuit according to the present invention.

In FIG. 4, 20-1 to 20n are frame aligners, 30 is a multiplex transmission device, and 31 is a multiplexer (
MUX), 32 is a demultiplexer (DMUX), TI
to Tn represent terminals.

The multiplex transmission device 30 is a device that time-division multiplexes a 50 Mb/s low-order group signal and converts it into a 600 Mb/s high-order group signal (iiW signal. As shown in FIG. 4, the input signal from the terminal is Frame aligners 20-1 to 20-n according to the present invention are used in the interface section.This allows frames of different phases input from each terminal to be aligned with the phase of frames generated in the multiplex transmission device. can.

〔Effect of the invention〕

As explained above, according to the third aspect of the present invention, it is possible to significantly reduce the amount of memory required for frame phase alignment and to shorten the delay time.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration example of the present invention, FIG. 2 is an explanatory diagram of the operation of a frame aligner according to the present invention, FIG. 3 is an application example of the present invention, and FIG. 4 is another application example of the present invention. FIG. 5 is an example of a basic frame related to the present invention, FIG. 6 is an example of a bit multiplexing circuit, FIG. 7 is an example of a bit multiplexed signal,
FIG. 8 is an explanatory diagram of the frame aligner function, and FIG. 9 shows an example of a conventional frame aligner circuit. In the figure, 10 is a separation unit, 11 is a storage unit, 12 is a frame output unit, 13 is an overhead detection circuit, 14 is a changeover switch, 15 is a payload FIFO memory, and 16 is an overhead FIFO memory. 17 represents a frame generation circuit, and 18 represents a selector.

Claims (1)

[Claims of Claims] A frame aligner circuit that performs phase alignment for a frame configured to be divided into a payload and an overhead, comprising: a separating means (10) for separating the payload and the overhead with respect to an input signal; and a separated input signal. A storage means (15) for storing the payload in the input signal, a storage means (16) for storing the overhead in the separated input signal, and reading from each of the storage means (15, 16) is switched, 1. A frame aligner circuit comprising: frame output means (12) for performing frame phase alignment.