JPH033032A - Interface circuit - Google Patents

Abstract

PURPOSE:To remove a delay error between a data bit delay due to the existence of a bit buffer circuit and an S bit by multiplexing the data bit and the S bit and driving the multiplexed bit prescribed times as much as the speed of a clock signal outputted from a terminal equipment. CONSTITUTION:The data bit of an envelop signal is converted into the speed of the terminal equipment by a speed converting circuit 1. In the circuit 1, the S bit is separated and the data bit and the S bit are multiplexedly converted into prescribed times as much as the speed of the terminal equipment. An output signal from the circuit 1 is inputted to a bit buffer circuit 2, which is driven twice of the speed of the terminal equipment. A selection circuit 3 selects the output signal of the circuit 1 or the circuit 2 and the output signal of the circuit 3 is separated into the data bit corresponding to the speed of the terminal equipment and the S bit. Consequently, a delay error between the data bit delay due to the existence of the bit buffer circuit 2 and the S bit can be removed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transmission system, and particularly to an interface circuit that converts an envelope signal into a signal for a terminal device.

[Conventional technology]

A conventional interface circuit of this type is composed of an S bit separation circuit 1O, a speed conversion circuit 11, a bit buffer circuit 12, and a selection circuit 13, as shown in FIG.

According to such an interface circuit, the envelope signal (Da in FIG. 2) is sent to the S bit separation circuit IO.
The bits are separated (FIG. 2 DC). Further, the data bits of the envelope signal (Da in FIG. 2) are converted to the signal speed of the terminal device in the speed conversion circuit 11 (ob in FIG. 2). Output signal from the speed conversion circuit 11 (Fig. 2 Db
) is input to the bit buffer circuit 12 and synchronized with the clock signal of the terminal device. For the data signal, a selection circuit 13 selects whether or not the bit buffer circuit 12 is included.

[Problem to be solved by the invention]

In the conventional interface circuit described above, the data signal passes through the bit buffer circuit 12 after S bit separation, so when the bit buffer circuit 12 is used, the data signal is delayed and a delay error with the S bit occurs. As a result, in the conventional interface circuit described above, a data signal may be dropped during data transmission.

The present invention has been made in order to eliminate the above-mentioned drawbacks, and it is an object of the present invention to provide an interface circuit in which a delay difference does not occur even depending on the path through which data signals pass.

[Means to solve the problem]

The twin interface circuit of the present invention takes in an envelope signal, converts the data bits to the speed of the terminal device, separates the S bits, and multiplexes these data bits and the S bits to a predetermined times the speed of the terminal device. a bit buffer circuit that synchronizes an output signal from this speed conversion circuit with a clock signal of a terminal device, and a selection circuit that selects an output signal from this bit buffer circuit and an output signal from the speed conversion circuit. , and a separation circuit that separates data bits and S bits from the output signal from the selection circuit.

The interface circuit of the present invention multiplexes data bits and S bits and operates at a predetermined speed of the clock signal of the terminal device, thereby reducing the delay error between the data bit delay and the S bit due to the presence or absence of a bit buffer circuit. It can be eliminated.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the interface circuit of the present invention. FIG. 2 is a diagram for explaining the operation of the embodiment of the present invention. The interface circuit shown in FIG. 1 includes a speed conversion circuit 1 and a bit buffer circuit 2.
The selection circuit 3 and the separation circuit 4 are configured as follows.

That is, the speed conversion circuit 1 converts the envelope signal (second
Figure Da) is taken in, the data bits (Figure 2 Db) are converted to the speed of the terminal equipment, and the S bits (Figure 2 Dc) are separated, and these data bits and S bits are converted to the speed of the terminal equipment. Multiple conversion is performed by a predetermined number of times. The bit buffer circuit 2 is configured to synchronize the output signal from the speed conversion circuit 1 with the clock signal of the terminal device. The selection circuit 3 has a circuit configuration that selects the output from the bit buffer circuit 2 and the output signal from the speed conversion circuit 1. The separation circuit 4 has a circuit configuration that separates data bits and S bits from the output signal from the selection circuit 3.

The operation of the embodiment having such a configuration will be explained.

The envelope signal (Da in FIG. 2) is input to the speed conversion circuit l. This envelope signal (Figure 2 Da) is
In the speed conversion circuit 1, the data bits (Db in FIG. 2) are converted to the speed of the terminal device. Further, in the speed conversion circuit 1, the S bit (Dc in FIG. 2) is separated, and these data bits and the S bit are multiplex-converted to a predetermined times the speed of the terminal device (Dd in FIG. 2).

The output signal from the speed conversion circuit 1 is input to a bit buffer circuit 2 for synchronization with the clock signal of the terminal device. The bit buffer circuit 2 is operated at twice the speed of the terminal device (De in FIG. 2).

Further, the selection circuit 3 selects the output signal from the speed conversion circuit 1 and the output signal from the bit buffer circuit 2, and operates by controlling the presence or absence of the bit buffer circuit 2. The output signal of this selection circuit 3 is passed through a separation circuit 4 to be separated into data bits at the speed of the terminal device and S bits.

〔Effect of the invention〕

As explained above, the present invention multiplexes data bits and S bits and operates at a predetermined times the speed of the clock signal of a terminal device. This has the effect of eliminating errors.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the interface circuit of the present invention, FIG. 2 is a diagram for explaining the operation of the same embodiment, and FIG. 3 is a block diagram showing a conventional interface circuit. 1... Speed conversion circuit, 2... Bit buffer circuit, 3... Selection circuit, 4... Separation circuit.

Claims (1)

[Claims] A speed at which an envelope signal is taken in, data bits are converted to the speed of a terminal device, S bits are separated, and these data bits and S bits are multiplexed to a predetermined times the speed of the terminal device. A conversion circuit, a bit buffer circuit that synchronizes an output signal from this speed conversion circuit with a clock signal of a terminal device, a selection circuit that selects an output signal from this bit buffer circuit and an output signal from the speed conversion circuit; An interface circuit comprising a separation circuit that separates data bits and S bits from an output signal from a selection circuit.