JPH03283730A - Adpcm channel tandem connection system - Google Patents

Abstract

PURPOSE:To reduce the deterioration in the reproduced voice signal by applying signaling and voice tandem connection without converting an ADPCM signal into the voice signal. CONSTITUTION:An ADPCM tandem connector 3 is provided with a channel interface circuit 31 interfacing a DS1 demultiplexer multiplexer 2a(2b) to receive the supply of an intra-station clock and first-in first-out memory (FIFOM) 32 applying speed conversion of a sender side data. Moreover, an FIFOM 33 applying speed conversion of a receiver side data and a signaling extraction circuit 34a extracting transmission signaling information by the violation code from a bipolar form sender data are provided. Moreover, a decoder circuit 34 converting an input bipolar signal into a unipolar signal and a code circuit 35 converting a receiver side data into a bipolar signal and adding frame information through the production of violation are provided. Thus, the signaling and voice tandem connection are implemented without converting the ADPCM signal into a voice signal. Thus, the deterioration in the voice quality is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an ADPCM channel tandem connection method for an ADPCM code communication system.

[Conventional technology]

In the conventional ADPCM channel tandem connection method, the transmitting side converts ADPCM-PCM audio and extracts signaling information, and the receiving side connects the audio and converts audio-PCM-ADPCM again and inserts the signaling information. It was a method.

[Problem to be solved by the invention]

In the conventional ADPCM channel tandem connection method described above, the transmitting side performs ADPCM-PCM-voice conversion and extraction of signaling information, and the receiving side performs voice connection and again performs voice-PCM-ADPCM conversion and inserts signaling information. Since it is a tandem connection system, there is a drawback that the audio quality deteriorates significantly due to ADPCM-voice and audio-AD, PCM conversion.

[Means to solve the problem]

The ADPCM channel tandem connection system of the present invention includes a channel interface circuit that interfaces with the next-order digital signal demultiplexer and receives clock supply, a speed conversion circuit that converts the speed of transmitting side data and receiving side data, and a bipolar format a transmission signaling extraction circuit that recognizes a transmission signaling frame from the transmission side data using a violation code and extracts transmission signaling information; a decoding circuit that converts a bipolar signal of a voice code and a signaling code into a unipolar signal; It has a code circuit that converts side data into a bipolar signal and adds frame information when a bipolar violation occurs.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the ADPCM tandem connection device in FIG. 1, and FIG. 3 is a fast-in-fast receiving side diagram in FIG. FIGS. 4(a) and 4(b) are diagrams showing the relationship between out-memory input and output data and clocks, and FIGS. 5(a) and 5(b) are format diagrams showing an example of one time slot data in this embodiment, respectively. b) is a diagram showing an example of the occurrence of bipolar violation on the receiving side, and FIGS. 6(a) and 6(b) are diagrams each showing an example of signal ring extraction of the ADPCM tandem connection device in FIG. 7th
This figure is a diagram showing the relationship between input/output data and clocks of the fast-in-fast-out memory on the transmitting side in FIG. 2.

In FIG. 1, in this embodiment, an ADPCM tandem connection device 3' that faces each other and transmits and receives data,
Primary group digital signal (hereinafter referred to as DS1) demultiplexing devices 2a and 2b which interface to this ADPCM tandem connection device 3, supply clocks, and perform demultiplexing of 24 channels of 64 Kbps data, and a DSL demultiplexing device 2.
The internal clock supply device 1 supplies internal clocks of 64 KHz and 8 KHz to the terminals a and 2b.

In FIG. 2, the ADPCM tandem connection device 3 in FIG. A waste-in-fast-out memory (hereinafter referred to as FIFOM) 32 that performs data speed conversion, a FIFOM 33 that performs speed conversion of receiving side data, and extracts transmission signaling information from bipolar format transmitting side data using a violation code. a decoder circuit (hereinafter referred to as DECODE) 34 that converts a bipolar input signal into a unipolar signal, and a code circuit that converts receiving side data into a bipolar signal and adds frame information when a violation occurs. (hereinafter referred to as C0DE) 35.

Next, the operation of the ADPCM tandem connection device shown in FIG. 2 will be explained.

First, FIGS. 1 and 2 show the operation of the receiving side.

Figures 3, 4 (a), (b) and 5 (a) (b)
).

CHIHF31 is DSI demultiplexer 2a (or 2b)
receives received data 41 separated into channels from
Write to FIFOM33. The read clock 39 of the FIFOM 33 is given from the CHI NF 31 to the internal clock supply device 1 in synchronization, and the received data 41 is sent to the CHI NF 31.
It is converted to the speed of the read clock 39 from F31. Incidentally, the relationship between the input/output data 41, 40 of the FIFOM 33 and the internal clock 39 is shown in FIG.

Output data 40 of FOFOM33 is input to C0DE35. The C0DE 35 converts the output data 40 into a bipolar signal and sends it to the opposing ADPCM tandem connection device 3 shown in FIG.

At this time, the 6th.
Signaling information is inserted in the 12th frame,
Signaling information is inserted in the opposing ADPCM tandem connection device 3, and frame information 42 is added to the output data 40 in order to extract the signaling in the opposing ADPCM tandem connection device 3. ) and (b), the 8-bit data of one time slot is assigned to two channels of 4 bits each, and a code is used in which each of the 4-bit bits is "1". Now, by using this code rule, we can create two consecutive bipolar violations: once for the 6th frame data as shown in Figure 5(a), and twice consecutively for the 12th frame data as shown in Figure 5(b). generated and used as frame information. Timing information of the 6.12th frame is sent from the CHINF circuit 31 to CoDE.
The signal is applied to a circuit 35 and a bipolar signal is output.

The data structure of one time slot in this embodiment is shown in Fig. 4 (
Examples of occurrence of bipolar violation are shown in FIGS. 5(a) and 5(b).

Next, FIGS. 1 and 2 explain the operation on the transmitting side.

This will be explained using FIGS. 6(a), (b), and FIG. 7.

A bipolar signal from the opposing ADPCM tandem connection device 3 shown in FIG. 1 is input to the DECODE 34.

The DECODE34 performs bipolar violation monitoring and bipolar/unipolar conversion. The 8-bit data of one time slot is synchronized with the internal 8kHz clock, and by monitoring the bipolar violation of the transmitting data, one bipolar bio The 8-bit data in which the rotation occurs is determined to be 6 frames, and
Two consecutive bipolar violations have occurred 8
The bit data is determined to be 12 frames. The signaling extraction circuit 34a extracts signaling information based on the frame information and sends it to the CHINF 31. Incidentally, an example of frame determination and an example of signaling extraction are shown in FIGS. 6(a) and 6(b).

DECODE34 performs bipolar/kneepolar conversion and writes the transmission data to FIFOM32.

The CHINF 31 adjusts the phase of the multi-frames on the multiplex side and reads out the transmission side data from the FIFOM 32 at the speed of the transmission clock of the DSL demultiplexer 2a. In addition, F
FIG. 7 shows a diagram of the relationship between the input/output data of the IFOM 32 and the clock. CHINF31 is DSI demultiplexer 2
According to the 6-frame pulse and 12-frame pulse for transmission from a, signaling information is inserted and sent to the DSL demultiplexer 2a.

〔Effect of the invention〕

As explained above, the present invention includes a channel interface circuit that interfaces with a DSI demultiplexer and receives clock supply, a speed conversion circuit that performs speed conversion of transmitting side data and receiving side data, and converting bipolar format transmitting side data. A transmission signaling extraction circuit that recognizes a transmission signaling frame using a violation code and extracts transmission signaling information, a decoding circuit that converts a bipolar signal of voice code and signaling code into a unipolar signal, and converts receiving side data into a bipolar signal. By having a code circuit that adds frame information when a bipolar violation occurs,
Signaling and audio tandem connections can be made without converting ADPCM signals to audio, so
This has the effect of reducing the deterioration of reproduced audio, which is a problem in conventional tandem connection systems.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the ADPCM tandem connection device in FIG. 1, and FIG. 3 is a fast-in-fast receiving side diagram in FIG. FIGS. 4(a) and 4(b) are diagrams showing the relationship between the input and output data of the out memory and the clock, and FIGS. 5(a) and 5(b) are format diagrams showing an example of one time slot data in this embodiment, respectively. 6(b) is a diagram showing an example of the occurrence of bipolar violation on the receiving side, and FIGS. 6(a) and 6(b) are diagrams showing an example of signaling extraction of the ADPCM tandem connection device in FIG. FIG. 7 is a diagram showing the relationship between input/output data and clocks of the fast-in-fast Aratome and memory on the transmitting side in FIG. 2. 1...Internal clock supply device, 2a, 2b...-Next group digital signal (DSL) demultiplexing device, 3...AD
PCM tandem connection device, 31... Channel interface circuit (CHINF), 32. 33... Fast-in-fast-out memory (FIFOM), 34...
Decode circuit (DECODE), 34a-signaling extraction circuit, 35... code circuit (CODE) 36.
... Signaling extraction signal, 37 ... Transmission data, 3
8...Write clock, 39...Read clock, 40...Output data, 41...Receive data, 4
2... Frame information, 43... Transmission signaling signal.

Claims (1)

[Claims] A channel interface circuit that interfaces with the primary group digital signal demultiplexer and receives clock supply, a speed conversion circuit that converts the speed of transmitting side data and receiving side data, and transmitting from the transmitting side data in bipolar format using a violation code. A transmission signaling extraction circuit that recognizes a signaling frame and extracts transmission signaling information, a decoding circuit that converts a bipolar signal of a voice code and a signaling code into a unipolar signal, and a bipolar violation circuit that converts the receiving side data into a bipolar signal. AD characterized in that it has a code circuit that adds frame information upon generation.
PCM channel tandem connection method.