JPS61125240A - System split system in pcm communication - Google Patents

Abstract

PURPOSE:To apply the title system to a communication line of 4 systems by giving a signal transmitted via an existing PCM24B system to a split means. CONSTITUTION:The lower portion in a figure shows a split section which splits a PCM224B system inputted from the right side into 4 PCM6 systems. That is, the transmission format and clock of a low-order group (PCM6 system X4) is subjected to subordinate synchronization to the transmission format and clock period of a high-order group (equivalent to PCM24 system), and a signal outputted as a serial binary code string of the high-order group is stored once in a buffer storage device once while using a multi-frame as one unit, the data is split into information content of predetermined constant channel, the information content of a multi-frame of a low-order group consists of the content, and after a frame synchronizing bit is added thereto, each is converted into a serial binary code synchronously with the low-order group clock and outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a signal splitting scheme for adapting digital signals sent by existing PCM 24 B systems to a PCM 6 channel system.

[Prior art]

The PCM six-path carrier telephone system is commonly known as the IPCM6 system in Japan, and is gradually becoming popular as a simple and economical communication system for short or medium distances in areas with relatively low call volume. The system has not yet been standardized nationally. In addition, it is desirable to transmit several lines of this system at once between relatively distant areas that use similar PCM6 systems, and in this case, in order to effectively utilize communication lines, it is necessary to As shown in the figure, the four PCM6 systems are further multiplexed using the multiplexer ■-a (101), and the line 1
00 for a certain distance and receive it. In the j・PCM 6 system, the splitting device MtJX-b
(102), a method is adopted in which the system is again divided into four PCM six systems. In this way, PCM signals for 24 channels can be transmitted as one system using one line 100, which is extremely economical. Hereinafter, this system will be tentatively referred to as "PCM24 system equivalent".

[Problem that the invention seeks to solve]

In this way, in order to connect the higher-order group side (the "PCM24 system equivalent" side) and the lower-order group side (1'-PCM6 system x autopsy side), it is necessary to synchronize both, and for this reason, conventionally For frame synchronization, extra pulses that are not directly related to the information to be transmitted are often added to the transmission format of
This is commonly called stack synchronization.

However, in general, the PCM 24 system, which is the main trunk line,
For example, a PC with specifications from the Telegraph and Telephone Public Corporation! In the M24B system, there is no room to add the above-mentioned frame synchronization pulse, and therefore the transmission formats of both systems cannot be made to match, and there is a problem that they cannot be directly connected.

This is due to the fact that the conventional PCM6 system was developed only for application within a local area, and was not originally intended for connection to existing backbone lines. This is becoming more and more acutely felt as a serious drawback as information becomes increasingly centralized.

[Means and effects for solving the problems] The present invention has been made in view of the above-mentioned problems.
PCM signals sent via the M24B system
In order to adapt to the communication lines of 6 systems x 4 systems, the following dividing means is taken.

Already, the transmission format and clock of the low-order group ("PCM6 system x 4") are synchronized and dependently synchronized with the transmission format and clock period of the high-order group (1" equivalent to the PCM24 system"), and the serial binary code string of the high-order group is synchronized. The signal to be output as a multiframe is stored in a buffer storage device as one unit, and the data is divided into information contents of a predetermined number of communication paths, and each of them is used to divide the information contents of the lower-order group side multiframe. After adding frame synchronization bits to this, each is converted into a serial binary code string synchronized with the lower-order group side clock and output.

〔Example〕

Hereinafter, the present invention will be described in detail based on illustrated embodiments. In order to facilitate understanding, not only the PC and 'M division method of the present invention but also the PCM multiplexing method will be explained at the same time.

FIGS. 1(a), (b), (C)*(d) show an embodiment of the present invention as a whole, and (a) shows the structure of the frame and multi-frame on the lower order group side in this embodiment, (b) C. Configuration of the circuit used in the method of the present invention (C)
, (d) is a drawing showing details of the multiplexing 1 division and circuit used in the circuit shown in (b).

Table 1 shows the PCM6 on the lower order group side used in the present invention.
Indicates the specifications of the system. First, Table 1 and Figure 1 (,)
To explain the frame structure of the PCM 6 system based on the upper part, an l frame, which is the basic unit of information transmission, is composed of a 49-bit serial binary code string, of which the first bit, The F bit in FIG. 11 is allocated to the same frame M bit, and the remaining 48 bits are assigned as information words for each communication path (in this case, a total of 6 communication paths). In other words, the information word for each call path is 98 bits per call. As will be described later, one multiframe is composed of 12 frames arranged in series. Furthermore, for the audio signal on each channel, 5 frames out of 6 frames (therefore, 10 frames out of 1 multiframe) are transmitted as 8-bit codes, and 1 frame out of 6 frames (therefore, 2 frames out of 1 multiframe) are transmitted as 8-bit codes.
frame) transmits the audio signal using the first 7 bits (1st to 7th bits), and the last bit (8th bit) carries the dial signal transmission (hereinafter abbreviated as signal transmission). .

Table 1 PGM6 system specifications and higher
system), and is based on the general and lower order group side (PCM system), which is clear from the pJ1 table.
6 system side) clock frequency is 329 kHz,
Therefore, the pulse interval within each information word is 1/329 (
kHz) = 2.55 (μB) Therefore, the time length of one frame (in other words, audio signal sampling interval) is 2.55 (μB) x 49 (bit) = 125 (μB) Therefore, the sampling frequency is i / 125 (μB) = 8 (kHz) 6 ports < Both are configured to be the same as that of the existing 1'OM24B system.

Furthermore, as shown in the lower part of Figure 1(a) and Table 2, 127
One multiframe is composed of 1/- frame as a unit. l
The length of multiframe 1/-me is 125 (μB) x 12 (
Prime)z15 (ms). As shown in the second column of Table 2 (F bit column)! +1 multi-frame periodic frame synchronization bit (F bit) has a certain temporal pattern (1, 0, 0, 0, 1, 1, 0, 1, 1,
1, 0, game h7 report) is given, and this functions as information for frame synchronization. The pulse pattern of this F bit is assumed to be the same as that of the PCM 24 B system.

Next, the 176-bit stay-ring method described above is adopted for signal transmission, as shown in Table 2. The 6th and 12th frames in the multi-frame are used as signal frames, and the 1st to 7th bits are used for voice transmission (No. 8 transmission), and the 8th bit is used for signal transmission (OL transmission). Hereinafter, this frame will be referred to as a signal frame.As mentioned above, the signal frame insertion position within the multiframe is the same as that of the PCM24B system.

The operation of multiplexing the four PCM-6 systems and dividing them again is performed in units of multiframes by the circuits shown in FIGS. 1(b), (c), and (d). The frame structure of the higher order group multiplexed by this circuit is shown in Figure 3.
CM 6 ). In other words, the 7 frames on the higher-order group side are frame synchronization pins (F
It consists of information words for 24 channels (8 bits/channel) with bit) at the beginning, and the number of bits per frame is 1(b) + 8 (bloH) x 24 (0H) = 19
3(b) Also, the clock frequency on the higher order group side is 1.544
MH2, and the transmission time per frame is 193
(b) XI/1.544 (MHz) = 125
(μB), which completely matches that of the lower order group (described above).

The multi-frame configuration on the higher order group side is based on the existing PCM 24
It completely matches that of the B system, and is also the same as that of the lower order group side, except that the amount of information per frame is 193 b (for 24 communication paths).

Furthermore, by multiplexing/division into multi-frames, the structure of multi-frames on the higher-order side (F-bit pulse pattern and signal frame insertion position) is also the same as shown in Table 2. It completely matches the multi-frame structure of the iL4 existing PCM24B system.

Next, the synchronization format of the system will be explained.

First, regarding bit synchronization on the low-order group side (PCM a side), in other words, synchronization of the clocks on the low-order group and high-order group, the transmission time per frame (frame time length) on the low-order group side and high-order group side is ) are both 125 μ3. Since the amount of information contained in one frame is 193 b and 49 b, respectively,
It is necessary that the following relationship holds between the two clock frequencies.

In order to prevent a slip phenomenon between the reference clocks between the high-order group and the low-order group (in other words, a phenomenon in which the relative time positions at both ends of each frame shift), the clock on the low-order group side must be fixed to the clock on the high-order group main station side. It is necessary to synchronize subordinate to.

Fig. 4 is a conceptual diagram explaining the flow of the recovered clock in this system, where 103 is the main station (PCM 24 B terminal equipment).
This is a clock recovery circuit that extracts a cyclic signal (in the case of this figure, a 1.544 MHz continuous wave component) from the input received pulse train, and is the same as in the normal case (LO resonance circuit is used).

104 is a PLL circuit that converts the regenerated clock pulse into a low-order clock pulse (392 kHz in the case of this figure), which divides the original pulse into 1/139 (8 kHz) and further multiplies this by 49. By doing this, a pulse train of a desired frequency is obtained.Due to the nature of the circuit, the frequency (392 kHz) and phase of the output pulse are completely dependently synchronized with the original clock pulse (1,544 MHz).

The low-order side clock established in this way is multiplexed/
In addition to functioning as a transmission/reception clock for the dividing device 101, each terminal station 105m, 105b on the lower order group side (PCM a side)
It is reproduced again at 105c and 105d, and functions as a transmitting and receiving clock for each of these terminal stations.

Next, regarding multiframe synchronization, a case will be described in which four PCM6 systems are multiplexed to obtain one PCM 24 B system. As already explained, the length of each frame between the high-order group and the low-order group is set to be completely equal, but the number of pulses included in one frame and the interval between adjacent pulses are different from those between the high-order group and the low-order group. completely different. Further, since the distances between the multiplexing device and each of the six PCM terminal stations are different, there is a possibility that the phase synchronization of frames of each system input to the multiplexing device may be incomplete. Furthermore, it is desirable to establish synchronization between the high-order group and the low-order group on a multi-frame basis.
Input the serial binary code string synchronized with the clock of side a),
The information words of each PCM6 system are stored as parallel binary code strings in a buffer memory (Burym) in units of one multi-frame.
n MEMORY ), add a predetermined pattern of frame synchronization bits to this, convert it into a serial secondary code string synchronized with the higher-order group side clock, and output it. 1 system of PCM6 of buffer button device 12 (Frame)X6 (OH/Frame)
X 8 (b) - 72X 8 (b). Similar measures can be taken when dividing one line of PCM 24 B into four lines of PCM 6.

On the receiving side, the F-bit pattern is decoded to accurately determine whether each input pulse is a chain-side bit of a chain-side channel of a chain-side frame. FIGS. 5(a) and 5(b) are conceptual diagrams showing the flow of each communication path in the case of multiplexing and division, respectively.

The circuit constructed based on the above basic concept is shown in Figure 1 (b
) Shown in (c) and (d). The multiplexing unit multiplexes the four PCM6 systems that receive less input from the left side in the upper row of Fig. 1(b) and converts it into one PCM 24 B system, and outputs it toward the right side. This is a division section that divides the input into A 2 B Q PG J 6 Numa Ku section and outputs it, but for the lower order group side, it is PCM 6 (1
) (Only the communication path numbers OH1, 2, 3...6) are shown. First, to explain the case of system multiplexing, la is the received P input as a bipolar pulse train.
The BU conversion circuit 2a converts the α signal into a unipolar pulse train and outputs it, and the BU conversion circuit 2a detects the same frame synchronization signal (F-bit pulse train) as the output of the BU conversion circuit 1a, and the contents of the information word will be described later. The frame synchronization detection circuit 3a outputs the output to the multiplexing circuit 4 of the frame synchronization detection circuit 2a, detects the frame number, communication path number, and boundary time between frames of the input signal, and multiplexes the results. This is a reception pulse generation circuit that outputs a control signal to the converter circuit 4, and its operation is regulated by the low-order group side black pulses extracted by the BU conversion circuit 1a.

5a outputs the frame number of the higher-order group side (in this case, the transmitting side) and other control signals to the multiplexing circuit 4, and also outputs a frame synchronization bit i (F This is a transmission pulse generation circuit that adds bits). Other 3 systems on the lower order group side (PCM 6 (2) l (
3)? Similar outputs are obtained for (4) ), and the outputs of the combinations are combined by an OR circuit (not shown) and output to the line.

FIG. 1(c) shows the internal configuration of the multiplexing circuit 4, and 4m is a serial/parallel conversion circuit (not shown in the figure) that converts the serial binary code string input from the frame synchronization detection circuit 2a into a parallel binary code string. 8/P), 4b is a serial/parallel conversion circuit 4
A buffer storage device temporarily stores the output of a.
r memory).

4C is a parallel/serial conversion circuit (indicated as P/S in the figure) that reads the data stored in the buffer storage device 4b, converts it into a serial binary code string, and outputs it to the line; 4d is a multiplexer. A microprocessor (MPU) controls the operation of each part of the circuit 4.

In the above configuration, PCM6 (1) input from the left side
After the received signal of the system (OHI, 2...6) is converted into a unipolar pulse train by the BU conversion circuit 2a, information regarding frame synchronization is extracted by the frame synchronization detection circuit 21, and the information word is (392kHz
z) as a serial binary code string in the multiplexing circuit 4.
It is input to the parallel conversion circuit 4a and converted into a parallel code string □
On the other hand, the reception pulse generation circuit 2m works together with the frame synchronization detection circuit 3a to detect the 7 frame number of the information data input to the multiplexing circuit 4, and uses the result as a control signal to control the serial/parallel conversion circuit. Send it out at a distance of 4m. MPU
4d stores the output data (parallel 2-column code string) of the serial/parallel conversion circuit 4 at a predetermined address in the buffer storage device 4b according to the 7-lem number in response to a command from the serial/parallel conversion circuit 4. When the storage of all information data for one multiframe for the four input side systems is completed, the parallel/serial conversion circuit 4c issues a transmission command to the MPU 4d. MPU4
d is a transmission pulse generation circuit (lγ). According to a command from 5a, an F bit is added to the top position of the multi-frame, and the same circuit 5a further transfers information data regarding the frame number instructed one after another to the parallel/serial conversion circuit 4C. Here, the transmitter clock (1,544MHz)
The signal is converted into a serial binary code string synchronized with , and further outputted to the line via the U-B conversion circuit 6a. The above operations are performed on the input side 4 systems PCM e (') t (2) t (3)
t (4) is performed in series for each system, and the outputs are combined by an OR circuit and output to the line side as one PGM24B system.

Next, the structure and operation of the lower dividing portion in FIG. 1(b) will be explained. In other words, PCM with more inputs from the right side
24 B system 1 system (Call route number OH1, 2, 3
..., 23.24) into four PCM6 systems (PC
M 6 (1), (2), (3) and (4))
The circuit network is divided into lb, 2b, and 3b in the figure.

The parts and functions of fib and fib 6b are the same as 1a, 2maro, 3a, 5a, and 6a in the upper part of the figure, except that the number of communication paths for information processed by these is different. Therefore, the explanation will be omitted. 7 is the low-order group side clock 3 which is subordinately synchronized with the high-order group clock 1.544 MHz.
The PLL circuit 8 that generates 92 kHz is a split circuit. Note that the operation of the reception pulse generation circuit 3b is based on the higher-order group side clock (1, 54
4 MHz), and the operation of the transmission pulse generating circuit 5b is regulated by the low-order group side black signal output from the PLL circuit 7, which is 392 kHz. Figure 1(d)
indicates the internal circuit of the dividing circuit 8, 8a (S/P) is a serial/parallel conversion circuit, 8b is a buffer storage device, and 8c (P
/S) is a parallel/serial conversion circuit, and 8d is a circuit U. Only one system PCM 6 (1) on the lower order group side of the above configuration is illustrated.

In the above configuration, one system of PCM24B system (O
HI, 2, 3. ...23, 24) are input from the right side, converted into a unipolar pulse train by the BU conversion circuit 1b, frame synchronization information is extracted by the frame synchronization detection circuit 2b, and the high-order group side clock (1,544 MHz)
The data is input to the serial/parallel conversion circuit 8a in the dividing circuit 8 as information data synchronized with the data. On the other hand, the reception pulse generation circuit 3b cooperates with the frame synchronization detection circuit 2b to detect the frame number and communication path number of the information data input to the serial/parallel conversion circuit 8a, and uses the information as a control signal for the conversion circuit. 8a in parallel. The serial/parallel conversion circuit 8a is connected to a predetermined communication path (in this case, CH
The MPU 8d converts only the information data of I′1, 2°, . It is stored in a predetermined address of the buffer storage device 8b according to the number. When the storage of all information data for one multi-frame is completed, the MPU 8d switches to the lower order group side (PCM
6 (1) Add an F pit to the beginning position of ), and from then on,
The information data regarding the frame numbers sequentially instructed by the transmission pulse generation circuit 5d is transferred from the buffer storage device 8b to the parallel/serial/serial conversion circuit 8C, where it is synchronized with the +J rack (392 kHz in this case) on the transmitting side. The signal is converted into a serial binary code string, and converted into a bipolar pulse string by the U-B conversion circuit 6B, and then outputted to the line as a PCM 6 (1) system.

As mentioned above, 9. Since the transmission format of the PCM6 system is set in accordance with that of the PCM24B system, the configuration of the multiplexing/division system between the two systems is extremely simple, especially every 6 frames. No special processing is required for the inserted signal bits (dial signals). In systems where the transmission formats for the high-order group side and the low-order group side are different, the signal bits are separated from the audio bits in the multiplexing/dividing device, stored in a temporary buffer storage device, and then incorporated into the transmission code string. A means is required.

In addition, transmission 7 of the higher-order group side system obtained by multiplexing
Since the output automatically matches that of the PCM24B system, it is possible to connect it not only directly to the PCM24B terminal station, but also to its higher-order group converter, which contributes to economical operation of the line network. becomes possible.

In addition, in the embodiment, a PCM6 system and a PCM2 system are used.
Although the case of the multiplexing/division method between the 4B systems has been described, the application of the present invention is not limited to this case, and the case where the higher-order group is, for example, the PCM30 channel method (European standard method), or It can be similarly applied to cases where the low-order group is in a system other than the PCM6 system.

〔Effect of the invention〕

In general, according to the PCM communication division method of the present invention as described above, the transmission format on the low-order group side is made to match that on the high-order group side, the clock on the low-order group side is slave-synchronized with that on the high-order group side, and the input Information data that is input in synchronization with the transmitter clock is temporarily stored in a buffer storage device in units of one multiframe, and after adding frame synchronization bits to this, a serial binary code string synchronized with the transmitter clock is generated. (In the case of multiplexing, it is converted into a single system, and in the case of division, it is multiple systems) and output, so the transmission format of the higher-order group side signal obtained by multiplexing is automatically changed to the transmission format of the desired existing system. It has become possible to match the existing system and connect directly to the terminal station of the existing system.

[Brief explanation of drawings]

Figure 1 (a) r (b) , Cc) + (d)・
. . . A diagram showing an embodiment of the present invention. (,)... A diagram showing a frame of a low order group (PCM 6 ) and a multi-frame. (b) A diagram showing the configuration of a multiplexing/division network. (c), (d)... Diagrams showing the internal configurations of multiplexing and dividing circuits, respectively. FIG. 2: A diagram showing the state of multiplexing and division of four systems of PCM 6 systems. Figure 3...
Higher order group (PCM 24 B ) and lower order group (PC!M
6) is a diagram showing a comparison of the frame configurations of 6). Figure 4...
- Conceptual diagram showing the flow of the reproduced clock. Figure 5 (,),
(b)...A conceptual diagram showing the transition of each communication path in multiplexing/division. Code table 1a, 1b-B-U conversion circuit, 2a,
2b - frame synchronization detection circuit, 3a, 3b.
. . . reception bar (to)) pulse generation circuit, 4 . . multiplexing circuit, 5a. 5b... Transmission pulse generation circuit, 6a, 6b No. U-
B conversion circuit, 7...PT, L circuit, 8...dividing circuit, 100...line, lOl...multiplexer,
102...Dividing device, 103...Clock regeneration circuit, 104-=PLL circuit, 105a, b, c
, d-PCM 6 terminal equipment.

Claims (1)

[Claims] The information content of a single PCM communication system input as a serial binary code string synchronized with a high-order group side clock is converted into a serial binary code string of multiple systems synchronized with a low-order group side clock (single). In the PCM communication system division method that converts and outputs the PCM, the transmission format on the low-order group side is set equal to that on the high-order group side, and the clock on the low-order group side is dependently synchronized with that on the high-order group side,
and temporarily storing the input information content as one multi-frame parallel binary code string in a buffer storage device, dividing the data into information content of a predetermined number of calls,
Each of them constitutes the information content of the low-order group side multi-frame, and after adding frame synchronization bits having a predetermined temporal pattern to each of the information contents, each is converted to the low-order group side clock. A dividing method for a PCM communication system characterized by converting into synchronized serial binary codes and outputting the converted signals.