KR900004474B1 - Electronic exchange interface circuit - Google Patents

Abstract

The apparatus for processing digital trunk function and alarm service includes a timing signal generator (200) for generating a first clock for data transmitting and a second clock for CCS data communication, a CCS porcessor (300) for transducing the first clock transmission speed of CCS data generated by data link processor to the second clock transmission speed and extracting CCS data having the second clock transmission speed by the first clock, a time switch unit (500) for switching the path of audio data, alarm and state data, and inserting and extracting CCS and CAS signal data, and a digital hybrid trunk unit (600) for interfacing the time switch unit (500) and opponent CEPT trunk.

Description

CEPT Digital Trunk Interface of Electronic Switching System

1 is a system block diagram of the present invention.

2 is a concrete block diagram of FIG.

3 is a concrete circuit diagram of FIG.

4 is an internal circuit diagram of a time switch of FIG.

FIG. 5 is a waveform diagram of a synchronization signal detection unit of a clock generator in FIG.

6 is an operation waveform diagram of the CCS processor of FIG.

7 is an internal circuit diagram of a digital trunk hybrid part in FIG.

8 is an information configuration diagram of the control interface of the digital trunk hybrid unit in FIG.

* Explanation of symbols for main parts of the drawings

100: control interface 200: timing signal generator

300: CCS processing unit 500: time switch unit

600: digital trunk hybrid unit 700: alarm and test unit

110: data buffer 120: address buffer

140: decoder unit 130: control buffer unit

160: weight generator 210: clock generator

220: frame synchronization signal generator 310: CCS insertion unit

320: CCS extraction unit 510: first time switch

520: second time switch 530: third time switch

610: DTH1 620: DTH2

630: DTH3 640: DTH4

710: AIS generating unit 720: alarm display unit

730: playback clock control unit 740: clock detection unit

The present invention relates to a digital trunk device of an electronic switchboard, and more particularly, to a device capable of processing digital trunk function and alarm service of a communication European depostes et Telecommunication (CEPT) method.

Currently used digital communication methods are time division multiplexing (CE) and NA (North America). The CEPT method and the NA method are distinguished as shown in Table 1 below.

TABLE 1

The digital trunk transmission method of the existing electronic exchange used in Korea is only available for NA method that transmits 24 channels per transmission line. Therefore, additional equipment has to be attached to perform CEPT data.

The International Telephone and Telegraph Consulative Committee (CCITT) recommends both methods, but when the NA and CEPT exchanges are matched, the CEPT method is followed. It is not a big problem for voice transmission by using bit robbing method, but it is not suitable for data transmission.It is not suitable for ISDN method (Integrated Service Digital Network) currently pursued. There was a problem with economic disadvantages.

It is therefore an object of the present invention to provide a CEPT digital trunk device in an electronic switchboard.

Another object of the present invention is to provide a CEPT digital trunk device capable of handling the alarm service recommended by the International Telegraph Advisory Committee.

Hereinafter, the present invention will be described in detail with reference to the drawings.

1 is a block diagram of the present invention, a control interface unit 100 for buffering a data address control signal and generating a data strobe and weight signal under the control of a CTPB (CEPT Trunk Processor Board), a processor (not shown), and a line concentrator. A timing signal generator for generating a frame format signal from a digital line concertrate (hereinafter referred to as DLC) and generating a system clock for signal transmission and a transmission / reception clock of CCS (common channel signaling) information. And CCS processing unit 300 for converting CCS information into 64Kbps / 2048Kbps bit rate and inserting and extracting into specific channel to communicate CCS information between remote station and switching station in CCS mode, and the control interface. The remote station switches the frame synchronization signal, signaling, alarm, control signal or voice and data by the signal of the unit 100. Time switch unit 500 for outputting CCS data during communication with the time switch unit 500 to exchange control and status information, voice data and CCS data of the trunk, digital data to reproduce the data and clock, and generate an alarm signal Trunk hybrid unit 600 and. It is composed of an alarm and text unit 700 to generate and display and test the AIS alarm, power and home alarms.

Based on the above configuration, the present invention will be described in detail with reference to FIG.

The 30 channel, voice data / data format of the CEPT method recommended in CCITT G 732 are shown in Table 2 below.

TABLE 2

In Table 2, a ^* is for international use, b ^* can be used for any channel for CCS (commomn channel signaling), and C is used for network synch (network synch) for domestic use.

The form of the CEPT 32 system will be described with reference to Table 1 above.

Channel 0 is used for frame array signal (even frame), remote alarm information (odd frame) and network information (international and domestic), bit allocation in odd frame is "X0011011", even frame Bit allocation in X is "X ₁ RJAY YYYY".

At this time, the even and odd frames X are for international use and Y is for domestic use for network synchronization, but is set to "1" when not in use.

Channel 16 is used for both CAS (Channel Associated Signaling) and CCS (Common Channel Signaling) signaling information transmission, multi-frame array signal, remote signaling alarm, and so on. Bit allocation is shown in Table 3 below.

TABLE 3

In channel 16 of frame 0, bit 6 is used for RSA (Remote Signaling Alarm), and when X bit is not used, it is set to '1' and abcd bit of frame 1-frame 15 is used for CAS signaling. B: When c and d bits are not used, b = 1, c = 0 and d = 1 are set.

In addition, the bit allocation with the remote switching center (RSS) uses CCS signaling without multiframe, and channel 16 transmits and receives signaling at 64 Kbps. Channel 1-channel 15 and channel 17-channel 31 are used for voice data or data transmission, and when the idle channel (idle channel) is inserted into the channel "1010100". Detailed description will be described later.

The outline of the present invention is as follows.

The apparatus of the present invention is housed in a Digital Trunk Interface Device (DTID), which is a Digital Trunk Interface functional block with a CEPT Trunk Processor Board (CTPB).

The device of the present invention, which performs all the functions of a digital trunk as a single board device using a hybrid circuit, can insert and extract signal information for both of CAS (Channel Associated Signaling) and CCS (Common Channel Signaling). . CEPT frame structure in time slot 0 (TS 0) on each subhighway by inputting frame sync signal and 4096KHz clock and four 32-channel subhighway bit streams from Digital Line Concentrator (DLC) The frame alignment signal is inserted and signal information is inserted into the time slot 16 (TS 16), and the voice data is transmitted to the other station via the line interface circuit together with the voice data.

On the other hand, it receives 32 channel data and signal information of 4 subhighways of other stations received through the transmission line, detects and processes various alarms, and separates voice data and signal information so that voice data is a trunk line concentrator ( It is output to Trunk Line Concentrator (TLC) and signal information is sent to Data Link Processor (DLP) for call processing. The time switch 500 performs insertion and extraction of signal information, insertion and extraction of various alarms and status information by the output of the control interface unit 100, and forms a passage for voice data and CCS data.

The digital trunk hybrid unit 600 connected to the time switch 500 performs all functions of the PCM digital trunk interface of the local station and the other station. The input source is the DLC demultiplexer which is the output of the local time switch 500. Bit streams and CCS information data output from DLP (local station is ELP, remote station is RLP), and various control information and signals which are outputs of the time switch 500 under the control of the control interface unit 100. Process information and output it through the CEPT link.

In addition, the input source processes the data received from the CEPT link at the time of the other station, and outputs voice channel data, CCS information data, and various alarm and signal information to the time switch 500.

At this time, under the control of the microprocessor controller, the control interface unit 100 outputs various signals by accessing the time switch 500. These control signals are the operation mode of the digital trunk hybrid unit 600, initial values for signal control, and CAS signal information. Alarm output control signal is output.

The timing signal generator 200 adjusts the frame synchronization supplied from the DLC demultiplexer to meet the system requirements because the state of the bit stream of the subhighway is different from the condition required in the system. MHz) and when the local exchange interfaces with the Remote Switching System (RSS), it transmits and receives RSS maintenance information and Inter Processor Communication messages using CCS. It is transmitted on (TS 16) at 64 Kbps and generates 64 KHz, which is an operation clock of the CCS insertion and extraction unit 300. In the CCS mode, the CCS processing unit 300 interfaces with the local exchange and the RSS, and inserting the CCS data transfers serial data, which is information to be transmitted from the ELP (Exchange Link Processor) to the RSS, by 64 Kbps by the output of the timing and clock generator 200. After receiving and converting the data into 8-bit parallel data, the system converts the data into 2048 Kbps serial data using the system transmission clock, which is output from the timing signal generator 200, and inserts the data into the time switch 500.

When the CCS data is extracted, the CCS data of time slot 16 (T.S 16) transmitted from the RSS is extracted from the second time switch 500, converted in the reverse order to the CCS data insertion order, and transmitted to the ELP of the local exchange.

The alarm and test unit 700 includes an alarm indication signal (AIS), an excessive error rate, a frame and multiframe alignment alarm, a remote alarm, and a remote junction alarm. (Remote Recovery Alarm: RJA), Remote Signaling Alarm (Remote Signaling Alarm: RSA), etc. generate and display, and also the recovery clock extracted from the timing signal generator 200 and the digital trunk hybrid unit 600 (recovery clock) Monitor).

FIG. 2 is a detailed block diagram of FIG. 1 and includes a control interface 100 including a data buffer 110, an address buffer 120, a decoder 140, a control buffer 130, and a standby signal generator 150. And a timing signal generator 200 composed of a clock generator 210 and a frame signal generator 220, a CCS processor 300 composed of a CCS inserter 310 and a CCS extractor 320, and a time switch S. 510, time switch unit 500 composed of time switch A 520 and time switch B 530, and DTH1 (601), DTH2 (602), and DTH3 (603). Digital trunk hybrid unit 600 composed of DTH4 (604), AIS generating unit (710), alarm display unit (720), replay clock control unit (730) and alarm detection unit (740). Configure.

The present invention will be described again with reference to FIG. 2, which is a specific block diagram of FIG.

The frame signal generator 220 which receives a clock and a frame synchronization signal of 4.096 MHz from the DLC has a condition that a bit stream state of a frame synchronization signal of the DLC and a subhighway (PSHW) are required internally according to the present invention. They are different and therefore fit to the appropriate conditions for the internal circuit switches SAB (510.520, 530) and DTH1-DTH4 (601-604).

In addition, the clock generator 210 inputs an output of 4.096 MHz, which is the output of the frame signal generator 220 and the DLC, to generate a clock of 2.048 MHz and 64 KHz, of which 2.048 MHz is a clock of the DTHl-DTIB4 (601-604). 64 KHz is supplied to the clocks of the CCS insertion unit 310 and the CCS extraction unit 320. CCS mode is used when the exchange interfaces with a remote switching system (RSS), and CAS mode is used when the exchange interfaces with a large station and trunk lines.

Therefore, DTHl-DTH4 (601-604) should be initialized to CCS mode or CAS mode during system initialization. The time switch S 510 and the time switches A and B 520 and 530 are controlled by a CTPB (not shown) to switch voice, data, and signaling information. The time switch S 510 uses a message mode to process signaling. In message mode, time switches A and B 520 and 530 initialize the normal mode to process voice data and data. That is, the time switch S (510) operates in the message mode, the time switches A, B (520, 530) in the normal mode through the data of the CTPB through the data buffer unit 110, the time switch S (510) and the time switch A The internal memory in B (520, 530) is selected to select a stream line at the stream bus input terminals STi0-STi4. In addition, the channel address of the selected stream line of the time switch S 510 and the time switches A and B 520 and 530 is designated by the address signal through the address buffer 120.

The time switches S, A, and B (510, 520, 530) receive various control signals through the control buffer unit 130. These control signals include read / write signals, data strobe signals, and chip select signals. The wait generator 150 generates a wait signal when the operation speed of the time switches S, A, and B 510, 52 0, 5 30 are different from the controller, and generates a wait signal through the control buffer 130. Output to CTPB. (The clocks used for the time switches S, A, B (510, 520, 530) are 4.096 MHz.)

In the above operation, in the CAS mode, the time switch 510 operates in the message mode, interfacing the signaling information of the power with the CTPB, the signaling information source with the DTH1-DTH4 (601-604), and the time switches A and B. (520,530) operates in normal mode to switch voice data and data of its own DLC to DTH1-DTH4 (601-604) and to switch voice data and data of a major exchange to its own DLC through DTHI-DTH4 (601-604). do.

In the CCS mode, the time switch 510 is not related to signaling, and a signal generated by a DLP (DATA Link Processor) of a Remote Switching Station (RSS) is output from an ELP (Exchange Link Process) of a RLP (Remote Link Processor) station of a RSS. CCS data inputted to the (STi4) terminal of the time switches A and B (520,530) through the CCS insertion unit 310 and inserted into the channel 16, and inserted into the channel 16 of the time switches A and B (520,530) and outputted to the STo4. This is output to the DLP of the local station through the CCS extraction unit 320.

In addition, the CCS data generated in the DLP of the home station is output to the DLP of the remote switching center (RSS).

Voice data and data or alarm and control information operate in the same manner as the CAS mode described above. As the input source of DTHI-DTH4 (601-604), control information and signaling information provided by CTPB inputted to control input terminal (CSTi0-CSTil) through time switch S 510, and time switches A and B ( 520, 530, and a bit stream input to a data input terminal (DSTi) or CCS information provided from a DLP. In addition, voice data and data of the power station received from the CEPT link or alarm control and signaling information are processed in DTHI-DTH4 (601-604), and then the voice data and data or CCS information in the CCS mode is the data output terminal (DST0). The pin is transmitted to the time switches A and B (520.530), and the CAS information in the CAS mode is transmitted to the time switch 510 through the control output terminal CST0.

DTHI-DTH4 (601-604) configured as described above can adjust the gain of transmission and reception, loop back function for each channel, definition of data channel or voice data channel, signaling mode setting of CAS mode or CCS mode, HDB3 (High Density) Bipolar 3) It performs coding and decoding function, frame arrangement function, retiming function and network information processing function. CEPT digital trunks output HDB3 signals over trunks, so they must be encoded as HDB3 signals when they are transmitted, decoded as HDB3 signals when received, and 2.048 MHz recovered from the received signals. retiming). The regeneration clock is also sent to the network synchronizer circuit and used as a reference clock for generating a system clock. In addition, frames are arranged in multi-frame transmission and frames are recovered in reception. The frame arrangement signal is carried on channel 0 of even frames. The retiming function is to bit-align the received data stream with the local clock. The retiming function loses the received data due to the phase difference that may occur between the local clock and the playback clock extracted from the received data. This is to prevent reading twice. In CAS mode, it inserts and extracts the signaling information transmission channel CHl6 to process CAS information, maintains and manages CAS memory, and also inserts and extracts channel 16 to exchange information between the local exchange and the remote switching center.

In addition, DTH1-DTH4 (601-604) detects and controls alarms generated by the alarm requirements recommended in CCITT.The types of alarms include Loss of Frame Alignment (LFA), Remote Junction Alarm (Remote Junction Alarm). : RJA) Loss of Multiframe Alignment (LMA) and Excessive Error Rate (ERR), Remote Signaling Alarm (RSA), Slip Alarm and AIS Alarm.

Accordingly, in the above alarm types, the frame array loss (LFA) alarm occurs when the frame array signal is three consecutive errors, and the frame array loss (LFA), overerror rate (ERR), and the alarm indication signal generated by the AIS generator 710 ( AIS) should be detected or the remote junction alarm (RJA) should be sent to the power station within 2msec when the service is in an out of service state and should be restored within 2ms when the alarm disappears. The multiframe array loss alarm (LMA) is generated when the multiframe array signal transmitted on channel 16 of the first frame (Frame 0) is received in error state twice in succession. It is released immediately. The remote signaling alarm (RSA) is an alarm that notifies the power station when a multiframe array loss alarm occurs in its own station. When the multiplexer array loss alarm is released, the remote signaling alarm is automatically released. Slip Alarm appears when slip occurs in the frame arrangement and retiming function.

The alarm indication signal (AIS), overerror rate (ERR), multiframe array loss (LMA) and frame array loss (LFA) are local alarms, remote signaling alarms (RSA) and remote junction alarms (RJA). ) Is a remote alarm, a local alarm is an alarm for a reception error, and a remote alarm is an alarm for a reception error. The alarm indication signal (AIS) is generated when the number of “0” s is less than three in two consecutive frames, and is caused by frame array loss (LFA), overerror (ERR) and AIS detection. This is also caused by the switch operation of the AIS generator 710.

The alarm indication signal (AIS) is also cleared when there are three or more "0s" in two consecutive frames.

When the alarm signal recommended by CCITT G 732 is generated in DTH1-DTH4 (601-604) as described above, the alarm display unit 720 controls the frame array loss (LFA) through the first time switch 510 under the control of the CTPB. The status of frame arrangement loss LMA, overerror rate ERR, alarm instruction signal AIS, remote signaling alert RSA, and remote junction information RJA are displayed. In addition, the regeneration clock control unit 730 inputs a regeneration clock of the DTH1-DTH4 (601-604) to output a regeneration clock and a 2048 Kbps signal loss alarm signal to a network synchronization device (NESD), and also a clock detection unit. 740 receives the system clock 4.048 MHz and the frame synchronization signal FS output from the DLC and continuously monitors these clocks, and outputs the result to the RAAB. 3 is a detailed circuit diagram of FIG. 2 and FIG. 3 is a concrete circuit diagram of the present invention. The data buffer unit 110 including the buffer 111 and the inverter 112 and the address buffer unit 120 including the buffers 121 to 123 are illustrated in FIG. ), A control buffer unit 130 comprising a buffer 131-133, a NAND gate 135, and an oragate 134, a decoder unit 140 comprising a decoder 141, 142, and an inverter 151-153. The NAND gates 154-156, the end gates 157, and the standby signal generator 150 composed of the buffer 158 correspond to the control interface 100, and the counters 211-212 buffer 213-. 215 and a clock generator 210 composed of NAND gates 216-219, buffers 221-222, inverters 223-226, latches 224-225, OA gates 227, and NAND gates 228. The portion formed by the frame synchronization signal generator 220 corresponding to the timing signal generator 200 corresponds to the parallel-parallel converter 311-312, the parallel-to-parallel converter 313-314 and the NAND gate 315-316. CCS inserts CCS composed of a unit 310, an inverter 321-322, an oragate 323-324, a serial-to-parallel converter 325-326, a parallel-to-parallel converter 327-328, and a NAND gate 329-330. The portion composed of the extraction unit 320 corresponds to the CCS processing unit 300, and includes the time switch S 510, the DTSA 521, the buffers 522-525, and the resistor 5R2 composed of the STSI 511 and the resistor 5Rl. The time switch A (520), the DTSB (522), the buffer (532-535) and the time switch B (530) composed of the resistor 5R3 correspond to the time switch (530) and DTH1-DTH4 ( The portion composed of 601-604 corresponds to the digital trunk hybrid portion 600, the AIS generating portion 710 composed of the switch 711 and the buffer 712, the latches 721-722, and the resistors 7Rl-7Rl6. , LED (LDI-LDl8), Inverter (7317-7320, 7325-7328), Nandgate (7321-7324, 7329-7332), Negative Oagate (7333-7336), Buffer (7337-7340) and Strap Switch ( Alarm display unit 720 composed of W3-W4), monostable multivibrator 7311-7312, buffer 7313- 7316) and a clock clock unit 740 composed of a regeneration clock control unit 730 composed of a strap switch (Wl-W2), a monostable multivibrator (741-742), an oragate (743), and a buffer (744). 4 is an internal circuit diagram and a mode selection method diagram of the time switches STS1, DTSA, and DTSB, and FIG. 5 is a synchronization signal detection waveform diagram that is an output of the timing signal generator 200. FIG. 6 is an operation waveform diagram of the CCS processing unit 300, FIG. 7 is an internal circuit diagram of the digital trunk hybrid DTH1-DTH4, and FIG. 8 is a configuration diagram of the control interface of the DTH1-DTH4.

Based on the above configuration, the present invention will be described in detail with reference to the third, fourth, fifth, sixth, seventh and eighth degrees of the present invention.

3 is a CEPT digital trunk circuit diagram capable of processing four lines of data and voice data.

DTSA 521 and DTSB 531 switch voice data and data of two lines, respectively, and insert or extract CCS information into 16 of 32 channels transmitted in each line in CCS mode. Interface control and signaling information with the CTPB.

STS1 (511) DTSA, B (521,531) which is connected to DTH1-DTH4 (601-604) and DLC and performs voice data and data path, insertion and extraction of signal information, extraction of various alarm and status information under the control of DTPB. Will be explained.

The internal circuit diagrams of the DTSA, B 521 and 531 and the STS1 511 are configured as shown in FIG. 4 (a). 2.048Mbps serial data is input to ST-BUS TM (Stil-STi7). Each serial input is 32CH of digital data and each channel is 8-bit data of PCM.

Each serial input is converted in parallel through a serial-to-parallel converter (SP) and stored in 256 × 8 bytes of data memory (DM), and the data stored in the data memory (DM) function as a time switch under the control of the CTPB. The connection memory consists of high connection memory (CMH) and low connection memory (CML), and has the same memory capacity as the data memory (DM). The output of the connection memory is serial data through a serial-to-serial converter (PS). After conversion to DTH1-DTH4 (601-604) through ST-BUS TM (STo0-STo7).

4 (b) is a functional explanatory diagram of FIG. 4 (a). The data D0-D7 of the CTPB through the 8-bit buffer 111 for data and the address signal A0- through the 6-bit buffer 121 for the address. The function of each time switch is performed by A5). The mode and each memory stream line can be selected according to the output of the control register (CR) by the CTPB data (D0-D7) through the buffer 111. The D7 bit is used in the split mode and D6 Bit is "High" transient message mode "low" is temporary normal mode, D5 bit is not used, D4, D3 bit is memory selection bit, 00 is not selected memory, 01 is selected data memory (DM) 10 selects the low connection memory (DML), 011 selects the high connection memory (CMH), and the D2-D0 bit selects eight stream lines as the ST-BUS TM select bit.

The 32-channel signal of each ST-BUS can be selected by the address signals A0-A5 through the buffer 121. Here, the STS1 511 initializes the message mode and outputs data written to the low connection memory in the CTPB to each DTH1-DTH4 (601-604), and writes to the data memory (DM) in each DTH1-DTH4 (601-604). The sent data is sent to CTPB, and the data here means signaling information, various alarms, and control information. In addition, DTSA, DTSB (521, 531) initializes the normal mode, switches local data through DLC, outputs to DTH1-DTH4 (601-604), and outputs DTH1-DTH4 (601-604) that outputs data received from a large station. Is switched to the DLC, and the data here refers to voice data and data. In the CCS mode, the STS1 511 does not use the signaling information and inserts various control information and signaling information into the channel 16 of each frame and transmits them.

)신호와 라이트(

)신호를 부논리곱하는 낸드게이트(135)에 의해 STS1(511),DTSA, B(521,531)의 데이타 스트로브(data strobe)가 결정되며 버퍼(133)를 통한 칩 선택 신호(

)에 의해 인에이블하는 디코더(141)는 버퍼(122. 123)를 통한 어드레스 신호(A8, A9)를 디코딩하여 각각의 출력(Q0-Q2)으로 STS1(511) DTSA,B(521,531)를 선택한다. 또한 STS1(511), DTSA. B(521, 531)의 칩 선택신호(

)를 반전하는 인버터(151-153)의 출력과 데이타 액크널리지(

)신호를 각각의 낸드게이트(154-156)를 사용하여 부논리곱하고 각각 낸드게이트(154-156)의 출력을 앤드게이트(157)를 이용하여 논리곱한 후 버퍼(158)를 통해 CTPB로 대기신호(wait)를 출력한다.Read CTPB through buffers 131 and 132

Signals and lights

The data strobe of the STS1 511, DTSA, and B (521, 531) is determined by the NAND gate 135 that negatively multiplies the signal, and the chip select signal through the buffer 133 is determined.

Decoder 141, which is enabled by the A / B, decodes the address signals A8 and A9 through the buffers 122 and 123, and selects STS1 511 DTSA and B 521 and 531 as respective outputs Q0-Q2. do. See also STS1 511, DTSA. Chip selection signal of B (521, 531)

) And the output of the inverter (151-153)

) Negatively multiply the signals using the respective NAND gates 154-156, and output the NAND gates 154-156 using the AND gate 157, respectively, and then wait for a CTPB through the buffer 158. Print (wait)

The reason for generating the standby signal as described above is that the data processing speed of the CTPB is the STS1 511. DTSA. It is faster than the data processing speed of B (521, 531), which gives a CTPB a wait signal. The data strobe signal is generated according to the data acceleration signal.

The OR gate 134 for inputting the chip select signal of the buffer 133 and the read signal of the buffer 131 buffers the CTPB and the data (D0-D7) of the STS1 511, DTSA, and B (521,531) in both directions. The transfer direction of the 8-bit buffer 111 is controlled. In addition, another decoder 142 enabled by the output Q3 of the decoder 141 decodes the address signals A4 and A5 through the 6-bit buffer 121 so that Q0 of the outputs Q0-Q3 is Q1 is the clock signal of another 8-bit latch 722, Q2 is the enable signal of the tri-state buffer 711 for AIS generation, and Q3 is the clock signal of the 8-bit latch 721. After inverting, the bidirectional tri-state 8-bit buffer 111 is enabled. (At this time, "00," "01", "10" signals are frequently applied to A8 and A9.)

MHz의 클럭과 프레임 동기신호(F.S)가 버퍼(222-221)를 통해 제5도의 (a)와(c)같이 래치(224)의 클럭과 데이타단에 입력하면 래치(224)는(e)와 같이 지연 출력되며 래치(224)의 출력을 데이타 단으로 입력하는 래치(225)는(a)와 같은

MHz의 클럭에 의해(f)와 같이 출력한다.From DLC

When the clock and frame synchronization signal FS of MHz is inputted through the buffers 222 to 221 to the clock and data terminals of the latch 224 as shown in (a) of FIG. 5 (a), the latch 224 is (e). As shown in (a), the latch 225 for delayed output and inputting the output of the latch 224 to the data stage is

It outputs as (f) by the clock of MHz.

)를 출력하는데 상기(g)와 같은 프레임 동기신호를 발생하는 이유는 DLC로부터 공급받는 프레임 동기신호와 서브 하이웨이(PSHW)의 비트 스트림의 상태가 STS1(511) 및 DTSA. B(521,531)와 DTH1-DTH4(601-604)의 내부에서 필요로 하는 조건과 상이하므로 DLC에서 제공하는 신호를 받아 상기 회로들이 요구하는 조건으로 맞추기 위함이다.The NAND gate 228 inputting the output of the latches 224 to 225 combines the two inputs (g) to give an inverted frame synchronization signal such as

The reason for generating the frame synchronization signal as shown in (g) is that the state of the frame synchronization signal supplied from the DLC and the bit stream of the sub highway (PSHW) is STS1 511 and DTSA. Since it is different from the conditions required inside B (521,531) and DTH1-DTH4 (601-604), it is for receiving the signal provided by the DLC and matching the conditions required by the circuits.

)는 카운터(211-212)를 클리어 시키며 인버터(223) 출력인

MHz를 분주하는 카운터(211-212)중 카운터(211)는

MHz를 출력하여 버퍼(213)를 통해 CCTB(Code Conversion Trunk Board)로 출력하며 인버터(214)와 버퍼(215)를 통한 2.048MHz를 테스트 포인트(Test point 1 : TP1)로 사용하며 또한 CCS삽입부(310) 및 CCS 추출부(320)의 클럭으로 사용한다. 카운터(212)는 64KHz를 출력하며 CCS데이타를 DTSA, B(521,531)의 스트림 버스 입력 및 출력중 채널 16에 삽입 및 추출하기 위한 CCS삽입부(310) 및 CCS추출부(320)의 병렬 및 직렬 변환 클럭으로 사용한다.The frame synchronization signal of the NAND gate 228 (

) Clears the counters 211-212 and outputs the inverter 223.

Among the counters 211-212 which divides MHz, the counter 211 is

Outputs MHz and outputs CCTB (Code Conversion Trunk Board) through buffer 213, using 2.048MHz through inverter 214 and buffer 215 as a test point (Test point 1: TP1), and also inserts CCS It is used as a clock of the 310 and the CCS extraction unit 320. Counter 212 outputs 64KHz and parallel and serial CCS inserter 310 and CCS extractor 320 for inserting and extracting CCS data into channel 16 during stream bus input and output of DTSA, B (521,531). Used as a conversion clock.

Referring to Figure 6, the insertion and extraction of the CCS data will be described. When the system interfaces with a remote station, the serial-to-parallel converter is used to transfer data (maintenance information, IPC messages, signaling) from the DLP (system: ELP, remote station: RCP) to the remote station using a 64KHz clock such as (j). (311, 312). The serial-to-parallel converters 311 and 312 convert the received serial data into 8-bit parallel data, and then load the serial-to-parallel converters 313 and 314 by using a frame synchronizing signal Fo, as shown in (b). The data loaded in parallel is converted to serial data at 2.048 Mbps using a 2.048 MHz system clock as in (d) and applied to ST-BUS TM (STi4) of DTSA and B (521,531). At this time, DTSA, B (521, 531) inserts CCS data into 16th of 32 channels of input ST-BUS TM (STi0-STil) from DLC, and controls CTPB through data buffer 111 and address buffer 121. Receive. The CCS data is then loaded on channel 16 and applied to the data input terminal (DSTi) of DTH1-DTH4 (601-604) via the output ST-BUS (STo0-STol) of DTSA, B (521,531). Is sent to the station. At this time, if the data transmitted from the remote station is applied to the ST-BUS TM (S Ti2-STi3) of DSTA, B (5 2 1,531) through the output data terminal DST0 of DTH1-DTH4 (601-604) In the reverse order of data insertion, data is sent to the DLC through STO2-STO3, and the CCS data of channel 16 is extracted and applied to the serial-to-parallel converters 325 and 326 through STO4.

MHz의 클럭으로 CCS데이타를 입력하여 병렬데이타로 변환한다. 병직렬 변환부(327,328)는

MHz를 반전한 인버터(226)의 출력과 2.048MHz를 오아게이트(237)를 통해 논리합한 후 오아게이트(237)의 출력과 (K)와 같은 DTSA,B(521,531)의 CST0출력을 논리합한 (1)과 같은 오아게이트(323,324)의 병렬 로드신호에 의해 직병렬 변환부(325,326)의 출력을 로드한다. (CSTo 출력은 DSTA,B(521,531)를 초기화할시 매 타임슬롯 16에서 "로우"신호를 출력하도록 초기화 시킨다)The serial-to-parallel converters 325 and 326 are connected via an inverter 322.

Convert CCS data into parallel data by clocking in MHz. Parallel-to-serial conversion unit (327,328)

The OR of the output of the inverter 226 which is inverted MHz and 2.048 MHz are ORed through the oragate 237, and then the OR of the ORA 237 and the CST0 output of the DTSA, B (521,531) such as (K) ( The outputs of the serial-to-parallel converters 325 and 326 are loaded by the parallel load signals of the orifices 323 and 324 as shown in 1). (CSTo output initializes to output "low" signal in every time slot 16 when DSTA, B (521,531) is initialized.)

KHz 클럭에 의해 64kbps의 CCS데이타를 DLP로 출력한다. DTH1-DTH4(601-604)의 입력 소스(input source)로서는 CTPB에서 제공되는 제어 및 시그날링 정보를 출력하는 STS1(511)과, DLP로부터 출력하는 비트 스트림 및 CCS모드시 DLP에서 출력하는 CCS데이타를 출력하는 DTSA,B(521,531)이며, CEPT링크로부터 수신되는 대국데이타가 있다. 이때 DTH1-DTH4(601-604)는 CEPT링크로부터 수신한 데이타를 처리하여 음성데이타 및 데이타는 DST0를 통해 DTSA,B(521,531)로 인가되며 CAS시그날링 정보는 CST0를 통해 STS1(401)로 인가된다. DTH1-DTH4(601-604)는 입력정보 및 데이타에 의해 송수신 패스의 이득 조정, 채널별 루프백 기능, 데이타 채널 또는 음성데이타 채널의 정의, CAS 또는 CCS모드의 시그날링 모드 설정, 로칼 및 원격 경보 전송 및 검출, 일래스틱 버퍼(elastic buffer)에 의한 슬립제어, 수신데이타로부터 클럭추출, 라인드라이브 및 수신(line drive 및 receive), 6dB패드제공, 각종 경보 및 상태(status)제공등의 기능을 수행한다.The parallel-to-serial converters 327 and 328 convert the parallel COS data in series and then convert the parallel COS data into series.

The KHz clock outputs 64 kbps of CCS data to the DLP. As an input source of the DTH1-DTH4 (601-604), the STS1 511 outputting control and signaling information provided by the CTPB, the bit stream output from the DLP, and the CCS data output from the DLP in CCS mode. DTSA, B (521, 531) for outputting the data. At this time, DTH1-DTH4 (601-604) processes the data received from the CEPT link so that voice data and data are applied to DTSA, B (521,531) through DST0, and CAS signaling information is applied to STS1 (401) through CST0. do. DTH1-DTH4 (601-604) is the input and data gain adjustment of the transmission and reception pass, loopback function for each channel, definition of data channel or voice data channel, signaling mode setting of CAS or CCS mode, local and remote alarm transmission And detection, slip control by elastic buffer, clock extraction from received data, line drive and receive, 6dB pad provided, and various alarms and status. .

7 is an internal configuration diagram of DTH1-DTH4 601-604. The process of transmitting voice data and data and control and signaling information will be described. Voice data or data outputting STO0-STO1 of DTSA, B (521) (531) enters the data interface (DI) through the data input terminal (DSTi), and STO1, STO3, STO5, STO7 of STS1 (511) The various control information outputs enters the control interface Cl through the control input terminal CSTi0, and the signaling information outputs STO2, STO4, STO6, and STO8 of the STS1 511 is signaled through the control input terminal CSTil. Enter control interface Cl with ring bits A, B, C, and D.

The digital attenuation ROM (DAR) processes the data according to the attenuation information for each channel by the output of the data and control interfaces (DI, CI). At the time of channel definition, the digital temporal attenuation is disabled instead of the voice data.

The CEPT format selector (CFM) multiplexes the voice data or data stream through the digital attenuation rom and outputs it to the CEPT link interface (CLI). The ABCD RAM SBR stores the formatted forward or backward signaling bits A, B, C, and D. At this time, the CEPT link interface (CLI) inserts control and signaling information into the channel 16, and outputs the completed CEPT data on the CEPT link through the bipolar line transmitter (BLI). At this time, the bipolar line transmitter (BLT) converts the NRZ data into bipolar data for transmission on the CEPT link. The bipolar line transmitter (BLT) synchronizes with a 2.048 MHz clock such as (a) which is input to C2i. After converting into 2-rail RZ Unipolar data such as (c) and (d), and converting these (c) and (d) data again into a bipolar signal as shown in Fig. (E) It transmits on the CEPT link through PAD0 and TXG.

A process of receiving reception information on a CEPT link will be described. First, the clock extracting unit E extracts the clock of the power system from the received data and synchronizes the data received at the power station with the signal of E20 outputted to E20. Variable inductors (6A5, 6B5, 6C5, 6D5) are installed externally to extract the receive clock. The falling edge of the receive clock occurs at the nominal center of the output of the receive data RXD. The receive clock (2.048 MHz) Connect an inductor that can vary between LA and LB to extract. The 8KHz extraction clock (E8K0) is driven by the E20 clock and used in an external phase-locked loop to generate the system clock.The regeneration clock (2.048MHz) output to E20 allows the signal to synchronize the network. Output to NESD (Network Synchonization Device).

When the reception clock of the clock extractor (CE) is equal to (a), the bipolar line receiver (BLR) inputs bipolar data such as RxT and TxR terminals from the CEPT link (b), and the bipolar data is inputted to the RxA terminal (c). NAND gates (6A, 6B, 6C, and 6D), which are output as shown in (R) and output through RxB and (R), and input to the outputs of RxA and RxB, are converted into NRZ pulses and applied as RxD terminals as (ㅁ). . After converting the CEPT method data to NRZ through the bipolar line receiver (BLR) and applying it to the CEPT link interface (CLI), the CEPT link interface (CLI) receives the clock (E20) of the clock extracting unit (CE) extracted from the received information. Separate received information with.

That is, the reception data is separated from the synchronous signaling and alarm information, and the reception data is output to the elastic buffer (EB) to check the phase difference between the transmission (self) clock and the reception (power) clock to control slip.

The data through the elastic buffer EB is output to the STi3-STi4 terminals of DTSA and B (521,531) through the data output terminal DST0 through the digital attenuation ROM (DAR) and the data interface (Dl).

The synchronous signaling and alarm information separated from the received information are output to the STi0-STi3 terminal of the STS1 511 through the STS0 of the control interface CI via the ABCD bit ram SR and the control logic CL.

First, a process of interfacing voice data and data will be described.

DTH1-DTH4 (601-604) inputs serial data of 32 time slots, which are outputs of STO0-STO1 of DSTA, B (521,531) through DSTi pin, so that time slot 0 and time slot 16 of 32 time slots control interface. Only 30 channels are effectively used as data channels without inserting the synchronization signal and signaling information through them. In CCS mode, time slot 16 input to DSTi becomes the active channel and is transmitted through time 16 of the CEPT link. do.

Second, control interfacing will be described.

All control and signaling information required for DTH1-DTH4 (601-604) is input through two control inputs (CSTi0, CSTil), respectively, and each control input consists of 32 time slots, so each voice and data channel or signal It has control and signaling information for the ring channel.

A description of the input of SCTiO as shown in FIG. 8 (a) during control interfacing is as follows.

(Aa) is information of CSTi0 for T.S0-T.S14 and TS14-TS31. B7 of the information is a function of channel definition. If this bit is set to '1', the corresponding TS of the CEPT link is treated as a data channel. Digital Attenuation and Alternate Digit Inversion (ADI) functions are disabled and b6 is a loop function. When this bit is set to '1', the TS on the CEPT link ignores the data transmitted from the remote station. The transmitted data is received tapped.

b5-b3 is a Receive Path Gain Control function that can attenuate the signal size appropriately as eight attenuation values for each channel for received digital data. Appear together

TABLE 4

b2-b0 can be appropriately attenuated as eight attenuation values for the digital data transmitted as the transmission pass gain control function, as shown in Table 5 below.

TABLE 5

(Ab) is CSTiO information input for T.S15, b7, b5, and b4 are test bits and are set to "1" during normal operation, and b6 is a loop function of T and S16, and b6 is "1". "The date and time, the transmitted T.S16 is received looped and b3-b0 is a no-debounce function for the signaling bits. When b3-b0 is set to" 1 ", the received signaling bit AD is If not debounced but these bits are set to "0", the AD bits are debounced for 6-8 ms.

(Ac) is CSTi0 information input for T.S31, b7-b6 are test bits. B7 is set to 1 and b2 is set to 0 in normal operation. B5 is CCS function. If b5 is 0, DTH1-DTH4 (601-604) Inputs signaling information of T.S16 through CSTi by operating in CAS mode, and when b5 is set to "1", DTH1-DTH4 (601-604) operates in CAS mode and inputs DS. It becomes the active channel, transmits CCS information, and outputs signaling information transmitted from a remote station through channel 16 of DST0. In addition, b4 is an 8KHz selection function.When b4 is set to "1", 8KHz clock signal synchronized to CEPT 2.048Mbps link is output through E8K0 of DTH1-DTH4 (601-604). If b4 is "0", E8K0 pin is high. In case of high impedance, b5 is set to 1 and all information is transmitted (All 1S Alarm). If b3 is "1", 32CH on CEPT Link sends alarm signal to 1 and b2 is TS 16. When b2 is set to "1" as All IS Alarm transmission, it transmits the alarm signal that all CH1 data on CEPT Link is "1". Bl is the XCTL control function. When bl is set to 1, DTH1-DTH4 (601-604) The XCTL is driven high, and if bl is 0, the XCTL of DTH1-DTH4 601-604 is driven low.

Description of the CSTil as shown in FIG. 8 (b) of the control interface is as follows.

(Ba) is CSTil information input for T.S0, and b7-b4 is a multiframe alignment, which contains data of T.S16 b7-b4 of frame 0. These bits correspond to a multiframe array signal. All must be set to "0" and b3, bl, b0 are extra bits and b3, bl. b0 contains T.S16, b3, bl, b0 of each frame 0. If not used, all bits are set to "1" and b2 is RSA (Remote Signaling Alarm) and contains T.S16 b2 data of frame 0. In case of loss of multi-frame array signal, b2 is set and alarm is sent to the power station.

(Bb) is CSTil information input for T.S1-T.S15, where T.S1-T.S15 contains T.S16 CAS signaling information of frames 1 to 15, of which b7-b4 is Contains T.S16 CAS signaling information A, B, C, D of frame N and b3-b0 contains CAS signaling information A, B, C, D of T.S16 b7-b4 of frame N + l5. .

In this case, it may be confused with "0" which is a multiframe signal, so that A, B, C, and D should not all have a combination of signaling bits of "0", so B, C, and D bits are not used. Set to = 1, C = 0, D = 1.

(Bc) is information input of CSTil to T.S16, where T.S16 includes T.S0 information of the frame array signal, of which b7 is an international use bit, and T.S0 of the frame array signal. Contains b7 data, which is a bit reserved for international use and is set to "1" when not in use, and b6-b0 contains T.S0 b6-b0 of the frame array signal, which is used as a frame array pattern signal. Therefore, it should be set to "11011".

(Bd) is CSTil input information for T.S17, where T.S17 includes T.S0 information of a non-frame alignment signal, of which b7 is an international bit and b7 of non-frame arrangement This bit contains data, which is reserved for international use and is set to "1" when not in use, and b6 is the frame array bit and contains the b2 data of the frame array and is set to "1". b5 is RJA (Remote Junctkon Alarm) and contains b5 data of non-frame array. This bit is used to send alarm to remote station when local alarm occurs. It is set to 1 when sending alarm and normal operation date and time is "0. B4-b0 is a domestic bit and contains data of b4-b0 of the non-frame array, and these bits are set to "1" when not used for domestic purposes. Description of the output of the CST0 as shown in FIG. 8 (c) of the control interface is as follows.

CST0 of DTH1-DTH4 (601-604) contains information such as a multiframe array pattern, signaling bits A, B, C, D frame array pattern, and non-frame array bit received on the CEPT link.

(Ca) is T.S0 information for SCT0, and b7-b4 is a received multiframe array signal and includes a multiframe array pattern of T.S16 b7-b4 of frame 0 received on a 2.048 Mbps CEPT link, and b7-b4. Is normal if "0" and b3, bl, b0 are the receive extra bits and contain the T.S16 b3, bl, b0 data of frame 0 received on the 2.048 Mbps CEPT link and b2 is the 2.048 Mbps CEPT link as the receive RSA. It contains the T.S16 b2 data of frame 0 received at. This bit is used as a remote alarm bit to inform the station from the remote station when the remote station receives the multiframe array in error.

(Cb) is CST0 information for T.S1-T.S15, and T.S1-T.S15 of CST0 includes ABCD data in which each frame received on a 2.048Mbps CEPT link for each TS is T.S16 CAS signaling bits. Among them, b7-b4 is the received CAS information (frame N), which is the signaling bits of T.S16 b7-b4 of frame N (N = 1,2 .................. 15) received on a 2.048 Mbps CEPT link. , B, C, and D, and b3-b0 is the received CAS information of frame N + l5 and A, B, C, and D, signaling bits of T.S16 b7-b4 of 2.048 Mbps CEPT link frame N + 015. It includes.

(Cc) is CST0 information for T.S16, and CST0 T.S16 contains T.S0 data of a frame array signal received on a 2.048Mbps CEPT link.

b7 contains the b7 data of the frame array signal. This bit should be set to 1 when not used for international use. b6-b7 contains the T.S0 b6-b0 data of the frame array signal as the receiving frame array pattern. These bits must be set to "0011 011" as the frame array pattern signal.

(Cd) is T.S17 information for CST0, and T.S17 of CSTO includes T.S0 data of non-frame array received on 2.048Mbps CEPT link.

b7 contains the T.S16 b7 data in the non-frame array. This bit must be set to "1" when not in use for international use, and b6 contains the b6 data of the non-frame array and set to "1". B5 is the receiving RJA and contains the T.S16 b5 data in the frame array. This bit is used as a remote alarm bit to inform the local station when a local alarm occurs or an AIS alarm is received. b0 contains the b4-b0 data of the non-frame array. These bits must be set to "1" when not in use for domestic use.

(Ce) is T.S18 information for CST0, which contains a number of alarm information indicating the operation status of the CEPT interface. Among these, b7 is a frame array alarm. If the frame array signal is received three times in error, it is determined as a frame array loss state and is set to "1", and b6 is a multi-frame array signal two times in a row. If it is received in error state, it is judged as multi-frame array loss state and b6 is set to "1" F and b5 is an over-error rate alarm, which changes the state of b5 when an over-error rate occurs. If it is received, it is determined that an over-error rate alarm occurs and toggles b5 state to be inverted from the previous state. B4 is a sleep alarm that changes the state of b4 when a sleep occurs. Toggle to reverse the state of b3 and b3 is the All 1S Alarm that is triggered when all bits enter "1". B3 is set to 1 when data of channel is received as "1", b2 is AIS alarm of receiving T.S16. If all T.S16 data of every frame is received as 1, b2 is set to 1 and bl is DTH1-DTH4. (601-604) and the XS pin state are sampled once for every prime.

출력을 각각 입력하는 리트리거블 모노쇼트(7311-7312)는(DTH1-DTH4)의

의 출력 펄스 상태에 따라 펄스를 발생하며 모노쇼트(7311-7312)의 출력은 스트립 콘넥타(W2)의 입력단으로 인가된다. 여기서 스트립 콘넥타(W2)는 스트랩 콘넥타(Wl)와 연동으로 동작하며 스트립 콘넥타(W2)의 출력단(A,B)를 통한 신호가 버퍼(7315-7316)를 통해 NESD의 정보신호로 인가된다.In DTH1-DTH4 (601-604) as described above, the reception clock signal through each E20 terminal is connected to four input terminals of the strap connector (Wl), and two of the four inputs are selected. The A and B outputs of the strap connector Wl are applied to the NESD reference clock through the buffers 7313-7314. That is, two clocks among four received clocks reproduced through the four-line CEPT link are selected and output to the NESD. Also, as in (c) of FIG. 9 (b), DTH1-DTH4 (601-604)

The retriggerable mono shorts (7311-7312) for inputting the output respectively are (DTH1-DTH4)

A pulse is generated in accordance with the output pulse state of the output and the output of the mono short (7311-7312) is applied to the input terminal of the strip connector (W2). The strip connector W2 operates in conjunction with the strap connector Wl, and a signal through the output terminals A and B of the strip connector W2 is applied as an information signal of the NESD through the buffers 7315-7316.

의 출력에 이상이 생기면 NESD 경보를 동작하게 된다. AIS란 경보지시신호(Alarm Indication Signal)로 상술한 바와같이 대국에서 수신한 데이타에서 추출해내는 대국 AIS 신호와 자국에서 시스템 운용자가 AIS 발생스위치(711)를 조작하여 발생시킬 수 있는 자국 AIS 신호가 있다.So of each DTH

If an error occurs in the output of the NESD alarm will be activated. AIS is an alarm indication signal (Alarm Indication Signal) as described above, there is a large AIS signal extracted from the data received from the large station and the local AIS signal that can be generated by the system operator in the local station by operating the AIS generation switch 711. .

AIS generation switch 711 is composed of four (7SWl-7SW4) according to the number of CEPT links, and when one switch is pressed generates an AIS signal on the corresponding CEPT link. If the user presses any of the switches for the AIS generation switch (711) (SWITCH ON), one of the local AIS signal input terminals 51-54 of the OA gate (i.e., NAND gate) 7333-7336 having the inverter attached to the front end. It acts as the input to the gate and this output reports to the RAAB through the corresponding buffer of butters (7337-7340). On the other hand, the CTPB periodically reads the signal state of the switch input to the buffer 712, and controls A111S data to be transmitted to the corresponding CEPT link that is switched on. At this time, if the AIS signal of the power data is detected by the DTH1-DTH4 (601-604) as described above, the CTPB recognizes the power AIS signal of the corresponding line through the STS1 401, and the CTPB operates the latch 722 to operate the CTPB. The display data of the display elements LD9-LDl2 are driven by the output data of the display device LD9-LDl2, and is simultaneously applied to the AIS signal input terminal of the NAND gates 7333-7336 to report that the AIS has occurred. When AIS data is received from the remote station, it handles the alarm at the same station as above and sends RJA alarm to the remote station.

MHz의 클럭을 단안정 멀티바이브레이터(742)로 입력하여 발생한 두 신호의 출력을 오아게이트(743)에 인가시키며 오아게이트(743)의 출력을 버퍼(744)를 통해 RAAB로 송출하여 현재 사용하고 있는 클럭 및 동기신호 상태를 검사한다. 또한 카운터(212)에서 출력하는 64KHz의 클럭을 상술한 바와같이 한 링크당 30채널의 음성 데이타 및 데이타를 전송하는 CEPT 방식의 교환기와 복잡한 채널 변환 장치를 사용하지 않고 인터페이스를 용이하게 사용할 수 있으며 이에따라 채널을 경제적으로 사용할 수 있고 종합 정보 통신만의 데이타 통신에도 적합하게 사용할 수 있으며 트렁크 한 모듈당 5개의 링크로 120채널의 데이타를 처리하던 것을 4라인으로 처리할 수 있어 보드수를 감소할 수 있으므로 시스템을 소형화할 수 있고 마이크로 프로세서(CTPB)와 직접 인터페이싱을 수행할 수 있으므로 기존 방식에서 할 수 없는 보드 기능 테스트를 수행할 수 있으며 각종 경보를 용이하게 추출하여 표시할 수 있으므로 시스템의 신뢰도를 향상시킬수 있는 이점이 있다.When RSA or RJA occurs in the received information, the CTPB controls the decoders 141 and 142 to operate the latch 722, and the display element of the corresponding line of the display elements LDl3-LDl6 is controlled by the data of the CTPB through the buffer 111. At the same time, the RSA or RJA signal from latch 722 is applied to inverter 7325-7328, and the output of inverter 7325-7328 reports the occurrence of RJA or RSA to RAAB while simultaneously strapping NAND gates 7329-7332. Output to P (local time ELP, remote station time RLP) through connector W4. In addition, when the CTPB recognizes the frame array alarm or the multi-frame array alarm, the decoders 141 and 142 control the latches 721 and the corresponding display elements of the display elements LD5-LD8 are driven according to the data of the CTPB. (7317-7320) and the output of the inverter (7317-7320) to the RAAB to report the frame and multi-frame array information of the line, while output to the DLP through the NAND gate (7321-7324) and strap connector (W3) do. To check the state of the clock, the frame synchronization signal FS through the buffer 221 is input to the monostable multivibrator 741 and through the buffer 222.

The clock of MHz is input to the monostable multivibrator 742 to output the two signals generated to the oragate 743 and the output of the oragate 743 is sent to the RAAB through the buffer 744 and is currently being used. Check the clock and sync signal status. In addition, as described above, the clock of 64KHz output from the counter 212 can easily use the interface without using a CEPT exchanger and a complicated channel conversion device that transmits 30 channels of voice data and data per link. The channel can be used economically, and it can be used for data communication only in general information communication, and the number of boards can be reduced by processing 120 channels of data with four lines per module per trunk in 4 lines. The system can be miniaturized and directly interfaced with the microprocessor (CTPB) to perform board function tests that cannot be done in the conventional way, and to easily extract and display various alarms, improving the reliability of the system. There is an advantage to that.

Claims (6)

In the CEPT digital trunk access device of an electronic switchgear, it interfaces with the processor that controls the CEPT trunk and outputs the operation mode of the CEPT digital trunk, signal control initial value, CAS information, alarm control signal, etc., and CAS information from the remote station. And a control interface unit 100 for inputting alarm status information to the CEPT trunk processor and generating a frame synchronization signal of a different condition that requires the system to provide a frame synchronization signal provided by the digital concentrator. And a timing signal generator 200 for dividing a system clock to generate a first clock for data transmission and a second clock for transmitting and receiving CCS information. Interfacing with the data link processor in the CCS mode, converts and inserts CCS information having the transmission rate of the first clock generated by the data link processor by the clock of the timing signal generator 200 into the second clock transmission rate, and inputs the inputted second data. The CCS processing unit 300 converts and extracts CCS information having a transmission rate of 2 clocks into the first clock transmission rate and transmits the CCS information to the data link processor, and the timing signal generator 200 under the control of the control interface 100. Switching the path of the voice data input from the digital concentrator and the power by a clock, switching the control interface unit 100 and the extraction of various alarms and status information, and inserting the CCS processing unit 300 and CCS information in CCS mode. The time switch unit 500 performs extraction and inserts and extracts CAS signal information in the CAS mode, and the CEPT trunk of the time switch unit 500 and the power station. A digital hybrid trunk 600 for interfacing and reproducing data and clocks received by the clock of the timing signal generator 200, extracting alarm and status information, and extracting voice data and CCS data; It displays the AIS alarm by the interface unit 100 and the time switch unit 500 and the alarm occurrence of the power station and the local station, applies a regeneration clock to the network unit circuit, and simultaneously tests the clock of the timing signal generator 200. Circuit and alarm characterized in that consisting of the alarm and test unit 700 output to the rack alarm access board. The data buffer unit of claim 1, wherein the control interface unit 100 buffers data in both directions under the control of the CEPT trunk processor so that the CEPT trunk processor accesses the time switch unit 500 to control the system. And an address buffer unit 120 that buffers the address signal, and a read / write signal buffered to generate a read / write signal, and at the same time, the data strobe signal is generated by negatively multiplying the two signals to generate a read signal and a chip select signal. Decodes the control buffer 130 and the predetermined output of the address buffer 120 and the chip select signal of the control buffer 130 to determine the corresponding time switch. The decoder 140 generating the first, second, and third decoding signals by the signal, and the corresponding time switch after inverting the chip select decoding call of the decoder 140. Data acknowledgment widely paper and negative logic multiplying apparatus characterized in that it consists of a wait signal generator 150 for generating a wait signal to when the processing speed between CEPT trunk processor and a timer different from that in the output. The clock generator 210 of claim 1, wherein the timing signal generator 200 inputs 4 MHz, the system clock, from the digital concentrator to generate a first clock of 2 MHz and a second clock of 64 KHz for transmitting and receiving CCS information. Receiving the 4MHz of the system clock and the frame sync signal from the digital concentrator, the frame sync signal as the data, the system clock as the clock, the first latch, the first latch output as the data, and the system clock as the clock. The frame signal generator 220 which latches one, first latches output as data, second latches using a system clock of 4 MHz, and then negatively multiplies the first and second latch outputs to generate different desired frame synchronization signals in the system. Device characterized in that configured as. The 16th time slot of the time switch of claim 1, wherein the CCS processing unit 300 serially converts the CSS information from the data link processor by the second clock in parallel and parallel by the first clock in the CCS mode. CCS inserting unit 310 for generating CCS information to be inserted into the terminal, and parallel CCS information outputted from the time switch by the first clock in parallel and operated by a frame synchronization signal and a 16th time slot designation signal. And a CCS extracting unit (320) for outputting CCS information to the data link processor by converting in parallel in two clocks. The first time switch 510 of claim 1, wherein the time switch unit 500 is initialized to a message mode under the control of the control interface 100 to switch CAS information and various alarms and status information. And second and third time switching (520,530) for switching to channel 16 and switching two sub-highway voice data, respectively. According to claim 1, wherein the alarm and test unit 700, the AIS generating unit 710 for generating a local AIS signal by the AIS generation switch operation by the system operator and the CEPT trunk through the control interface 100 Driven by the output of the processor, the frame and multi-frame array alarm, remote junction and signal alarm, AIS alarm, and over-error rate alarm drive the display device for the relevant CEPT line to display the alarm occurrence and output it to the rack alarm access board. An alarm display unit 720 for informing alarm occurrence to a corresponding data link processor when a remote alarm occurs, a reproduction clock control unit 730 for extracting a reproduction clock from each digital trunk hybrid and outputting it to a network device, and a digital trunk concentrator; Clock check to detect supplied system clock (4MHz) and frame sync signal and output to rack alarm access board Apparatus characterized in that it consists of a unit (740).

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