JPS60125030A - Synchronous terminal equipment - Google Patents

Abstract

PURPOSE:To synchronize a transmission and a reception pulse train completely with each other, and to repeat them easily by operating two timing pulse generating circuits synchronously with the same multiframe information, and equalizing the delay of signal processing through a delay circuit. CONSTITUTION:A PCM pulse train is frame-synchronized by a receiving frame interface/frame synchronizing circuit 1 and converted by a frame converting circuit 2 into a new frame of a station with multiframe synchronizing timing pulses from a timing pulse generating circuit 10. The PCM pulse train from the converting circuit 2 is separated into 64kb/s data, channel by channel with pulses from the circuit 10 and outputted from a channel circuit 4. When information is repeated, channel by channel, the output of the circuit 4 is inputted to a transmitting PCM channel circuit 6, a synchronizing pattern is inserted by a frame synchronizing pattern inserting circuit 8, and the resulting information is outputted from an interface circuit 9. Although two-frame delay is performed in a mutual converting process of frames, the delay circuit 11 performs delay and the synchronizing pattern is inserted by the circuit 8.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to pulse code modulation (hereinafter abbreviated as PCM).
The present invention relates to a synchronous terminal device that is applied to a synchronization system and a signaling relay system during digital relay in a multiplex communication system.

[Prior Art] Conventionally, there has been a device of this type as shown in FIG. In the figure, (1) is a reception interface/frame synchronization circuit, and (2) is a frame that converts the PCM signal frame from reception interface/frame synchronization circuit (1) into a new frame using a timing pulse signal (described later). conversion circuit, (3) is a timing pulse generation circuit that generates various timing pulses in synchronization with externally supplied frame information, (4) is a 64Kb/S PCM
A receiving PCM channel circuit that outputs the I channel (
5) is a receiving signal circuit that outputs a telephone channel signal;
(6) is a transmitting PCM channel circuit that inputs the 64Kb/S PCMI channel, (7) is a transmitting signal circuit that inputs the telephone channel signal, and (8) is the frame from the timing signal generation circuit (3). A frame synchronization pattern insertion circuit inserts a synchronization turn into a pulse train of a PCM signal, and (9) is a transmission interface circuit.

Next, the operation will be explained.

FIG. 2 shows an example of a bit-staying PCM frame structure, which is based on CCITT (International Telegraph and Telephone Consultative Committee) Rec, G, 733. Here, one multiframe (1.5m5ec) consists of 12 frames (Fl to F12), and each frame has 1 bit (referred to as S bit) for frame/multiframe synchronization and 192 bits of PCM signals for 24 channels. 193 bits (8 bits/1 channel x 24 channels)
In the 6th frame F6 and the 127th frame F12, the 8th bit of each channel transmits a signal at the time of telephone transmission (syder ring). FIG. 2 also shows a frame structure showing each audio bit Sv and signal bit S8 of 154-4 Mb/S in 24-channel multiplexing and 64 Mb/S in 1-channel.

The PCM pulse train having the frame configuration shown in FIG. The frame is then converted to a new frame for the other station. Specifically, the reception interface/frame synchronization circuit (1
) is written to the buffer memory using the frame synchronization timing pulse from the timing pulse generation circuit (3), and read out using the frame synchronization timing pulse from the timing pulse generation circuit (3).
Adjust frame timing. The PCM pulse train from the frame conversion circuit (2) is separated into audio information S and signal information S8 for each channel by the respective timing pulses from the timing pulse generation circuit (3). 4) is output from the reception signal circuit (5). When relaying these information Sv and Ss on a channel-by-channel basis, the output of the receiving PCM channel circuit (4) is input to the transmitting PCM channel circuit (6), and the output from the receiving signal circuit (5) is input to the transmitting signal circuit (
7). The outputs from the transmit PCM channel circuit (6) and the transmit signal circuit (7) of the Shu Yannel are combined, and a frame synchronization pattern is further inserted in the frame synchronization turn insertion circuit (8), and - the transmit interface circuit (9) After that, the PCM pulse train shown in FIG. 2 is output.

In Figure 1, there are two timing pulse generation circuits (
3) operates in synchronization with the same frame information supplied from the outside, so even if each channel is relayed channel by channel, the time slots of the channels within the frame remain the same.

If the relay for each channel is converted into audio information Sv (analog), it will be asynchronous with the frame synchronization turn operation, and the audio information Sv and signal information S8 will be asynchronous.
There is no problem because it can be completely separated and relayed, but 64Kb
1.54 when relaying with /S data (digital)
Since a one-frame delay occurs in the mutual conversion process between 4 Mb/S and 64 Kb/S, there is a delay of 2 frames between points A and B in Figure 1.
A frame delay (indicated by the dashed line in FIG. 3) occurs.

FIG. 3 shows the frame structure of a conventional device when digitally relaying at 64 Kb/S. As shown in Fig. 3, although the frame synchronization patterns 81 to 812 at points A and B are synchronized, the actual received pulse train is transmitted with a delay of two frames (Flt-Fl 2j), so each channel The signal bits included in the received PCM pulse train are transmitted in duplicate, including those included in the received PCM pulse train and relayed, and those newly inserted in the transmission system. For this reason, what is included in the received PCM pulse train and relayed may be extra information bits (for example, the third
F6 in the diagram. or F12t), the PCM bits for the uttered speech information change from 8 bits to 7 bits (see FIG. 2), degrading the signal-to-quantization noise (S/Nq). This process had a major drawback in that the more digital relay sections at 64 Kb/S, the more the S/Nq deteriorated, and the line quality deteriorated.

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventional ones as described above.
By delaying the frame synchronization pattern of the transmission system by the frame delay caused by the mutual conversion between S and S, and by configuring the audio information bits and signal information bits to be relayed together without separating them, The purpose of the present invention is to provide a synchronous terminal device that can easily perform relaying without degrading line quality.

[Embodiments of the invention]

FIG. 4 shows an example of a synchronous terminal device according to the present invention, and the same parts as in FIGS. 1 to 3 are denoted by the same reference numerals, and the explanation thereof will be omitted.

In the figure, α0) is a timing pulse generation circuit that generates each cage tying pulse in synchronization with multiframe information supplied from the outside, and 圓 is a timing pulse generation circuit (which generates the frame/multiframe synchronization pattern generated at 1α). This is a frame/multi-frame synchronization pattern delay circuit that delays.

Next, the operation of the above configuration will be explained.

The PCM pulse train having the frame configuration shown in Fig. 2 is frame synchronized by the reception interface/frame synchronization circuit (1), and then converted into a multi-frame synchronization timing pulse from the timing pulse generation circuit (10) by the frame conversion circuit (2). It is converted to a new frame of the other station. The PCM pulse train from the frame conversion circuit (2) is separated into 64 Kb/S data for each channel by various timing pulses from the timing pulse generation circuit (10), and is output from the receiving PCM channel circuit (4).

When relaying this information on a channel-by-channel basis, the receiving PC
The output of the M channel circuit (4) is input to the transmission PCM channel circuit (6), and a frame/multiframe synchronization pattern is inserted in the frame synchronization pattern insertion circuit (8). The PCM pulse shown in the figure is output.

Here, two second timing pulse generation circuits α0)
operates in synchronization with the same multi-frame [i] supplied from the outside, so even if each channel is relayed channel by channel, the time slots of the channels within the frame remain the same. When digitally relaying 64Kb/S data as described above.

Since there is a delay of one frame each in the mutual conversion process between 1,544 Mb/S and 64 Kb/S, points 0 and D in Figure 2
However, the frame/multiframe synchronization pattern in the transmission system is delayed by two frames in the frame/multiframe synchronization pattern delay circuit (111) and inserted in the frame synchronization pattern insertion circuit (8). For example, the actual signal information bits of the transmitted PCM pulse train are synchronized with the time slots of the frame/multiframe synchronization pattern, and no extra signal information bits are inserted as shown in Figure 5, so there are many digital relay sections. Even if there is, the line quality will not deteriorate.

In the above embodiment, a PCM system with a 24-channel capacity was described, but the operation is the same for systems with different capacities, and the signal processing process of the PCM pulse train has a delay of N frames other than 2 frames. Also, the delay amount of the frame/multiframe synchronization pattern delay circuit circle is N
If it is set in a frame, the same effect as in the above embodiment can be achieved.

〔Effect of the invention〕

As described above, according to the present invention, the two timing pulse generation circuits are operated in synchronization with the same multiframe information, and the amount of delay in the signal processing process of the PCM pulse train is equalized by the frame/multiframe synchronization pattern delay circuit. Since the transmitting and receiving PCM pulse trains operate in complete synchronization up to multiple frames, there is no need to relay signal information bits, and the line quality is guaranteed. can be provided at low cost.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional synchronous terminal equipment, Fig. 2 is a diagram showing the PCM frame configuration of the bit-staying method, and Fig. 3 is a block diagram of a conventional synchronous terminal equipment.
Fig. 4 is a block diagram showing an example of a synchronous terminal device according to the present invention, and Fig. 5 is a frame configuration diagram when digital relay is performed using a conventional device. Fig. 5 is a frame configuration diagram when digital relay is performed using the device of Jin's invention. FIG. (1)...Reception interface/frame synchronization circuit, (2)...Frame conversion circuit, (4)...Reception P
CM channel circuit, (6)...Transmission PCM channel circuit, (8)...Frame synchronization pattern insertion circuit,
(9)...Transmission interface circuit, +101.
...Timing pulse generation circuit, αD...Frame/
Multi-frame synchronization pattern delay circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent Masuo Oiwa

Claims (1)

[Claims] (1) a reception interface/frame synchronization circuit;
A timing pulse generation circuit generates a timing pulse in synchronization with external frame information, and a timing pulse from the timing pulse generation circuit generates a PCM signal frame frame-synchronized by this receiving interface/frame synchronization circuit. A frame conversion circuit that converts into a new frame and outputs it; a reception PCM channel circuit that receives the output from the frame conversion circuit and separates it into predetermined data for each channel according to the timing pulse and outputs it; and a reception PCM channel circuit that converts it into a new frame and outputs it. a frame/multiframe synchronization pattern delay circuit that delays the multiframe synchronization pattern from the timing pulse generation circuit; and a multiframe delayed by the frame/multiframe synchronization pattern delay circuit. PCM synchronization pattern
A synchronous terminal station device comprising a frame synchronous pattern insertion circuit that inserts into a signal pulse train and sends it to a transmission interface circuit.