JPH0194735A - Method and device for receiving time-division multipled signal - Google Patents

Abstract

PURPOSE:To preferentially receive a time division multiplexed signal by executing decoding in terms of block after resetting timing for block synchronization to a newly multiplexed and transmitted channel. CONSTITUTION:A multiple signal inputted through a signal line 300 is distributed to each corresponding channel module by a separating circuit 310. A timing circuit 320 indicates whether a time slot is assigned to the channel or not. A block decoding circuit 330 executes the decoding responding to a pulse for the block synchronization and regenerates a significant signal from a code signal to be inputted through a signal line 302. To a selecting circuit 350, a regenerating signal and a false noise are inputted, and either of these two signals is selected and outputted to respond to a selecting signal inputted through a signal line 322. A noise generating circuit 340 generates a false voice at a receiving side and makes a silent state in an ordinary telephone call when the significant signal is not generated at a transmitting side.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method and apparatus for receiving time division multiplexed signals in which a plurality of telephone signals are encoded with high efficiency and then efficiently time division multiplexed.

[Conventional technology]

Conventionally, digital voice insertion (DS) has been used as a method of multiplexing and transmitting preferentially channels in which significant signals such as voice signals and data modem signals exist among multiple telephone channels.
I) There was a method. This method utilizes the fact that in a normal conversation, the time during which one person is actually speaking is approximately 40 channels during the call, and by inserting the voice of the other channel into the empty time, transmission efficiency is improved. It enhances the for example.

: iJ A line with a transmission speed of 48 Mbps has 64
Kbps pulse code modulated (PCM) telephone signal is 3
If the DST method is applied to a line where 0 channels are multiplexed, it becomes possible to multiplex approximately 60 channels.

If 32 Kbps adaptive differential PCM (ADPCM), which encodes highly efficiently at half the encoding speed of 64 Kbps PCM, is used as the audio signal encoding method, the number of channels can be further doubled to 120 channels. Recently, with the development of coding technology, even more efficient block coding of 16 Kbps has come to be used.

[Problem that the invention seeks to solve]

However, when applying the DSI method by lowering the encoding speed of the audio signal, if a block encoding method is used as the encoding method in which each block consisting of multiple audio samples is encoded, the frame rate of the transmission path Since the block coding period is longer than the period, it is necessary to send one block of audio signal using multiple frames. for example,
Block encode the audio signal every 1Qmsec to 16K
When transmitting at bps, the frame period of the transmission path is 1
If it is 25 p sec (1/8 kHz),
2 bits are multiplexed in 1 frame, and 1 bit is multiplexed in 8o frames.
The block audio signal is encoded and transmitted.

Audio signal analysis parameters, quantization signals, etc. are multiplexed into one block, and decoding is performed block by block on the receiving side as well.

Therefore, it is necessary for the receiving side to know not only the frame synchronization of the transmission path but also the block synchronization. For this reason, conventional methods have been to configure multiframes with a length that is an integral multiple of the transmission line frame period, and to make the multiframe period the same length as the block period, or to include a synchronization signal for block synchronization in the l block signal. block synchronization between the encoder and decoder was established by including However, in the former case, a new multi-frame synchronization circuit is required, and a block encoding method with different block lengths cannot be used. Furthermore, in the latter case, the bits originally used for audio encoding are deleted as bits for block synchronization, resulting in deterioration of sound quality.

Therefore, the present invention provides a time division multiplexed signal receiving method and apparatus that can apply the DSI method by establishing block synchronization on the transmitting and receiving sides without configuring multi-frames in the transmission line or sending block synchronization signals. The task is to do so.

[Means for solving problems]

A method for receiving a time division multiplexed signal according to the present invention is a method for receiving a time division multiplexed signal that is block-coded and multiplexed by giving priority to a channel in which a significant signal exists among a plurality of input channels over a channel in which a significant signal does not exist. In this configuration, when performing block decoding on a newly multiplexed and transmitted channel among the received channels, the block decoding is performed after resetting the block synchronization timing.

Further, the time division multiplexed signal receiving apparatus of the present invention includes a plurality of channel modules that block decode the block coded signal into which block coded signals of a plurality of channels are multiplexed and output a reproduced signal. a timing circuit for resetting the block synchronization timing according to the allocation signal output from the separation circuit, and a timing circuit for resetting the block synchronization timing in accordance with the block synchronization signal output from the timing circuit, each of the plurality of channel modules A block decoding circuit that performs block decoding of a block encoded signal output from the circuit, a noise generation circuit that generates pseudo noise, a decoded signal output from the block decoding circuit, and an output from the noise generation circuit. and a selection circuit that receives as input the decoded signal and the pseudo noise and selects either the decoded signal or the pseudo noise according to a selection signal output from the timing circuit and outputs the selected signal as a reproduced signal.

[Effect]

In the present invention, a channel in which a significant signal such as an audio signal exists among a plurality of input channels is block encoded, and then the DS
It is preferentially multiplexed and transmitted using the I method. Therefore, the channel configuration multiplexed within a transmission line frame changes from time to time. Therefore, a time slot assignment signal for informing the receiving side of which channels are multiplexed in the transmission path frame is transmitted together with the encoded audio signal. The receiving side knows which channel the received signal belongs to from the sent time slot assignment signal, and distributes the received signal to the decoding circuit of the corresponding channel.

That is, looking at one Q input channel, the transmission side detects the occurrence of a significant signal and sends time slot assignment information indicating that a transmission path time slot has been assigned to this channel, and then transmits the encoded signal. After the time slot assignment signal is received on the receiving side, the transmitted encoded signal is decoded and a reproduced signal is output.

Therefore, in the present invention, when this time slot assignment signal is sent, the transmitting side resets the block encoding timing of the newly multiplexed channel by time slot assignment and starts encoding, and the receiving side Immediately after the slot allocation signal is received, the block decoding timing is reset, and decoding is started using the encoded signal received thereafter as the head signal of one block.Thus, block synchronization is established on the transmitting and receiving sides. Performs encoding and decoding. As a result, significant signals can be transmitted while maintaining block synchronization on the transmitting and receiving sides, without adding new multi-frame configurations or block synchronization bits in the prior art as described above.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a time division multiplexed signal receiving apparatus according to an embodiment of the present invention, and FIG. 2 is a diagram showing signals on main signal lines in FIG. 1. 3 is a configuration diagram showing an example of a time division multiplex transmitting device corresponding to the receiving device in FIG.
The figure shows the signals of the main signal lines.

First, a time division multiplex transmitter that generates a time division multiplex signal to be input to a receiver will be described.

Referring to FIG. 3, here it is assumed that there are N input channels, and signals of channels CHI, CH2, CHN are transmitted via signal lines 100, 101, 102 to channel modules 150, 160, .
170. Since each channel module has the same configuration, the channel module 150 for channel CHI will be described. The signal detection circuit 120 checks whether the input signal is a significant signal such as voice.
The result is output to multiplexing circuit 180 via signal line 121. In the delay circuit 110, the input signal is delayed by the time required to detect a significant signal in the signal detection circuit 120, and then the delayed input signal is output to the block encoding circuit 130.

In the multiplexing circuit 180, when a significant signal is detected according to the signal detection result inputted via the signal line 121, a transmission path time slot is assigned to the block encoding circuit 130.
The coded signal outputted from the channel via the signal line 131 is multiplexed with the coded signal of other channels and the time slot assignment signal, and is outputted to the transmission line via the signal line 181. An assignment signal indicating whether or not a time slot has been assigned is input to the timing circuit 140 via a signal line 182. The timing circuit 140 outputs a pulse for block synchronization of the block encoding circuit 130 as a signal &114.
1, and the block encoding circuit 130 performs block encoding in synchronization with this synchronization pulse.

Figure 4 shows the signals [141, 182 and 1] in Figure 3.
31 is a diagram illustrating an example of a signal at No. 31. In the figure, a signal 201 indicates a block synchronization pulse signal output from the timing circuit 140 via a signal line 141. In synchronization with the rise of this pulse signal, the input signal is divided into blocks and encoded. signal 20
2 is an allocation signal outputted from the multiplexing circuit 180 via the signal de ρ182, and the significant signal is the signal detected by the signal detection circuit 12.
0, and if a time slot for transmitting this significant signal can be secured, it becomes a high level signal. While the signal is at a low level, there is no significant signal, indicating a section in which no time slot is assigned. Since the timing circuit 140 is reset in synchronization with the rising edge of the allocation signal 202, the block synchronization timing for block encoding is reset every time a new significant signal is generated and a time slot is newly allocated. . In this way, the signal 203 resets the block synchronization timing while the encoded significant signal is transferred to the signal line 13.
1 is used to explain a signal when outputted via 1. The shaded portion is a portion that is not actually transmitted, and no significant signal exists in this section.

Next, referring to FIG. 1, which shows an embodiment of a time division multiplex signal receiving apparatus corresponding to the above-mentioned time division multiplex transmission apparatus,
The multiplexed signal input via the signal line 300 is sent to the separation circuit 3.
10 to each corresponding channel module. Since the channel modules 360, 370, and 380 have the same configuration for each channel, channel CH1 is used here.
The channel module 360 will be explained. An assignment signal is input to the timing circuit 320 via a signal line 301t-. This assignment signal indicates whether or not a time slot is assigned to that channel, similar to that explained in connection with the transmitter. The block decoding circuit 330 connects the timing circuit 320 to the signal line 321.
Decoding is performed in accordance with the block synchronization pulse outputted via the signal line 302, and a significant signal is reproduced from the encoded signal inputted via the signal line 302. The block decoded playback signal and the pseudo noise output from the noise generation circuit 340 are input to the selection circuit 350 via signal lines 331 and 341, and the selection circuit 350 is input from the timing circuit 320 via the signal line 322. Depending on the signal, one of the signals is selected and output. The noise generating circuit 340 generates pseudo noise on the receiving side when no significant signal is generated on the transmitting side to create a silent state in a normal telephone conversation.

FIG. 2 shows signals on the main signal lines in FIG. 1. The signal 401 is a block synchronization pulse inputted to the block decoding circuit 330 via the signal line 321, and block decoding is performed in synchronization with the pulses generated for each block length. The signal 402 is the signal line 30
This is an allocation signal that is input via 1, and is at a high level when an encoded signal is sent from the transmitting side, and is at a low level when no coded signal is sent. In synchronization with the rising edge of this allocation signal 402, the timing circuit performs decoding in the same manner as on the transmitting side in synchronization with the allocation signal 402, thereby establishing block synchronization between the transmitting side and the receiving side and encoding. and decoding can be realized. signal 4
03 is a selection signal input to the selection circuit 350 via the signal line 322. Since the decoded signal in block decoding is generally output with a delay of one block length from the received signal, the selection signal 403 is also a signal delayed by the length of l block compared to the allocation signal 402. The signal 404 is a reproduction signal outputted from the selection circuit 350 through all the signal lines 351. Pseudo-noise is inserted into sections where no significant signal exists to maintain the naturalness of normal conversation.

〔Effect of the invention〕

As described above, according to the present invention, without adding a multi-frame synchronization circuit and a block synchronization signal, a channel in which a significant signal exists among a plurality of input channels is block encoded and is preferentially time-divided. Multiplexed signals can be received.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a time division multiplexed signal receiving apparatus according to an embodiment of the present invention, FIG. 2 is a diagram showing signals in FIG. 1,
Fig. 3 is a configuration diagram showing an example of a time division multiplex transmission device;
The figure is a diagram showing the signals in FIG. 3. 310... Separation circuit, 320... Timing circuit, 330... Block decoding circuit,
340... Noise generation circuit, 350...
Selection circuit, 360.370°380°°°°°° Channel module. Agent: Susumu Uchihara, patent attorney, 3t. Figure 1 Figure 3 Figure 2 Figure 4

Claims (2)

[Claims] (1) In a time division multiplexed signal reception method in which a channel in which a significant signal exists among a plurality of input channels is given priority over a channel in which a significant signal does not exist, and is block-coded and multiplexed, among the received channels, A method for receiving a time division multiplexed signal, characterized in that when performing block decoding on a newly multiplexed and transmitted channel, block decoding is performed after resetting block synchronization timing. (2) a separation circuit that receives a multiplexed signal in which block coded signals of a plurality of channels are multiplexed and separates the block coded signal for each corresponding channel; and the block coded signal output from the separation circuit. a plurality of channel modules for block decoding and outputting reproduced signals, and a timing circuit for each of the plurality of channel modules to reset timing for block synchronization according to an allocation signal output from the separation circuit; a block decoding circuit that performs block decoding of a block encoded signal output from the separation circuit in accordance with a block synchronization signal output from a timing circuit; a noise generation circuit that generates pseudo noise; and a noise generation circuit that generates pseudo noise; The output decoded signal and the pseudo noise output from the noise generation circuit are input, and one of the decoded signal and the pseudo noise is selected according to the selection signal output from the timing circuit and output as a reproduced signal. 1. A time division multiplexed signal receiving device comprising a selection circuit.