JPH02134938A - Data multiplexing/demultiplexing system - Google Patents

Abstract

PURPOSE:To improve communication efficiency by segmenting serial data of respective channels to blocks consisting of a prescribed number of bits and converting these serial data to one serial data. CONSTITUTION:When the data of plural channels are multiplexed to one serial data, data to be multiplexed are distributed to blocks consisting of the prescribed number of bits and multiplexed. For example, the data of channels A, B, and C are inputted to serial/parallel converting circuits 11, 12, and 13 in a data multiplexer/demultiplexer 1 respectively and converted to 8-bit parallel data and inputted to a multiplexing circuit 14. consequently, data which is constituted in the format based on HDLC procedures or the like and has the start and the end easily identified without frame synchronization is multiplexed/ demultiplexed with a minimum delay without waiting for one frame. Thus, the communication efficiency of bidirectional data communication or the like is improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to data multiplexing and demultiplexing when data that does not require frame synchronization is multiplexed and demultiplexed in a data communication system.
Regarding separation method.

[Conventional technology]

Conventionally, when data of various channels is multiplexed with frame synchronization in a data multiplexing/demultiplexing method, the data of each channel is multiplexed in a batch. Therefore, when multiplexing and demultiplexing each channel, data is accommodated in the next frame. Examples of such frame configurations and multiplexing/demultiplexing methods are shown in FIGS. 6, 7, and 8. In each figure, F is a frame pattern, A is 1.024Mb
A channel for transmitting ps data, B is 256Kbps
C is a channel for transmitting data of 128 Kbps, and empty space is unused.

[Problem to be solved by the invention]

In the conventional data multiplexing/demultiplexing method as described above, when multiplexing the data of each channel, it is multiplexed into the next frame, and when demultiplexing the multiplexed data, it is separated into the next frame, resulting in a maximum Eframe delay. . therefore,
Even when multiplexing data that does not require frame synchronization and should minimize delay, such as HDLC format data, frame synchronization causes a maximum delay of one frame each during multiplexing and demultiplexing. The disadvantage is that communication efficiency is low.

[Means to solve the problem]

The data multiplexing and demultiplexing method of the present invention includes a first means for dividing first channel serial data that does not require frame synchronization and second channel serial data that requires frame synchronization into blocks each having a predetermined number of bits; The data of the first channel divided into blocks by the first means is multiplexed into the nearest frame at a constant period in units of blocks, and the data of the second channel divided into blocks by the first means is multiplexed in units of blocks. a second means for multiplexing into the next frame following the nearest frame at a constant cycle; and a third means for separating the data of the first channel and the data of the second channel from the received multiplexed data into blocks, respectively. means; fourth means for converting the block-by-block data separated by the third means into serial data of the first channel and serial data of the second channel; Second. and fifth means for controlling operation timings of the third and fourth means.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a data multiplexing/demultiplexing device according to an embodiment of the present invention. This data multiplexing/demultiplexing device M1 has the function of multiplexing the data of channels A, B, and C into serial data and sending it out to the communication line, as well as separating the data of each channel from the multiplexed serial data from the communication line. have. The data of channels A, B, and C are input to serial-to-parallel conversion circuits 11, 12, and 13 in the data multiplexing/demultiplexing device 1, respectively, and converted into 8-bit parallel data, which is input to the multiplexing circuit 14. The 8-bit parallel data multiplexed by the multiplex circuit 14 is
It is converted into serial data by the parallel-serial conversion circuit 15 and output to the communication line. In addition, multiplexed serial data input from a communication line is converted into 8-bit parallel data by a serial-parallel conversion circuit 21, separated into 8-bit parallel data for each channel A, B, and C by a separation circuit 22, and then converted from parallel to serial. circuit 23
, 24.25 and converted to serial data,
Output to each channel's interface. The control circuit 31 of the data multiplexing/demultiplexing device 1 performs multiplexing circuit 14, demultiplexing circuit 22, serial-to-parallel conversion circuits 11, 12, 13.21, and parallel-to-serial conversion based on frame synchronization timing input and microcomputer interface input/output information. Controls the timing of each of circuits 15.23 and 24.25.

Next, the operation will be explained using FIG. 1, FIG. 3, FIG. 4, and FIG. 5. FIG. 3 shows an example of a frame structure, where the communication line is 2.048 Mbps, and channel A is 1.04 Mbps.
024Mbps.

Channel B is 256Kbps and Channel C is 128K
This is the case for a data transmission rate of bps.

Channel A is for data formatted according to HDLC procedures that do not require frame synchronization. Further, FIG. 4 does not show a time chart for the multiplex method, and FIG. 5 does not show a time chart for the separation method. The 256 Kbps serial data input from channel B is converted to serial data by the serial-parallel conversion circuit 12, and the 256 Kbps serial data input from channel B is
The 8Kbps serial data is converted into 8-bit parallel data (
block) and input to the multiplexing circuit 14. Each block is accommodated in the storage position of each channel of the next frame at a timing specified by the control circuit 31. Note that in this case, there is no advantage in terms of delay over the conventional method. The 1,024 Mbps data input to channel A is converted into blocks of 8 bits each by the serial-parallel conversion circuit 11, and then stored in the channel A storage position of the own frame according to instructions from the control circuit 31, regardless of the frame synchronization timing. can do. Therefore, the delay of channel A becomes 24 bits of data at 2.048 Mbps (≠12 μ5 ec) in FIG. 4, which can be much smaller than in the conventional system. Similarly, when separating the data of each channel from the input multiplexed data, in the case of channels B and C, the next frame is each 256 Kbps as in the conventional method.

It is output as 128Kbps serial data,
Channel A is reconfigured as 1.024 Mbps serial data in the order in which the frames arrived without waiting for the next frame.

The detailed configuration of the control circuit 31 in FIG. 1 will be explained with reference to FIG. 2. The control circuit 31 has an address bus input 1 selection signal input, a write signal input, and a read signal input as a microcomputer interface through human buffers 101 and 1, respectively.
02, 103°, 104, 105, 106, and the data bus input/output is connected to the input/output buffer 107. The outputs of the input buffers 101 and 102 are connected to the address decoder 108 and
The output of channel A mode setting circuit 109. Channel B mode setting circuit 110. Channel C mode setting circuit 1
11. In addition, the outputs of input buffers 103 and 104 are also supplied to channel A mode setting circuit 109. Channel B mode setting circuit 110. Each is input to the channel C mode setting circuit 111. Internal data bus 11
2 has an input/output buffer 107. Channel A mode setting circuit 109. Channel B mode setting circuit 110. A channel C mode setting circuit 111 is connected. As a result, channel A mote setting circuit 109. Channel B mode setting circuit 110° Channel C mode setting circuit 111 can set the mode of each channel and read the mode setting status.

Also, channel A mode setting circuit 109. Channel B mode setting circuit 110. Channel C mode setting circuit 111
Each output of channel A timing generation circuit 11
3. Channel B timing generation circuit 114. Channel C
In addition to being input to the timing generation circuit 115, the outputs of the input buffers 105 and 106 are also input to the channel A timing generation circuit 113, the channel B timing generation circuit 114, and the channel C timing generation circuit 115.

The outputs of the input buffers 105 and 106 are input to a multiplex/separate timing generation circuit 116. Multiplex/separate timing occurrence #rl16. Channel A timing generation circuit 113. Channel B timing generation circuit 114. The outputs of the channel C timing generation circuit 115 are output as timing outputs through output buffers 117, 118, 119, and 1.20, respectively.

Next, the operation of the control circuit 31 will be explained with reference to FIGS. 1 and 2. When setting the speed of channel A and whether or not frame synchronization is necessary, the selection signal input and address bus input from the microcomputer (not shown) of the data multiplexing and demultiplexing device 1 are input to the input buffers 102 and 101 in the control circuit 31.
, the signal for channel A is enabled. At the same time, a write signal input from the microcontroller is input to the channel C mode setting circuit 109 via the input buffer 103, and when data from the data bus is input via the human output buffer 107, the mode of channel A is set according to the input data. be done. The settings include the transmission speed of channel A and whether or not frame synchronization is required. Channel A mode setting circuit 10
9, the frame timing input input via the input buffers 105 and 106, and the system clock input, the channel A timing generation circuit 113 converts the channel A serial-parallel converter 11 and parallel-serial converter 23. timing is created. The same applies to channels B and C. In addition, the multiplexing/demultiplexing timing of multiplexed data is determined when the transmission speed of multiplexed data is constant (
In this embodiment, in the case of 2.048 Mbps), the timing is always the same, so the frame timings from the input buffers 105 and 106 are both generated by the multiplexing/demultiplexing timing generation circuit 116, and the parallel/real conversion circuit 15 is generated from the output buffer 117. and is supplied to the serial-parallel conversion circuit 21.

〔Effect of the invention〕

As explained above, according to the present invention, when data of multiple channels is multiplexed into one serial data, the data to be multiplexed is divided into blocks of a predetermined number of bits and multiplexed, based on the HDLC procedure etc. For data that is configured in a format where the start and end of the data can be easily identified without frame synchronization, multiplexing and demultiplexing can be performed with minimum delay without waiting for one frame. As a result, communication efficiency in bidirectional data communication and the like can be improved.

[Brief explanation of the drawing]

1 and 2 are block diagrams showing one embodiment of the present invention, and FIGS. 3, 4, and 5 are diagrams showing the frame structure and the timing of the multiplexing/demultiplexing system in the same embodiment. 6, 7, and 8 are diagrams for explaining conventional examples. 1...Data multiplexing/demultiplexing device, 11, 12.13...
・Serial-parallel conversion circuit, 14... multiplex circuit,
15... Parallel-serial conversion circuit, 21... Serial-parallel conversion circuit, 22... Separation circuit, 22
．． 24.25...Parallel-serial conversion circuit, 31
...Control circuit, 101, 102, 103゜104.1
05, 106... Input buffer, 107... Input/output buffer, 108... Address decoder, 109...
・Channel A mode setting circuit, 110...Channel C
Mode setting circuit, 111...Channel C mode setting circuit, 112...Internal data bus, 113...Channel A timing generation circuit, 114...Channel C timing generation circuit, 115...Channel C timing generation Circuit, 116... multiplex/separate timing generation circuit,
117, 118, 119, 120... Output buffer.

Claims (1)

[Scope of Claims] First means for dividing first channel serial data that does not require frame synchronization and second channel serial data that requires frame synchronization into blocks each having a predetermined number of bits; multiplexing the data of the first channel divided into blocks by the means into the nearest frame in block units at a constant cycle; and the data of the second channel divided into blocks by the first means in units of blocks at a constant cycle. a second means for multiplexing into the next frame following the nearest flume; a third means for separating the first channel data and the second channel data from the received multiplexed data into blocks, respectively; fourth means for converting the block-by-block data separated by the third means into serial data of the first channel and serial data of the second channel; and the first, second, third, and fourth channels. and a fifth means for controlling the operation timing of the means.