JPS61129933A - Time division multiplexer - Google Patents

Abstract

PURPOSE:To simplify the hardware and to improve the expanding performance of a line to be supported by connecting a virtual port comprising a read/write memory at any time to a bus to which a port being an interface with a terminal device is connected. CONSTITUTION:The internal bus 141 connecting the terminal interface (port) 15 is provided with the virtual port 17 comprising a read/write memory at any time. In case of relaying also, the data transmitted from a high speed line 111 is written once in the port 17, and then the said data is read at any time and transmitted from other high speed line 112, which is controlled by time division multiplex control sections 131, 132. Thus, the internal bus connecting directly the control sections is abolished to simplify the hardware of the titled device and improve the expanding performance of the lines to be supported.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a time division multiplexing device in a time division multiplexing communication system in which three or more time division multiplexing devices are coupled to a plurality of high-speed digital lines. This invention relates to a configuration related to a relay operation.

[Technical background of the invention]

FIG. 5 is a block diagram showing an example of a conventional time division multiplex communication system of this type. One time division multiplexer is connected to a time division multiplexer IB, and the time division multiplexer IB is connected to a time division multiplexer IC via high-speed digital lines. Time division multiplexer IA, IB, IC
Multiple rfi terminals each! 1jt2 is connected.

Note that the broken lines coming out of each time division multiplexer are logical t
1 data bus and not a physical line. In such a time division multiplex communication system, a time division multiplexer flllA and a time division multiplexer I
The operation in which C transmits and receives data via the time division multiplexer IB is called relaying.

FIG. 6 shows an example of the structure of a frame for controlling 4M data communication partners in the time division multiplex communication system shown in FIG. Code 3A, 3B.

3Cjd A frame for controlling each time division multiplexer, 1
A frame consists of n channels. Here, if we pay attention to frame 3A of the time division multiplexer IA, the channel B is written as a time division multiplexer with the corresponding terminal device connected to the time division multiplexer IA using that channel. Indicates that communication is to be performed between the corresponding terminal devices connected to device IB, and the time division multiplexing device fllA uses the special channel written as C in the channel in the frame.
The corresponding terminal equipment and time division multiplexer I connected to
This shows that communication is performed between the corresponding terminal devices connected to C by relaying the time division multiplexing device IB. the other 7
The same applies to frames 3B and 3C.

FIG. 7 is a block diagram showing a detailed example of a conventional time division multiplexing device of this type. Reference numeral 4 denotes a system control section that controls the entire time division multiplexing apparatus, and in particular controls a plurality of time division multiplexing and relay control sections 5. A plurality of low-speed side terminal interfaces (hereinafter referred to as ports) 8 are connected to each time division multiplexing and relay control section 5 via a bus 6 and a bus 7 .

Although not shown, a terminal device is connected to each port 8. Further, each time division multiplexing and relay control unit 5 connects to a high-speed line 101 via a high-speed line interface 9, respectively.
．． 102. Furthermore, the time division multiplexing and relay control sections 5 are interconnected by a bus 11. Note that the high-speed line interface 9 connects data etc. from the time division multiplexing and relay control unit 5 to the high-speed line 101 (or 1
It has the function of establishing a frame structure and electrical interface with the data etc. of 02).

Conventionally, when transmitting and receiving data with a terminal device connected to its own time division multiplexing device via the high-speed line 101 (or 102), the time division multiplexing and relay control unit 5 uses the bus 6 (or 7) via high-speed line 101 (or 102
) and the corresponding port 8 to perform communication between two terminal devices and relay between the high-speed lines 101.102, the high-speed lines 101. 102
Connecting is done from K. Therefore, the time division multiplexing and relay control section 5 performs control to switch the internal node to be used depending on whether data is to be transmitted/received to/from the IC card 8 or relayed.

[Problems with background technology]

In the time division multiplexing device constituting the conventional time division multiplex communication system as described above, the time division multiplexing and relay control unit 5 Internal bus C9 bus 6 used by
7.11), and the time division multiplexing and relaying procedures of the relay control unit 5 were complicated. or,
The example in Figure 7 shows the case where two high-speed lines 101 and 102 are supported, but if more than n lines are supported and relaying between all lines is possible, each time division multiplexing The bus 11 connecting between the conversion and relay control units 5 is n f
/((n-2) l 2f ), which has the disadvantage that the hardware of the time division multiplexing and relay control unit 5 is extremely complicated. Moreover, depending on the number of high-speed lines supported, the bus 1 connecting each time division multiplexing and relay control unit 5
Since the number of 1's changes, the structure of the time division multiplexing and relay control section 5 differs each time, and the structure is not constant with respect to n. For this reason,? The drawback is that it is extremely difficult to expand the system by arbitrarily increasing the number of high-speed lines to be used.

[Purpose of the invention]

SUMMARY OF THE INVENTION In view of the above-mentioned drawbacks, it is an object of the present invention to provide time division multiplexing that can simplify a control unit that switches between data transmission and reception between terminal devices and relay operations between lines, and improve the expandability of supported lines. The goal is to provide equipment.

[Summary of the Invention] The present invention provides a virtual port consisting of a memory that can be read and written at any time on an internal bus that connects a terminal interface (port), and even in the case of relaying, data is sent from one high-speed line using the internal bus. After writing the received data to the virtual port, a control unit is provided that reads the data at any time and sends it out from another high-speed line, eliminating the need for an internal bus that directly connects the control units, which was necessary in the past. The above object is achieved by configuring the control section to perform the same control as data transmission and reception between terminal devices even in the case of relaying.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a time division multiplexing apparatus according to the present invention. The high-speed line 111 includes a high-speed line interface 121, a time division multiplexing control unit 131, and a bus 141.
is connected to multiple ports 15 via the high-speed line 1
12 is connected to a plurality of ports 15 via a high-speed line interface 122, a time division multiplexing control section 132, and a bus 142. Time division multiplexing control unit 131. 132
Fi is controlled by a system control unit 16 that controls the entire device. Furthermore, a virtual port 17 that commonly performs a relay function is connected to the buses 141 and 142. In addition,
In this example, the time division multiplexer is connected to high speed line 111. 11
2 shows the case where two lines are supported.

FIG. 2 shows the time division multiplexing control section 131 (
132 is a block diagram showing a detailed example of the same. The time division multiplexing control section includes a read port address generation section 18, a read data buffer 19R, a write port address generation section 18W, and a write data buffer 19W. At the time of reading, the port address generating section 18R outputs read signals R and D, and also outputs the address of the port from which data is to be read to the address bus A. Each port 1 shown in Figure 1
51: has a unique address, and if the port 15 corresponding to the address output from the boat address generation section 18R outputs the read signal RD, the data is transferred to the time division multiplexing control section. data buffer 1
9R via data bus D.

The data once held in this data pack 719B is then sent out to the high speed line via the high speed line interface.

At the time of writing, the boat address generating section 18W outputs the write signal WR, and at the same time outputs the write signal WR.
)15 address is output to address bus A. If the write signal WR has been output to the port 15 of the corresponding address, the data buffer 1 of the time division multiplexing control section
Data is taken in from data bus 9W via data bus D. Data transmitted through the high-speed line is written to data bus 19W via the high-speed line interface.

FIG. 3 is a block diagram showing a detailed example of the port 15 shown in FIG. 1. 4. Port address decoder 20W for writing and data buffer 21 for writing.
It consists of a port address decoding unit 20R for reading and a data buffer 21R for reading.

When writing to the liF (when outputting the write signal WR), the port address decoder 20W inputs the data on the data bus D to the buffer 21W if the write destination address (on the address bus) is its own address. This captured data is then sent to a terminal device (not shown). At the time of reading (when outputting a read signal hole), the read port address decoder 2OR decodes the read data pack if the read destination address (on address bus A) is the address of its own port. Data from a terminal device (not shown) held in 121B is sent onto data bus D.

FIG. 4 is a block diagram showing a detailed example of the virtual port 17 shown in FIG.
Address defood section 22W for reading.

22R+, a memory access control section 23, and a memory (R, AM) 24. When writing (
(When the write signal WR is being output)
When the write destination address of the data bus controller is the address of its own port, the reply decoder P unit 22W sets the memory access control unit n to the write mode.

This allows the memory access control unit 23Fi to write the data on the data bus D to the address of the memory 24 specified by the address bus A. The address decoder P section 22F sets the memory access control section 23 to the read mode P when the address of the address bus person is its own address. Accordingly, the memory access control section 23H reads out the data stored in the address section of the memory specified by the address bus A, and sends it to the data bus D. In Figure 2.3.4 above, address bus A and data bus D correspond to bus 141 or bus 142 in Figure 1; Alternatively, they are collectively referred to as buses 142.

Next, the operation of this embodiment will be explained. First, the relationship between the channel number in the frame that controls the time division multiplexer and the board aviles will be described.

In the frame, there are n channels, from the beginning, 1st, 2nd, etc.
...Numbered 0 For example, when passing the data of the first channel of the frame passed from the high-speed line interface 121 to the port of address α, the time division multiplexing control unit 131 adjusts the timing of the first channel. When this occurs, the bus 141 outputs the K address α, and at the same time passes the data to the corresponding port, channel number 2.3, etc.
. . 4 is the same for n, and is associated with each port address.

The correspondence between this channel number and the /-4 address is set from the system control section 16 to the port address generation sections 18B and 18W of the time division multiplexing control section shown in FIG. The correspondence relationship can be changed as required. Therefore, the time division multiplexing control unit 131 (
叉Fi132) Fi high-speed line 111 (also #'1112)
The data of each channel sent via the channel is sent to the corresponding port 15 in a time-division manner, or the data from each port 15 is read out in a time-division manner and connected to the high-speed line 111 (or 112) using the corresponding channel. ).

Here, the time division multiplexing control unit 131(
Also, when viewed from 11132), it performs exactly the same operation as the other port 15. In this example, this virtual = fr-)1
7 is used to perform relay operations between time division multiplexers. For convenience of explanation, for example, the time division multiplexing device shown in FIG. 1 is referred to as IB in FIG. 5, the high speed line 111 is referred to as the time division multiplexing device IA in FIG. It is assumed that the data of the time division multiplexer ft1A is connected to the time division multiplexer I shown in FIG.
It is assumed that the operation of relaying to the time division multiplexing unit WlIC via B is performed.

First, when data is sent through the high-speed line 111, the time-division multiplexing control unit 131 assigns addresses within the virtual 4-txt corresponding to busy channels to the bus (2.3.
In FIG. 4, the address bus A) 141 is output, and the data sent through the high-speed line 111 is written to the address of the memory device in FIG. 4 through the bus 141 (bus D in FIG. 2.3.4). On the other hand, the time division multiplexing control unit 132 performs virtual /-)1 corresponding to each channel in a time division manner.
7 (address bus A in Figures 2.3.4) 142, and outputs the data written at the address of the memory in Figure 4 to the bus (Figures 2, 3, and 4). The data is read through the data bus D) 142 and then sent to the high-speed line 112. Therefore, data sent from the high-speed line 111 is once written to the virtual port 17 and then immediately read out and sent to the high-speed line 11.
2 will be sent out. Therefore, data from a terminal device of one time division multiplexer connected to high speed line 112 is connected to high speed lines 1 and 12 via time division multiplexer IB in FIG. 1 as a relay. It will be sent to the terminal device of the time division multiplexer IC. Also, fast mouth! 112
The operation of relaying the data to the high-speed line 111 and sending it out is performed in the same way.

According to this embodiment, even when the time division multiplexing apparatus performs a relay operation, the time division multiplexing control unit 131 (or the Fi 132
) only reads and writes data to virtual port 17;
Since the reading and writing of data to and from Fi 13 and its operations are essentially the same, the time division multiplexing control unit 131 (also
There is no need to distinguish whether 2) is data communication between terminal devices or relay of communication data, and both can be controlled using the same procedure. This eliminates the need for a bus that connects the time-division multiplexing control units, making it possible to simplify the hardware configuration of the control unit, and to standardize the control unit regardless of the number of high-speed lines supported. This can significantly improve system scalability. Furthermore, the above effect simplifies the configuration of the time division multiplexing device, so the reliability of the system can be improved accordingly.

In addition, in the embodiment shown in FIG.
Since the memory 24 used in 7 has a large number of addresses, multiple relays between high-speed conversions of three or more lines are also possible in a similar manner. In addition, the time division multiplexing control unit @ 131 (
Alternatively, in 132), since the control units for transmission and reception (for IF reading and reading) are provided independently as shown in FIG. 2, it is also possible to perform full 2'-duplex communication.

〔Effect of the invention〕

As described above, according to the time division multiplexing device of the present invention,
A virtual, 1f-
), temporarily write the data sent from one high-speed line to the virtual port, and then read the written data and send it to the other high-speed line. Since the received data is relayed, the hardware of the device can be simplified and the expandability of the supporting line can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the time division multiplexing device of the present invention, FIG. 2 is a block diagram showing a detailed example of the time division multiplexing control section shown in FIG. 1, and FIG. is a block diagram showing a detailed example of the port shown in Fig. 1, Fig. 4 is a block diagram showing a detailed example of the virtual port shown in Fig. 1, and Fig. 5 is a block diagram showing a detailed example of the virtual port shown in Fig. 1.
The figure shows an example of a time division multiplex communication system configured using a plurality of conventional time division multiplex devices.
FIG. 7 is a block diagram showing an example of a conventional time division multiplexing device. 15...Port 16...System control unit 17...
Virtual=te-to 22W, 22R... Arres decoding part wing... Memory access control part... memory 111. 112...High speed line 121,12
2... High-speed line interface 131, 132... Time division multiplexing control section agent Patent attorney Book 1) Takashi Fig. 1 Fig. 2 Fig. 3 Fig. 4 Fig. 5 Fig. 1 Dimension Fig. 7

Claims (1)

[Claims] A plurality of ports serving as an interface with a terminal device, a virtual port connected to a bus to which these plural ports are connected, and data of each channel sent from a high-speed line to the port or the virtual port of the corresponding address. a plurality of time division multiplexing control units that time-divisionally write data to ports and time-divisionally read data from the port or the virtual port at an address corresponding to each channel and send it to the high-speed line; and these time division multiplexing control units. 1. A time division multiplexing device comprising: a system control section that arbitrarily sets correspondence between channels and addresses of the ports and virtual ports; and a system control section that controls the entire device.