JPH07250102A - Data transmission circuit - Google Patents

Abstract

PURPOSE:To obtain a data transmission circuit which enables the transmission of sent and received data with extremely short intervals between frames without interrupting data input and output processing and transmission and reception processing. CONSTITUTION:A data input part 1, dual-port memories 3 and 4 where data can be written and read at the same time, a data bus 2 which is used exclusively to write data, a data bus 5 which is used exclusively to read data, and a data transmission part 6 are used. The data input part 1 selects the dual-port memory 3 or 4 at specific intervals of time and writes data in specific units through the data bus 2. The data transmission part 6 selects the dual-port memory 3 or 4 different from the dual-port memory that the data input part 1 has selected and reads data in specific units out through the data bus 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission circuit for transmitting / receiving digital data to / from an external device.

[0002]

2. Description of the Related Art FIG. 4 shows an example of the configuration of a conventional data transmission circuit. FIG. 4A shows a data transmission circuit for converting the frame format of the input data and transmitting it. Further, FIG. 4B is a data receiving circuit for converting the frame format of the received data and outputting the data. Generally, in these circuits, each of the data input unit 1 or the data receiving unit 8, the memory 9, the data transmitting unit 6 or the data output unit 7 is connected to the data bus 10. When transmitting data by the data transmission circuit shown in FIG. 4A, first, the data input unit 1 inputs data to be transmitted, and the data is written into the memory 9 via the data bus 10. After this work is completed, the data transmission unit 6 reads the data from the memory 9 via the data bus 10, converts the data into a predetermined frame format, and then transmits the data. When the data receiving circuit shown in FIG. 4B receives the data, the data receiving unit 8 receives the data and converts the received data into a frame format that can be written in the memory 9. After that, data bus 1
Write to memory 9 via 0. After this work is completed, the data output unit 7 reads data from the memory 9 via the data bus 10 and outputs the data.

[0003]

However, in the conventional data transmission circuit, all the devices are connected to one data bus. Therefore, in the data transmission circuit in FIG. 4A, the data transmission unit 6 cannot read data from the memory 9 while the data input unit 1 is writing data to the memory 9. Therefore, the data cannot be transmitted unless the data input is completed. FIG. 5 is a timing chart showing the time relationship of reading and writing data from and to the memory 9 in the conventional data transmission circuit. In FIG. 5, the timing at which the data input unit 1 writes data to the memory 9 is shown as (a), and the timing at which the data transmission unit 6 reads data from the memory 9 is shown as (b). The shaded area indicates the time when the memory 9 is being accessed.

On the other hand, even in the data receiving circuit shown in FIG. 4B, similarly to the data transmitting circuit shown in FIG. 4A, the data cannot be received unless the output of the data is completed. In this case, (a) in FIG. 5 shows the timing when the data output section 7 reads the data from the memory 9, and (b) shows the timing when the data receiving section 8 writes the data to the memory 9.

As described above, according to the conventional data transmission circuit, data input and data transmission, or data reception and data output cannot be executed simultaneously. Therefore, the actual transmission processing time Tt becomes the total time of the data input / output time and the data transmission / reception time. Further, it is difficult to perform continuous transmission / reception in which there is no interval between frames of transmission / reception data. Further, when it is desired to shorten the interval between frames, there is a problem that sufficient time cannot be taken for data input / output processing. The present invention is
The present invention has been made in the background as described above, and provides a data transmission circuit that does not interrupt data input / output processing and that can transmit / receive data with extremely short intervals between frames. The purpose is to

[0006]

The invention according to claim 1 is
In a data transmission circuit for transmitting / receiving digital data to / from an external device, each of first and second storage means having first and second input / output ports and each of the first and second storage means is provided. Writing means connected to the first input / output port, alternately selecting the first or second storage means at predetermined time intervals, and writing a predetermined unit of digital data to the selected storage means; A storage unit different from the storage unit selected by the writing unit is connected to the second input / output port of each of the second storage units, and a predetermined unit of digital data is selected from the selected storage unit. And a reading means for reading out. According to a second aspect of the present invention, in a data transmission circuit for transmitting / receiving digital data to / from an external device, first and second input / output ports and first and second input / output ports are provided.
Connected to the first input / output port, the first or second storage area is alternately selected at predetermined time intervals, and a predetermined unit of digital data is stored in the selected storage area. Connected to the second input / output port and a storage area different from the storage area selected by the writing means at predetermined time intervals, and a predetermined unit of digital data is selected from the selected storage area. And a reading means for reading out.

[0007]

According to the present invention, the writing means, at predetermined time intervals,
The first or second storage means or the first or second storage area is selected alternately, and a predetermined unit of digital data is written in the selected storage means or storage area. On the other hand, the reading means selects the storage means selected by the writing means, a storage means different from the storage area, or a storage area at predetermined time intervals, and the selected storage means or a predetermined unit of digital data from the storage area. Read out.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A data transmission circuit according to an embodiment of the present invention will be described below. A. Data Transmission Circuit FIG. 1 is a block diagram showing the configuration of the data transmission circuit according to the first embodiment of the present invention. A data input unit 1 is a buffer for inputting data to be transmitted and writing the data in the dual port memory 3 or 4 via the data bus 2. A data transmission unit 6 reads data from the dual port memory 3 or 4 via the data bus 5, converts the frame format and transmits the data.

Next, the operation of the data transmission circuit shown in FIG. 1 will be described. First, the data input unit 1 inputs data, and sequentially writes the data in the dual port memory 3 via the data bus 2. Next, when the data input for one frame is completed, the data input unit 1 inputs the data for the next frame and writes the same data to the dual port memory 4 via the data bus 2. Further, when the data input of this frame is completed, the data input unit 1 inputs the data of the next frame and writes the same data to the dual port memory 3 via the data bus 2. In this way, the dual port memory 3 and the dual port memory 4 are alternately switched and written for each frame.

On the other hand, the data transmission section 6 includes the data input section 1
When writing data to the dual port memory 3, the data is read from the dual port memory 4 via the data bus 5, the frame format of the data is converted and transmitted. When the data input unit 1 is writing data to the dual port memory 4, the data transmission unit 6 reads the data from the dual port memory 3 via the data bus 5 and reads the data. Convert the frame format and send.

FIG. 3 is a timing chart showing a time relationship between data input and data transmission in the first embodiment of the present invention. In the figure, (a) shows the timing when the data input section 1 writes data to the dual port memory 3 or 4, and (b) shows the timing when the data transmission section 6 reads data from the dual port memory 3 or 4. Shows. Further, Tf represents the transmission time of one frame of data, and the shaded portion represents the timing at which the data input unit 1 or the data transmission unit 6 is accessing the dual port memory 3 or 4.

As described above, in the data transmission circuit shown in FIG. 1, the data bus 2 receives the data from the data input unit 1.
Used only to write to dual port memory 3 or 4. Further, the data bus 5 is used only for reading data from the dual port memory 3 or 4 to the data transmission unit 6. Therefore, the data input section 1
Can continuously write data for one frame into the dual port memory 3 or 4, and the processing is not interrupted by the processing of the data transmitting unit 6.
Further, the data transmitting unit 6 can continuously read the data for one frame, and the process is not interrupted by the process of the data input unit 1.

B. Data Reception Circuit FIG. 2 is an example of the configuration of a data reception circuit according to the second embodiment of the present invention. A data receiving unit 8 receives data, converts the frame format of the data, and writes the data in the dual port memory 3 or 4 via the data bus 2. A data output unit 7 is a buffer for reading from the dual port memory 3 or 4 via the data bus 5 and outputting the data.

Next, the operation of the data receiving circuit shown in FIG. 2 will be described. First, the data receiving unit 8 receives data, converts the frame format of the data, and sequentially writes the data in the dual port memory 3 via the data bus 2. Next, when the data reception for one frame is completed, the data receiving unit 8 receives the data for the next frame. further,
The frame format of the received data is converted and written in the dual port memory 4 via the data bus 2.
Further, when the data reception of this frame is completed, the data receiving unit 8 receives the data of the next frame, converts the frame format of the same data, and writes it in the dual port memory 3 via the data bus 2. In this way, the dual port memory 3 and the dual port memory 4 are alternately switched and written for each frame.

On the other hand, the data output section 7 has a data receiving section 8
Is writing data to the dual port memory 3, the dual port memory 4 to the data bus 5
The data is read and output via. Further, the data output unit 7 reads data from the dual port memory 3 via the data bus 5 and outputs the data while the data receiving unit 8 is writing data to the dual port memory 4.

3 (a) also shows the timing when the data output unit 7 is accessing the dual port memory 3 or 4, and FIG. 3 (b) shows that the data receiving unit 8 is dual. The timing of accessing the port memory 3 or 4 is also shown. Further, Tf indicates the transmission time of one frame of data, and the shaded portion also indicates the timing at which the data output unit 7 or the data receiving unit 8 is accessing the dual port memory 3 or 4.

As described above, in the data receiving circuit shown in FIG. 2, the data bus 2 is used only for writing data from the data receiving section 8 to the dual port memory 3 or 4. Further, the data bus 5 is used only for reading data from the dual port memory 3 or 4 to the data output unit 7. Therefore, the data receiving unit 8 can continuously write the data for one frame into the dual port memory 3 or 4, and the process is not interrupted by the process of the data output unit 7. Also,
The data output unit 7 can continuously read data for one frame, and the process is not interrupted by the process of the data receiving unit 8.

By the way, a normal dual-port memory stores data of the same address through two ports.
It is a structure that cannot be accessed at the same time. Therefore, while data is being written in one port, reading is waited at the same address in the other port, and the processing is interrupted. However, according to the present invention, in the dual port memory of one system, data write and read access are not performed at the same time, and therefore the processing is not interrupted.

In the above-mentioned first and second embodiments, two systems of the dual port memory 3 and the dual port memory 4 are provided, and data writing and reading are alternately performed for each frame. Regarding this, one dual-port memory is divided into a storage area corresponding to the dual-port memory 3 and a storage area corresponding to the dual-port memory 4 on the address so that the data bus 2 and the data bus 5 do not simultaneously access the same address. You may divide and use.

[0020]

As described above, according to the present invention, it is possible to perform data input and data transmission after format conversion, or data reception and data output after format conversion independently. Become. Therefore, data input / output processing or data transmission / reception processing is not interrupted, and data transmission with extremely short intervals between frames of transmission / reception data is possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a data transmission circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a data receiving circuit according to a second embodiment of the present invention.

FIG. 3 is a timing chart during data transmission according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional data transmission circuit.

FIG. 5 is a timing chart when data is transmitted by a conventional data transmission circuit.

[Explanation of symbols]

1 ... Data input section, 2 ... Data bus (writing side), 3
... Dual port memory (first system), 4 ... Dual port memory (second system), 5 ... Data bus (read side), 6 ... Data transmission unit, 7 ... Data output unit, 8 ... Data reception unit, 9 ... Memory, 10 ... Data bus.

Claims (2)

[Claims] 1. A data transmission circuit for transmitting and receiving digital data to and from an external device, comprising first and second storage means having first and second input / output ports, respectively, and the first and second storage means. It is connected to each of the first input / output ports of the storage means, and the first or second is connected at predetermined time intervals.
Are alternately connected to the write means for writing a predetermined unit of digital data to the selected storage means, and the second input / output ports of the first and second storage means, respectively, for a predetermined time. A data transmission circuit, comprising: a storage unit different from the storage unit selected by the writing unit, and reading unit for reading out a predetermined unit of digital data from the selected storage unit. 2. A data transmission circuit for transmitting and receiving digital data to and from an external device, comprising: storage means having first and second input / output ports and first and second storage areas; Writing means for connecting to the input / output port of each of the first and second storage areas alternately for a predetermined time and writing a predetermined unit of digital data in the selected storage area; And a reading unit which is connected to the port, selects a storage area different from the storage area selected by the writing unit at predetermined time intervals, and reads a predetermined unit of digital data from the selected storage region. Data transmission circuit.