JPH03283745A - Data collection control system - Google Patents

Abstract

PURPOSE:To eliminate the need for a serial parallel conversion circuit corresponding to a line by writing a serial data from plural lines sequentially in a dual port memory and using a processor so as to read and process the data corresponding to the line from the dual port memory. CONSTITUTION:A serial data fed to an input port of a dual port memory 2 is written according to a write address from an address control circuit 3. In this case, a serial data corresponding to lines 1-1-1-n is not converted into a parallel data in this case but written. Then the data corresponding to the line is read from an output port of the dual port memory 2 by the control of a processor 4. Thus, a serial data is received without provision of the serial parallel conversion circuit to process the data by the processor 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data collection control method for collecting and processing serial data from multiple locations.

Data obtained from various distributed devices,
Sends the status information etc. of the device to the center via the line,
A system is known in which the center collects and processes data transmitted via each line, and the data is transmitted serially via the lines, and at the center it is processed by a processor. , will be processed as parallel data. Therefore, a means for serial-parallel conversion of collected data is required. There is a demand for economicalization of the configuration for collecting such data.

[Conventional technology]

FIG. 4 is a block diagram of a conventional example, 31-1 to 31-
n is the line, 32-1=32-n is the serial-parallel conversion circuit (S
/P), 33-1 to 33-n are direct memory access control circuits (DMAC), 34 is a common bus, 35 is a microprocessor (MPU), 36 is a memory, and 37 is an interrupt controller.

Data detected by various distributed devices (not shown) or status information of various devices is transmitted as serial data to each line 31-1 to 31-n.
Each of the data is converted into parallel data of 8 bits or 16 bits corresponding to the bus width of the common bus 34 by the serial/parallel conversion circuits 32-1 to 32-n, and the interrupt signals IR1 to IRn are sent to the interrupt controller 37 for each conversion process. or a DMA (direct memory access) request is sent.

Interrupt signal IR from serial/parallel conversion circuits 32-1 to 32-n
When sending I to IRn, the interrupt signal selected by the interrupt controller 37 is applied to the microprocessor 35, and the microprocessor 35 connects the common bus 34 from the serial/parallel converter circuit corresponding to the interrupt signal. Parallel data is read through the memory 36 and written to the line corresponding area of the memory 36.

In addition, when sending a DMA request from the serial/parallel conversion circuits 32-1 to 32-n, a bus request is sent from the direct memory access control circuits 33-1 to 33-n to the microprocessor 35, and the microprocessor 35 transfers the bus request to the microprocessor 35. When the permission signal for the request is sent, the direct memory access control circuit writes the converted parallel data to the memory 360 line corresponding area via the common bus 34.

Therefore, data corresponding to the lines 31-1 to 31-n is written into the memory 36, and the processor 35 judges the data detected by the various devices or monitors the status of the various devices.

[Problem 3 to be solved by the invention: When data is transmitted through the lines 31-1 to 31-n, it is serial transmission, and when it is processed by a processor, parallel data is transmitted according to the number of bits processed by the processor. will be converted to . For this purpose, serial/parallel conversion circuits 32-1 to 32-n are provided for lines 31-1 to 31-n.
Since it is necessary to provide 32-n, there is a disadvantage that as the number of lines increases, the configuration becomes large and complicated. Furthermore, the converted parallel data is written to the memory 36 through the processor or by occupying the common bus 34, which has the disadvantage of reducing the throughput of the processor.

SUMMARY OF THE INVENTION An object of the present invention is to make the device smaller and more economical, and to prevent the throughput of the processor from decreasing.

[Means to solve the problem]

The data collection control method of the present invention uses a dual port memory and will be explained with reference to FIG.

A dual port memory 2 that inputs synchronized serial data from multiple lines 1-1 to 1-n in batches for each number of input ports, and a write address of this dual port memory 2 that corresponds to the bits of the serial data. It is equipped with an address control circuit 3 for incrementing, and a processor 4 for reading and processing data corresponding to a line from the output port of this dual port memory 2, and for processing serial data from a plurality of lines 1-1 to 1-n. After being written into the memory 2, it is read out and processed under the control of the processor 4.

[Effect]

Serial data applied to the input port of dual port memory 2 is written in accordance with the write address from address control circuit 3. In this case, serial data corresponding to lines 1-1 to 1-n will be written without being converted into parallel data. Since data corresponding to the line can be read from the output port of the dual port memory 2 under the control of the processor 4, serial data can be received and processed by the processor 4 without providing a serial/parallel conversion circuit. .

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, and 11-1
~11-n is the line, 12 is dual port memory, 13
are timing circuits including address control circuits, 14-1~
14-m is a data receiver, 15 is a common bus, 16 is a processor, and LGI-LGm is a line group.

The dual port memory 12 has eight ports PTI and PT2 on one side and eight ports on the other side, and an address terminal ADI,
AD2, read enable terminals *R1, *R2, and write enable terminals *Wl, *W2. For example, when a write enable signal is applied to the write enable terminal *W1, the signal is applied to the port PT1. When data is written and a read enable signal is applied to the read enable terminal *R2,
Data is read from port PT2.

In addition, the timing circuit 13 connects the lines 11-1 to 11-n to 8
Outputs transmit enable signals FPI to FPm corresponding to line groups LGI to LGm for each line and a transmission clock signal SCK for synchronizing serial data, and outputs signals to data receivers 14-1 to 14-m. It has a configuration that outputs a timing signal for latching data, outputs an address signal to be applied to the address terminal ADI of the dual port memory 12, and outputs a read enable signal or a write enable missing signal. For example, the ready-to-send signal F
Contents include a counter that counts up the transmission clock signal SCK by PI-FPm, increments corresponding to the bits of the serial data, and designates an area corresponding to the line groups LGI to LGm in correspondence to the transmission enable signals FPI to FPm. Become.

Furthermore, the devices (not shown) connected via the lines 11-1 to 11-n start transmitting data in response to a transmission enable signal, and transmit data serially in synchronization with the transmission clock signal SCK. It has a structure.

Therefore, the timing circuit 13 sends the transmittable signals FP1 to F.
Serial data is transmitted in synchronization with the transmission clock signal SCK from devices connected to the lines of the line group LGI to LGm from which Pm was sent. For example, if the send ready signal FPI and the transmission clock signal SCK are Line 11-1
~11-8, the serial data synchronized with the transmission clock signal is sent to the data receiver 14- via lines 11-1 to 11-8.
1, is latched by the timing signal from the timing circuit 13, and the latch output is applied to the port (PTI) of the dual port memory 12, and the latch output is applied to the port PTI of the dual port memory 12.
A write enable signal is applied to the write enable terminal *Wl from 3, and an address signal is applied to the address terminal ADI. The first bit of serial data is written.

Then, when the second bit of the serial data synchronized with the transmission clock signal SCK is latched by the data receiver 14-1 by the timing signal, the address signal applied to the address terminal ADI is incremented, and the area corresponding to the line group LGI is incremented. For example, the second bit of eight serial data from lines 11-1 to 11-8 is written to address 2. Thereafter, serial data of a predetermined number of bits is written in the area corresponding to the line group LGI of the dual port memory 12 in the same manner.

Then, when transmitting ready signal FP2 and transmission clock signal SCK are sent to the devices connected to lines 11-9 to 11-16 of line group LG2, serial data is transmitted via lines 11-9 to 11-16. It is input to the receiver 14-2, latched by the timing signal, and the latch output is applied to the port PTI of the dual port memory 12.
Line group L by the address signal from the timing circuit 13
The first bit of eight pieces of serial data is written, for example, at address 1 in the area corresponding to G2.

Serial data can be similarly collected for line group LGm and written in the area of dual port memory 12 corresponding to line group LGm.

The processor 16 applies a read enable signal to the read enable terminal *R of the dual port memory 12, and also adds an address signal for reading data of the desired lines 11-1 to 11-n to the address terminal AD2. 8 bits can be read in parallel from port PT2.

FIG. 3 is an explanatory diagram of the operation of the embodiment of the present invention, (a),
(e) is the send ready signal FPI, FP2, (b) is the transmission clock signal SCK, (C), (b) is an example of the serial data corresponding to the line of line group LGI, (f), @ is the signal of line group LG2. An example of serial data corresponding to a line, (c) shows an address signal. Transmission ready signal FPI shown in (a) and transmission clock signal SC shown in (b) for line group LGI
K, serial data is transmitted through the lines of the line group LGI, and eight first bits are latched in the data receiver 14-1. The address signal All shown in (Company) is applied to the address terminal ADI of the dual port memory 12, and the first bit of eight pieces of serial data, some of which are shown in (C) and (A), is transferred to the dual port memory 12. written.

Next, when the second bit is latched into the data receiver 14-1, eight second bits are written into the dual port memory 12 by the address signal A12. Thereafter, the serial data corresponding to the line of line group LGI is written in the dual port memory 12 in the same way, and then the send enable signal FP2 shown in (e) and the transmission clock signal SCK shown in (b) for line group LG2 are sent. By being sent, line group L
When the serial data corresponding to the G2 line is transmitted and the data receiver 14-2 latches the eight first bits (part of which are shown in (f) and @), the address signal A21 shown in (c) causes the dual Port memory 12 line group LG
Eight first bits are written to the first address of the area corresponding to the second bit. Thereafter, the address signal is incremented in the same manner, and the line group L
Serial data corresponding to the G2 line is written to the dual port memory 12.

As mentioned above, serial data from multiple lines can be written to dual-port memory 12 without intervention from processor 16, and processor 16 can optionally read line-specific data from dual-port memory 12. Therefore, the throughput of the processor 16 is not reduced. Furthermore, serial data can be received and processed by the processor 16 without providing a serial/parallel conversion circuit for each line.

The above-mentioned embodiment shows a case where transmittable signals FPI to FPm are sequentially transmitted to each of the line groups LGI to LGm, but the transmittable signals FPI to FPm are simultaneously transmitted to the data receivers 14-1 to 14-1. Line group LGI~L in 14-m
It is also possible to latch the signal using a high-speed latch signal whose timing differs depending on Gm, and to write it into the dual port memory 12. In this case, the latch output is reset upon completion of writing, and the writing operation of the dual port memory 12 is performed for the number of line groups LGI to LGm within one bit time of serial data.

〔Effect of the invention〕

As explained above, the present invention provides a plurality of lines l-1 to l-1.
Serial data from -n is sequentially written to the dual port memory 2, and the processor 4 reads line-compatible data from the dual-port memory 2 and processes it, eliminating the need for a line-compatible serial/parallel converter circuit as in the conventional example. Therefore, economicalization can be achieved. Furthermore, since the dual port memory 2 is realized by a relatively large capacity semiconductor integrated circuit, the device can be made smaller.

Further, serial data can be written to the dual port memory 2 without the intervention of the processor 4, and the processor 4 can read and process data from the dual port memory 2 as necessary. This has the advantage that there is no reduction in throughput.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of the operation of an embodiment of the present invention.
FIG. 4 is a block diagram of a conventional example. 1-1 to 1-n are lines, 2 is dual port memory, 3
4 is an address control circuit, and 4 is a processor.

Claims (1)

[Scope of Claims] A dual port memory (2) into which synchronized serial data from a plurality of lines (1-1 to 1-n) are collectively input for each number of input ports;
an address control circuit (3) that increments the write address of 2) in correspondence with the bits of the serial data; and a processor (4) that reads and processes data corresponding to the line from the output port of the dual port memory (2).
The serial data from the plurality of lines (1-1 to 1-n) is written in the dual port memory (2) and then read out and processed under the control of the processor (4). Data collection control method.