JPS629458A - Multi-cpu system bus - Google Patents

Abstract

PURPOSE:To perform transmission/reception of data between multi-CPU systems for each byte or block with no collision of data, by using a means which performs the general communication to all slave CPU systems and carries out transmission/reception of data with the slave CPU system having the transmission/reception right. CONSTITUTION:A master CPU system 11 sets a designated address of an interface part 12 to an address bus and therefore one or all interface parts 12 are activated. When data are transmitted to the slave CPU systems 13 from the system 11, the part 12 fetches data by a writing action carried out at the side of the system 11 and informs the existence of data to the system 13. Then the fetched data are delivered by a data reading action at the side of the system 13. The write and read inhibiting signals are controlled for each byte or block and the transmission of data is possible every plural bytes. Furthermore a series of data can be transmitted to the system 11 from the system 13 by repeating the above-mentioned operations.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a data collection device, a switching device, and a transmission control device that need to send and receive data and collect and transfer information between a plurality of CPUs. Related to system buses in devices, multiplexing devices, etc.

(Conventional technology) Conventionally, in this type of multi-CPU system.

Each communicating pair is equipped with an 8255-type motherboard input/output port, and one is used for data transmission from the master to the slave, and the other is used for data transmission from the slave to the master. It is configured to allow bidirectional data transmission.

In FIG. 2, reference numeral 22 is an interface unit equipped with an 8255 type Noclarel input/output port.

Next, the operation of the above conventional example will be explained. In Figure 2, ・Glarel input/output, I? -) The left side of 22 is connected to the master CPU system 21, and the right side is connected to the slave CPU system 23.

Data transmission from the master to the slave is performed by writing from the master, the buffer unit latches the data, prohibits writing to the master side, notifies the slave side that there is received data, and reads from the slave, the buffer unit latches the data on the master side. All write protection is removed and data is no longer sent to the slave side.

The same applies to data transmission from the slave to the master, and by repeating the above operations, data can be transmitted and received in units of bytes.

In this way, even the conventional multi-CPU system described above can perform bidirectional data transmission.

(Problems to be solved by the invention) However, in the above conventional multi-CPU system,
Problems include: port selection signals and data write enable/disable signals are required for each slave CPU, making it impossible to accommodate multiple slave CPU systems; block transfer is not possible due to the use of buffers; and simultaneous communication from master to slave is not possible. was there.

The present invention is intended to solve these conventional problems, and aims to provide an excellent multi-CPU system bus that can accommodate a large number of slave CPU systems and also perform block transfer and simultaneous communication. It is.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides
Setting the address signal for system selection is individual communication, −
Multi-slave C is a contention method that facilitates simultaneous communication and uses a common interrupt line for transmission requests from slaves.
This makes it easy to accommodate the PU system and allows block transfer using memory.

(Function) The present invention has the following functions in addition to the above configuration. In other words, by setting the address of any slave by the master, data can be sent and received between individual slaves, and by setting a simultaneous address, data can be sent from the master to the slaves all at once, and transmission requests from slaves are sent to the common side system. It is possible to notify the master using a contention method using a wire.

(Example) FIG. 1 shows the configuration of an embodiment of the present invention.

In FIG. 1, 11 is a master CPU system,
It is connected via an interface section 12 to a system 13 consisting of a plurality of slave CPUs.

Next, the operation of the above embodiment will be explained. Master CPU
When the system 11 sets the specified address of the interface unit 12 to the address bus, one or all the interface units 12 are activated, and data transmission from the master CPU system 11 to the slave CPU system 13 is performed by writing from the master side. Accordingly, the interface section 12 takes in the data, notifies the slave side 13 of the presence of the data, and outputs the data that has been taken in by the data reading operation on the slave side. By controlling the write inhibit and read inhibit signals in units of 1 byte or in units of blocks, transmission in units of multiple bytes becomes possible.

The basic operation is the same for transmission from the slave CPU system 13 to the master CPU system 11, and by repeating the above operation, it is possible to transmit a series of data.

The transmission request from the slave CPU system 13 is a contention method, and the corresponding slave CPU system 1 is sent by polling the status from the vector or the master.
3 can be detected.

In this way, according to the above embodiment, by setting the specified address, the master CPU system 11 can perform 1=1 or simultaneous data transmission with any slave CPU system 13, and write to the data memory is prohibited. This has the advantage that block transfer can be performed by controlling the read inhibit signal.

(Effects of the Invention) As is clear from the above examples, the present invention has the following effects.

(1) By providing an address signal line for selecting a slave CPU system and using a common line system for interrupt signals, it is possible to accommodate multiple slave CPU systems.

(2) Master/slave C is controlled by the address signal line.
Individual communication and simultaneous communication between PU systems is possible.

(3) Block transfer is possible by controlling write-inhibit and read-inhibit signal lines and data memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a multi-CPU system according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional multi-CPU system. DESCRIPTION OF SYMBOLS 11... Master CPU system, 12... Interface unit, 13... Slave CPU system, 21.
. . . Master CPU system, 22 . . . Interface section, 23 . . . Slave CPU system. Figure 1

Claims (1)

[Claims] In a CPU interface used in a multi-CPU system that operates asynchronously, data communication requests from multiple slaves are processed by polling or interrupt information under the control of the master between one master and multiple slaves. means for detecting and setting the right to send and receive data to the slave for which a communication request has occurred through selection, a means for simultaneously communicating to all slaves, and a means for sending and receiving data to the slave for which the right to send and receive is set. What is claimed is: 1. A multi-CPU system bus comprising means for transmitting and receiving data, and transmitting and receiving data between multiple CPUs in units of bytes or blocks without data collision.