FR2449928A1 - Data processing system with transfer through interface - has CPU, principal memory, several bus lines and bidirectional data transfer method using interrupts - Google Patents

Data processing system with transfer through interface - has CPU, principal memory, several bus lines and bidirectional data transfer method using interrupts

Info

Publication number
FR2449928A1
FR2449928A1 FR8001951A FR8001951A FR2449928A1 FR 2449928 A1 FR2449928 A1 FR 2449928A1 FR 8001951 A FR8001951 A FR 8001951A FR 8001951 A FR8001951 A FR 8001951A FR 2449928 A1 FR2449928 A1 FR 2449928A1
Authority
FR
France
Prior art keywords
cpu
bus lines
interface
transfer
interrupts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR8001951A
Other languages
French (fr)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Italia SpA
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Italia SpA, Honeywell Information Systems Inc filed Critical Honeywell Information Systems Italia SpA
Publication of FR2449928A1 publication Critical patent/FR2449928A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Abstract

The system relates to the exchange of information between a central processing unit (CPU) and a number of peripherals, such as teleprinters, magnetic tapes or discs. There is bi-directional transfer through an interface. An input unit is connected directly to the CPU which has two bus lines (A, B) each with peripherals (206, 212); (214,222). The centrals processor has 64 k words, as is connected with a first principal memory with 48 k words and a second principal memory with 16 k words. Information is transferred to the first unit, and then to successive units in response to signals from a microprogramme, which may interrupt the operations of the various units in order to divert information along one of the common bus lines.
FR8001951A 1979-01-31 1980-01-30 Data processing system with transfer through interface - has CPU, principal memory, several bus lines and bidirectional data transfer method using interrupts Withdrawn FR2449928A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US812279A 1979-01-31 1979-01-31

Publications (1)

Publication Number Publication Date
FR2449928A1 true FR2449928A1 (en) 1980-09-19

Family

ID=21729897

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8001951A Withdrawn FR2449928A1 (en) 1979-01-31 1980-01-30 Data processing system with transfer through interface - has CPU, principal memory, several bus lines and bidirectional data transfer method using interrupts

Country Status (5)

Country Link
JP (1) JPS55103621A (en)
AU (1) AU5497280A (en)
BE (1) BE881408A (en)
CA (1) CA1141866A (en)
FR (1) FR2449928A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111782743B (en) * 2020-06-08 2024-03-22 上海飞未信息技术有限公司 Space data management method in cloud computing environment

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3688274A (en) * 1970-12-23 1972-08-29 Ibm Command retry control by peripheral devices
FR2240482A1 (en) * 1973-08-06 1975-03-07 Siemens Ag

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3688274A (en) * 1970-12-23 1972-08-29 Ibm Command retry control by peripheral devices
FR2240482A1 (en) * 1973-08-06 1975-03-07 Siemens Ag

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ELECTRONIC DESIGN, vol. 23, no. 23, 8 novembre 1975, pages 70-75, Rochelle Park (USA); *

Also Published As

Publication number Publication date
BE881408A (en) 1980-05-16
JPS55103621A (en) 1980-08-08
CA1141866A (en) 1983-02-22
AU5497280A (en) 1980-08-07

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