AU5497280A - Synchronous bus wait/retry cycle apparatus - Google Patents
Synchronous bus wait/retry cycle apparatusInfo
- Publication number
- AU5497280A AU5497280A AU54972/80A AU5497280A AU5497280A AU 5497280 A AU5497280 A AU 5497280A AU 54972/80 A AU54972/80 A AU 54972/80A AU 5497280 A AU5497280 A AU 5497280A AU 5497280 A AU5497280 A AU 5497280A
- Authority
- AU
- Australia
- Prior art keywords
- cycle apparatus
- synchronous bus
- bus wait
- retry cycle
- retry
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US812279A | 1979-01-31 | 1979-01-31 | |
US008122 | 1979-01-31 |
Publications (1)
Publication Number | Publication Date |
---|---|
AU5497280A true AU5497280A (en) | 1980-08-07 |
Family
ID=21729897
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU54972/80A Abandoned AU5497280A (en) | 1979-01-31 | 1980-01-25 | Synchronous bus wait/retry cycle apparatus |
Country Status (5)
Country | Link |
---|---|
JP (1) | JPS55103621A (en) |
AU (1) | AU5497280A (en) |
BE (1) | BE881408A (en) |
CA (1) | CA1141866A (en) |
FR (1) | FR2449928A1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111782743B (en) * | 2020-06-08 | 2024-03-22 | 上海飞未信息技术有限公司 | Space data management method in cloud computing environment |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3688274A (en) * | 1970-12-23 | 1972-08-29 | Ibm | Command retry control by peripheral devices |
GB1480781A (en) * | 1973-08-06 | 1977-07-27 | Siemens Ag | Data processing system |
-
1980
- 1980-01-25 AU AU54972/80A patent/AU5497280A/en not_active Abandoned
- 1980-01-29 BE BE0/199157A patent/BE881408A/en not_active IP Right Cessation
- 1980-01-30 FR FR8001951A patent/FR2449928A1/en not_active Withdrawn
- 1980-01-31 JP JP950680A patent/JPS55103621A/en active Pending
- 1980-01-31 CA CA000344828A patent/CA1141866A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS55103621A (en) | 1980-08-08 |
CA1141866A (en) | 1983-02-22 |
BE881408A (en) | 1980-05-16 |
FR2449928A1 (en) | 1980-09-19 |
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